KR970009057A - High-speed serial communications link for desktop computer peripherals - Google Patents

Abstract

The described system is to provide a reconfigurable serial connection in a processor to either a workstation or a server and a user-categorized I / O device such as a video display terminal, storage device and other peripherals. Maintainable I / O throughput above 1 Gbps supports the needs of displays and video devices. The system also allows for hot plug-and-play of user-classified I / O devices.

Description

High-speed serial communications link for desktop computer peripherals

Since this is a trivial issue, I did not include the contents of the text.

Figure 1 shows a general desktop computer configured using the techniques described herein, Figure 2A shows an overall topology of a ring communication system, Figure 2B shows a link module, Lt; / RTI >

Claims (11)

CLAIMS What is claimed is: 1. A communication system between a plurality of peripherals coupled to a processor, the system comprising: a downstream communication path coupled to the processor, the downstream communication path extending from the processor to enable the processor to transmit data to the peripheral; A serial communication ring that provides an upstream path from the peripheral to the processor to enable data to be transmitted to the processor; And a plurality of modules coupled to the ring, each module including a pair of bidirectional communication ports for providing a connection to the ring for at least one peripheral device and for connecting the module to both the upstream path and the downstream path The communication system comprising: 2. The method of claim 1, wherein the data is transmitted on the ring to cells addressed by a source to a property destination, each module comprising: Release the first portion of the cell for later use with another module when the data is read from the ring by the addressed peripheral device and not release at least one cell with transmission addressed to the peripheral device Logic, whereby the data in the at least one cell that is not released by the peripheral device is correctly received by the addressed peripheral device. 3. The communication system of claim 2, wherein the logic releases all cells except the first and last cells. 4. The communication system of claim 3, wherein the logic in the source at the source releases all cells in the module of the destination that were not released by the logic. CLAIMS What is claimed is: 1. A communication system between a plurality of peripherals coupled to a processor, the system comprising: a downstream communication path coupled to the processor, the downstream communication path extending from the processor to enable the processor to transmit data to the peripheral; A serial communication ring for providing an upstream path from the peripheral to the processor to enable data to be transmitted to the processor; Wherein said peripheral device is coupled to said ring to release a first portion of said cell for later use with another module when said data is read from said ring by said addressed peripheral, Each of the plurality of modules holding logic on the ring as an indication to the source that the data in the at least one cell that has not been released by the peripheral has been correctly received The communication system comprising: 6. The communication system according to claim 5, wherein the logic releases all cells except the first and the last cell. 7. The communications system of claim 6, wherein the logic in the source at the source releases all cells in the module at the destination that are not released by the logic. CLAIMS What is claimed is: 1. A communication system between a plurality of peripherals coupled to a processor, the system comprising a predetermined number of cells and coupled to the processor, the processor extending from the processor to enable data to be transmitted to the peripheral device A serial communication link that provides an upstream path from the peripheral device to the processor to enable the peripheral device to transmit data to the processor; Wherein each of the modules is coupled to the ring to provide a connection to the ring for at least one peripheral device, one of the modules being used as a master module to allocate the predetermined number of cells, Each module being assigned a new module that is connected to the ring every hour; Each module comprising transmit logic for placing data on the ring when an empty cell is present and setting a particular bit already used when no empty cell is present; Each of the modules including receive logic for decreasing use of the cell to the minimum number when detecting that the particular bit is set by another module. A communication system between a peripheral device comprising a video display device coupled to a computer processor, the communication system comprising: a fiber optic cable coupled to the computer processor via a host interface; a first link module coupled to the fiber optic cable and the video display device; A twisted pair of cables coupled to the fiber optic cable and extending to the at least one second link module and an additional computer peripheral coupled to the at least one second link module. 10. The apparatus of claim 9, wherein the at least one second link module comprises a plurality of link modules serially interconnected by a twisted pair of cables, and a separate computer peripheral device connected to each link module Communication system. 11. The apparatus of claim 10, wherein the first link module comprises: First and second bidirectional ports coupled to the fiber optic cable to permit communication between the video display coupled to the link module and to the peripheral device coupled to each of the ports to allow the communication to be coupled to the module And a router for selecting whether or not the wireless communication apparatus is connected to the communication network. ※ Note: It is disclosed by the contents of the first application.