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KR970008523A - Semiconductor Package Heat Sink Structure - Google Patents

Semiconductor Package Heat Sink Structure Download PDF

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Publication number
KR970008523A
KR970008523A KR1019950019583A KR19950019583A KR970008523A KR 970008523 A KR970008523 A KR 970008523A KR 1019950019583 A KR1019950019583 A KR 1019950019583A KR 19950019583 A KR19950019583 A KR 19950019583A KR 970008523 A KR970008523 A KR 970008523A
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KR
South Korea
Prior art keywords
heat sink
semiconductor chip
bulk
kappa
semiconductor package
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KR1019950019583A
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Korean (ko)
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KR0159985B1 (en
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신원선
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황인길
아남산업 주식회사
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Priority to KR1019950019583A priority Critical patent/KR0159985B1/en
Publication of KR970008523A publication Critical patent/KR970008523A/en
Application granted granted Critical
Publication of KR0159985B1 publication Critical patent/KR0159985B1/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

본 발명은 반도체 패키지 히트싱크구조에 관한 것으로, 일반적으로 히트 싱크 내장형 반도체 패키지에서는 반도체 칩(1)에서 그라운드를 형성할때 반도체 칩(1)이 본딩된 히트싱크(2)의 표면에 본딩을 하는 것으로, 종래의 히트싱크(2)는 반도체 칩(1)의 회로동작시 발생하는 열을 외부로 방출하는 것을 목적으로 전기전도성과 열방출 효율이 우수한 카파(Cu)의 벌크(BULK)로 형성하였던 바, 이러한 카파벌크 히트싱크(2)에는 골드와이어(3)의 본딩이 불가능하여 그 표면에 은(Ag)을 도금하여 상부에 골드와이어(3)를 그라운드 본딩하였으나, 이는 히트싱크(2) 상부에 도금된 은에 의해서 그 접착력이 불량하게 되는 문제점이 있었던 바, 본 발명은 히트싱크로 사용되는 카파벌크 상부에는 그라운드 골드와이어(3) 부착층으로서니켈층(5)을 형성하고, 상기 니켈층(5)의 산화를 방지하며 반도체 칩(1) 접착용 에폭시(4)와의 접착력이 우수한 팔리디움층(6)을 형성하여 히트싱크(2)상에 반도체 칩(1)을 견고히 부착되도록 하며, 그라운드 본딩시 골드와이어(3)의 본딩 결합력을 향상시키고, 아울러서 카파벌크 바로 위에 카파 스트라크층(8)을 형성하므로 블리스터로 인한 부가층들간의 계면박리를 없앨수 있는 등의 효과가 있는 반도체 패키지 히트싱크구조이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package heat sink structure. In general, in a heat sink-embedded semiconductor package, when the ground is formed in the semiconductor chip 1, the semiconductor chip 1 bonds to the surface of the heat sink 2 to which the semiconductor chip 1 is bonded. In the conventional heat sink 2, the heat sink 2 is formed of bulk BULK of Cu, which is excellent in electrical conductivity and heat dissipation efficiency, for the purpose of dissipating heat generated during the circuit operation of the semiconductor chip 1 to the outside. The kappa bulk heatsink 2 was not bonded to the gold wire 3, and silver (Ag) was plated on the surface thereof to ground bond the gold wire 3 to the top. Since the adhesion strength becomes poor due to the silver plated on the bar, the present invention forms a nickel layer (5) as an adhesion layer of the ground gold wire (3) on the upper kappa bulk used as a heat sink, and the nickel layer ( 5) Prevents oxidation and forms a palladium layer 6 having excellent adhesion to the epoxy 4 for bonding the semiconductor chip 1 so that the semiconductor chip 1 is firmly attached to the heat sink 2 and gold when ground bonding. The semiconductor package heat sink structure has the effect of improving the bonding strength of the wire 3 and, at the same time, forming the kappa strike layer 8 directly on the kappa bulk, eliminating interfacial separation between the additional layers due to blisters. .

Description

반도체 패키지 히트싱크구조Semiconductor Package Heat Sink Structure

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명의 제1실시예에 따른 히트싱크의 요부 확대 단면도, 제3도는 본 발명의 제1실시예에 따른 와이어 본딩 상태의 요부 확대 단면도.2 is an enlarged cross-sectional view of a main portion of a heat sink according to a first embodiment of the present invention, and FIG. 3 is an enlarged cross-sectional view of a main portion of a wire bonding state according to a first embodiment of the present invention.

Claims (5)

카파벌크를 히트싱크로서 반도체 칩 하부에 부착시켜 사용하는 반도체 패키지 히트싱크구조에 있어서, 상기 카파벌크 히트싱크 상부에 니켈층을 형성하고, 상기 니켈층의 상부로 니켈층 산화를 방지하는 팔라디움층이 형성된 것을 특징으로 하는 반도체 패키지 히트싱크구조.In a semiconductor package heat sink structure in which kappa bulk is attached to a lower portion of a semiconductor chip as a heat sink, a palladium layer is formed on top of the kappa bulk heat sink, and a nickel layer is prevented on top of the nickel layer. A semiconductor package heat sink structure, characterized in that formed. 제1항에 있어서, 상기 카파벌크 히트싱크와 니켈층 사이에 카파 스트라이크층이 형성된 것을 특징으로 하는 반도체 패키지 히트싱크구조.The semiconductor package heat sink structure of claim 1, wherein a kappa strike layer is formed between the kappa bulk heat sink and the nickel layer. 제1항 또는 제2항에 있어서, 상기 니켈층은 30 마이크로 인치 이상의 두께로 형성됨을 특징으로 하는 반도체 패키지 히트싱크구조.3. The semiconductor package heat sink structure of claim 1 or 2, wherein said nickel layer is formed to a thickness of 30 micro inches or more. 제1항 또는 제2항에 있어서, 상기 팔라디움층은 3마이크로 인치 이상의 두께로 형성됨을 특징으로 하는 반도체 패키지 히트싱크구조.3. The semiconductor package heat sink structure of claim 1 or 2, wherein said palladium layer is formed to a thickness of at least 3 micro inches. 제1항 또는 제2항에 있어서, 상기 니켈층은 팔라디움층의 두께 보다 두꺼운 것을 특징으로 하는 반도체 패키지 히트싱크구조.The semiconductor package heat sink structure according to claim 1 or 2, wherein the nickel layer is thicker than the thickness of the palladium layer. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950019583A 1995-07-05 1995-07-05 Semiconductor Package Heat Sink Structure Expired - Lifetime KR0159985B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950019583A KR0159985B1 (en) 1995-07-05 1995-07-05 Semiconductor Package Heat Sink Structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950019583A KR0159985B1 (en) 1995-07-05 1995-07-05 Semiconductor Package Heat Sink Structure

Publications (2)

Publication Number Publication Date
KR970008523A true KR970008523A (en) 1997-02-24
KR0159985B1 KR0159985B1 (en) 1998-12-01

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100547391B1 (en) * 2003-10-23 2006-01-31 (주)동양기연 Manufacturing method of heat sink for semiconductor package mounting
KR100712837B1 (en) * 2004-04-29 2007-05-02 엘지전자 주식회사 Heat sink and surface treatment method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100547391B1 (en) * 2003-10-23 2006-01-31 (주)동양기연 Manufacturing method of heat sink for semiconductor package mounting
KR100712837B1 (en) * 2004-04-29 2007-05-02 엘지전자 주식회사 Heat sink and surface treatment method

Also Published As

Publication number Publication date
KR0159985B1 (en) 1998-12-01

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