KR970007675A - Programmable Data Match Detection Circuit - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a programmable data match detection circuit, comprising: a first input register section for receiving and storing n bits of data from a data bus; and a second input register for receiving and storing another n bits of data from a data bus. A counter and a counter unit for counting up to 2 ²ⁿ and outputting to the comparison unit for comparison with n-bit data of the two input register units, and receiving the output signals of the counter unit for n-bit data of the two input register units. A comparison unit for comparing two data to generate a comparison match signal, a program register unit for controlling a mask time for controlling a final match signal by a program, a comparison match signal generated by the comparison unit and the program register unit Mask that controls the presence or absence of the final match signal with the output signal And a programmable data coincidence detection circuit configured to generate a data coincidence detection output only within a predetermined time period by inputting a desired time interval in advance programmatically.

Description

Programmable Data Match Detection Circuit

Since this is an open matter, no full text was included.

2 is a circuit diagram of a programmable data match detection circuit according to an embodiment of the present invention, FIG. 3 is a circuit diagram of a mask unit circuit according to an embodiment of the present invention, and FIG. 4 is a mask part circuit according to an embodiment of the present invention. Is a timing diagram.

Claims (5)

A first input register section for receiving and storing n-bit data from the data bus, a second input register section for receiving and storing another n-bit data from the data bus, and n of the first and second input register sections. A counter unit for counting up to 2 ²ⁿ and outputting the number to 2 ²ⁿ to a comparison unit, and receiving n-bit data of the first and second input register units and an output signal of the counter unit, and comparing the two data. A coincidence signal having a comparator for generating a comparison coincidence signal, a program register for adjusting a mask time for controlling a final coincidence signal with a program, a comparison coincidence signal generated at the comparator and an output signal of the program register section Programmable data coincidence detection, characterized in that the mask portion for controlling the output of the Circuit. 2. The apparatus of claim 1, wherein the mask unit comprises: a first logical means for receiving the first bit of the output of the program register and the output of the comparator; a second bit for receiving the second bit of the output of the program register and the output of the comparator; A third logical means for receiving an AND and a third bit of the output of the program register and an output of the comparator, a fourth logical means for receiving an output of the comparator and a fourth bit of the output of the program register; A first negative OR that takes as an input the output of the first logical AND means and an output of the second negative OR, and a second negative OR that uses the output of the second logical AND and the output of the first negative AND Means, third negative AND means for inputting the output of the third AND logic means and an output of the fourth AND logic means, and the fourth logical AND means A fourth negative logical sum means for inputting the output and the output of the third negative logical sum means, a fifth logical multiplication means for inputting a comparison coincidence signal with the output signal X of the first negative logical sum means, and the third A sixth logical means for inputting a comparison coincidence signal and an output signal (Y) of a negative-orthogonal means; and a logical sum for generating a final coincidence signal as an input of the outputs of the fifth logical and sixth logical means. A data coincidence detecting circuit comprising means. 3. The programmable data match detection circuit according to claim 2, wherein the first to sixth logical products comprise an AND gate. 3. The programmable data match detection circuit according to claim 2, wherein the first to fourth negative logic means comprise a NOR gate. 3. The programmable data match detection circuit according to claim 2, wherein the logical sum means comprises an OR gate. ※ Note: The disclosure is based on the initial application.