KR970004817B1 - Method of manufacturing semiconductor device - Google Patents

Abstract

No content.

Description

Semiconductor device and manufacturing method

1 is a cross-sectional view showing the configuration of main parts of a semiconductor device according to the first embodiment of the present invention.

2 is a cross-sectional view for explaining the manufacture of the main part according to the first embodiment.

3 is a cross-sectional view showing the configuration of a main part of a semiconductor device according to a second embodiment of the present invention.

4 is a cross-sectional view of a semiconductor device showing still another embodiment of the present invention.

5 is a cross-sectional view illustrating a method of manufacturing the embodiment shown in FIG.

6 is a characteristic diagram showing the change in the boron concentration distribution according to the depth of the polyside wiring in contact with the semiconductor substrate.

7 is a characteristic diagram showing the change of the p-type contact resistance with the passage of the annealing time.

8 is a plan view showing a sample for evaluating lateral diffusion.

9 is a characteristic diagram showing the relationship between the interval D and the p-type contact resistance of the sample of FIG.

10 is a characteristic diagram showing the change in the boron concentration distribution according to the depth of the polyside wiring.

11 is a characteristic diagram showing a change in the arsenic concentration distribution according to the depth of the polyside wiring.

12 is a characteristic diagram showing a change in an n-type contact resistance as the annealing time elapses.

13 is a characteristic diagram showing the change of impurity concentration distribution according to the depth of the three-layer polyside wiring.

14A is a layout view of a two-stage CMOS inverter using metal wiring and dual polyside wiring.

14B is a layout view of a two-stage CMOS inverter using metal wiring.

FIG. 15A is a cross-sectional view of the two-stage CMOS inverter of FIG. 14A.

FIG. 15B is a cross-sectional view of the two-stage CMOS inverter of FIG. 14B.

Fig. 16 shows the distribution of boron concentration after heat treatment in a four-layer film of silicon oxide film / tungsten silicide film / polysilicon film / silicon oxide film.

FIG. 17 is a view schematically showing impurity diffusion and congestion in a conventional two-layer polyside interconnection. FIG.

* Explanation of symbols for main parts of the drawings

1: silicon substrate 2: device isolation film (device isolation region)

3: source and drain (p ⁺ diffusion layer region) 4: gate oxide film

5,13: first p ⁺ polysilicon film (first polycrystalline silicon film)

6,14: tungsten silicide film

7,15: second p ⁺ polysilicon film (second polycrystalline silicon film)

8,9,16 silicon oxide film 10 BPSG film

11 interlayer insulating film 12 contact hole

60 gate electrode 61,65 polyside wiring.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device and a method for manufacturing the same, which prevent deterioration of contact resistance due to heat treatment during the manufacturing process.

threshold voltage of the p ⁺ type polycrystalline p-channel MOS transistor having a polysilicon gate electrode, as compared to the p-channel MOS transistor having a polysilicon gate electrode n + type, the short channel effect is further suppressed, and also, the MOS transistor ( Vth) can be set even lower. This is disclosed, for example, in IEEE, IEDM, Technical Digest P418-422 (1984).

In addition, in order to electrically connect the p ⁺ type impurity diffusion region formed in the semiconductor substrate with the polycrystalline silicon wiring, a p ⁺ type polycrystalline silicon film is used as the polycrystalline silicon wiring. The p ⁺ type polycrystalline silicon film has a higher specificity than that of a general metal. Wiring and electrode, can be resistivity of the wiring and electrodes formed from, because preferably formed of a low material, a refractory metal silicide, a p ⁺ polycide film laminated film on the p ⁺ type polycrystalline silicon film.

The p ⁺ polyside film is composed of a high melting point material which does not deteriorate even after heat treatment at a temperature of 900 ° C or higher. Therefore, after the step of forming the wiring and the electrode from the p ⁺ polyside film, the BPSG film is formed as an interlayer insulating film, and the step of planarizing the thus formed BPSG film by heat treatment can be performed. The semiconductor device thus manufactured is described in Japanese Patent Laid-Open No. 57-192070.

Even when a BPSG film is not used as the interlayer insulating film, in order to activate the p ⁺ -type impurity, heat treatment must be performed after the formation of the p ⁺ polyside film. In this heat treatment, the boron concentration may be lowered by out-diffusion of boron. In order to prevent this decrease in boron concentration, an insulating film must be deposited on the p ⁺ polyside film before the heat treatment. See, for example, Journal of Vacuum Science and Technology B, Vol. 5 p1674-1688 is disclosed in 1987.

However, the above-described prior art has a problem described below.

When heat-treated p ⁺ polycide film by a p ⁺ poly ungjip boron at the interface between the film and the insulating film which covers the side of it, there is a phenomenon in which a boron concentration of the p ⁺ polycide N degradation is known. This phenomenon is described, for example, in IEEE, IEDM, Technical Digest p407-410 (1985).

The lowering of the boron concentration causes specifically the following problems. When the p ⁺ polyside film is used as the gate electrode of the MOS transistor, the threshold voltage of the MOS transistor fluctuates in accordance with the decrease in boron concentration. (2) When the p ⁺ polyside film is used as the wiring for contacting the p-type impurity diffusion region, the contact resistance increases as the boron concentration decreases.

DISCLOSURE OF THE INVENTION An object of the present invention is to provide a semiconductor device having a polyside wiring in which boron concentration does not decrease by heat treatment in order to solve the above problems, and a method of manufacturing the same.

In order to achieve the above object, the semiconductor memory device of the present invention is a semiconductor device having a semiconductor substrate, a p-type impurity diffusion region formed in the semiconductor substrate, and a polyside wiring electrically connected to the p-type impurity diffusion region. The polyside wiring comprises a first polycrystalline silicon film, a high melting point metal silicide film formed on the first polycrystalline silicon film, and a second polycrystalline silicon film formed on the high melting point metal silicide film. .

A p-channel MOS transistor formed on the semiconductor substrate is additionally provided so that the p-type impurity diffusion region is any one of a source and a drain of the p-channel MOS transistor. The first polycrystalline silicon film of the impurity diffusion region has both a portion where p-type impurities are diffused and a portion where n-type impurities are diffused. In a preferred embodiment, p-type impurities are diffused substantially uniformly in the lateral direction in the second polycrystalline silicon film of the polyside wiring.

In order to achieve the above object, the polyside wiring of the present invention comprises a first polycrystalline silicon film, a high melting point metal silicide film formed on the first polycrystalline silicon film, and a second polycrystalline silicon film formed on the high melting point metal silicide film. The first polysilicon film has both a portion where a p-type impurity is diffused and a portion where an n-type impurity is diffused, and the p-type impurity is diffused substantially uniformly in the lateral direction in the second polycrystalline silicon film. .

In order to achieve the above object, another semiconductor device of the present invention is a CMOS semiconductor device having a semiconductor substrate, an n-channel MOS transistor formed on the semiconductor substrate, and a p-channel MOS transistor, wherein the n-channel MOS transistor is the semiconductor. An n-type source and an n-type drain formed of an n-type impurity diffusion region formed in a substrate, and the p-channel MOS transistor has a p-type source and a p-type drain composed of p-type impurity diffusion regions formed in the semiconductor substrate, The semiconductor device includes a polyside wiring having a first polycrystalline silicon film, a high melting point metal silicide film formed on the first polycrystalline silicon film, and a second polycrystalline silicon film formed on the high melting point metal silicide film, The polysilicon film includes an n-type impurity diffusion portion connected to the n-type source or the n-type drain, the p-type source and Characterized in that with the p-type impurity diffusion portion, which is connected to the p-type drain Sykes.

A method for manufacturing a semiconductor device of the present invention includes the steps of forming a p-type impurity diffusion region in a semiconductor substrate and forming a polyside wiring connected to the p-type impurity diffusion region. The step of forming the polyside wiring includes the steps of forming a first polycrystalline silicon film connected to the p-type impurity diffusion region, forming a high melting point metal silicide film on the first polycrystalline silicon film, and the high melting point. And forming a second polycrystalline silicon film on the metal silicide film.

According to the semiconductor device of the present invention, since bores of boron in the polyside wiring are prevented, the fluorine concentration in the polyside wiring does not decrease by heat treatment. As a result, the threshold value of the MOS transistor having such a polyside wiring as the gate electrode is difficult to change. In addition, since the contact resistance between the polyside wiring and the p-type impurity diffusion region does not increase by heat treatment, stable contact characteristics are obtained.

According to the present invention, there is provided a CMOS semiconductor device in which deterioration of contact characteristics is suppressed by preventing impurities from spreading laterally in the dual polyside wiring.

(Example 1)

Embodiments of the present invention will be described below with reference to the accompanying drawings.

1 shows a partial cross section of a semiconductor device of the present invention. For simplicity, a single MOS transistor is shown in FIG. 1, but the semiconductor device of the present invention is a device in which a plurality of MOS transistors are formed on the same semiconductor substrate. The semiconductor device comprises a silicon substrate 1, an MOS transistor formed in each of the element isolation film 2 formed in the element isolation region on the surface of the silicon substrate 1 and the plurality of element regions on the surface of the silicon substrate 1; And an interlayer insulating film 10 made of a silicon oxide film 9 covering a MOS transistor and a Boro-Phospho Silicate Glass (BPSG) film.

Each MOS transistor includes a source and a drain region (p ⁺ type impurity diffusion region extending from the surface of the silicon substrate 1) 3 formed in the silicon substrate 1 and a gate oxide film formed on the silicon substrate 1. (Thickness: 10 nm) 4, a gate electrode 60 formed on the gate oxide film 4, and a silicon oxide film 8 (thickness: 200 nm) formed on the gate electrode 60 are provided. The region shown in FIG. 1 of the silicon substrate 1 is an n-type well region formed in the p-type silicon substrate 1. The MOS transistor may be formed on the n-type silicon substrate.

The source and drain regions 3 are spaced apart from each other at a predetermined distance (for example, 500 nm) in the lateral direction of FIG. 1, and the region between the source and drain regions 3 forms a channel region of the MOS transistor. Doing. The gate electrode 60 covers the channel region via the gate oxide film 4. In accordance with the potential of the gate electrode 60, a conductive channel for electrically connecting the source and drain regions 3 is formed in the channel region.

The gate electrode 60 of this semiconductor device includes a p ⁺ type first polycrystalline silicon film (thickness: 100 nm) (5) and a tungsten silicide film (thickness: 200 nm) formed on the p ⁺ type polycrystalline silicon film 5 (6). has a sandwich-type three-layer polycide structure consisting of 100nm) (7):) and, p ⁺ type second polycrystalline silicon film (having a thickness formed on the tungsten silicide film. In a semiconductor integrated circuit device having a plurality of MOS transistors, the polyside wiring has each gate electrode portion of a group of transistors and a plurality of wiring portions for connecting each gate electrode. In the present invention, electrodes and wirings having a polyside structure are collectively referred to as polyside wiring. The width of the polyside wiring of this embodiment is typically about 500 nm to 100 nm. In order to refine, you may make it narrower than this width.

In addition, the thickness of each film | membrane which comprises a saik polyside wiring is set to arbitrary arbitrary values according to a design. The high melting point metal silicide film interposed between the first and second polycrystalline silicon films may be a film made of a high melting point metal silicide other than tungsten silicide, or a multilayer film including another kind of high melting point metal silicide film. An important point is that the high melting point metal silicide film is not integrally formed on the upper surface.

The silicon oxide film 9 prevents the diffusion of impurities (boron and phosphorus) from the BPSG film 10 into the silicon substrate 1. A film having an effect of preventing diffusion, for example, a silicon nitride film, may be used in place of the silicon oxide film 9.

The MOS transistor is a p-channel MOS transistor. By inverting the impurity conduction type of the silicon substrate 1, the source and drain regions 3, an n-channel MOS transistor is obtained. The polyside wiring can be applied to a CMOS (complementary MOS) semiconductor device. A CMOS semiconductor device is a semiconductor device having a p-channel MOS transistor and an n-channel MOS transistor on the same semiconductor substrate. In more detail, a CMOS semiconductor device may include, for example, an n-channel MOS transistor formed on a p-type silicon substrate and a p-channel MOS transistor formed on an n-type well having a p-type silicon substrate and an n-type well formed therein. Equipped.

The semiconductor device in FIG. 1 has a p ⁺ type second polysilicon film between the tungsten silicide film 6 and the silicon oxide film 8, so that the top surface of the tungsten silicide film 6 and the silicon oxide film 8 are directly The main feature is that they are not in contact. FIG. 16 shows the boron concentration distribution in a multilayer structure composed of a silicon oxide film, a polycrystalline silicon film, a tungsten silicide film and a silicon oxide film. In other words, a boron concentration distribution is shown for a conventional two-layer polyside structure sandwiched on a silicon oxide film, in which the polyside structure consists of a polycrystalline silicon film and a tungsten silicide film on the polycrystalline silicon film. As shown in FIG. 16, the boron concentration distribution has a peak at the interface between the silicon oxide film and the tungsten silicide film. This indicates that boron is packed at the interface. Boring of boron causes a decrease in the boron concentration in the tungsten silicide film and the polycrystalline silicon film. In other words, the interface between the tungsten silicide film and the polycrystalline silicon film takes on boron in the polyside wiring and functions as a sink for absorbing boron.

On the other hand, at the interface between the tungsten silicide film and the polysilicon film, bores of boron do not occur. This is considered to be due to a mismatch between the tungsten silicide film and the silicon oxide film when the crystal grains of the tungsten silicide film are grown by heat treatment, but such mismatching hardly occurs between the tungsten silicide film and the polycrystalline silicon film.

The concentration distribution shown in FIG. 16 was obtained by performing secondary ion mass spectrometry (SIMS) on the sample having the above structure. The sample was produced as follows. First, a silicon oxide film and a polysilicon film were sequentially formed on the silicon substrate, and then boron ions were implanted into the polycrystalline silicon film. A tungsten silicide film and a silicon oxide film were sequentially formed on the polysilicon film, and then heat treated at 900 占 폚 for 30 minutes. By this heat treatment, boron in the polysilicon film is diffused to the interface between the tungsten silicide film and the silicon oxide film.

According to the embodiment of the present invention shown in FIG. 1, the area of the interface between the tungsten silicide film 6 and the silicon oxide film 9 (the area of the side surface of the tungsten silicide film 6) is not limited to the conventional semiconductor device. Compared with the area of the interface between the tungsten silicide film 6 and the silicon oxide film 8 in this case, the thickness is substantially negligible. In this embodiment, since the area of the interface (interface between the silicide and the insulating film) where boron tends to shrink is significantly reduced, boron in the p + type first polysilicon film 7 and the tungsten silicide film 8 is the interface. To avoid being punished. For this reason, the boron concentration in a wiring is prevented from decreasing by the boron constriction.

As another preferred embodiment, not only the top surface of the tungsten silicide film 6 but also its side surface may be covered with the p-type second polycrystalline silicon film 6. In this embodiment, since the tungsten silicide film 6 is completely covered by the polysilicon film, there is no interface between the tungsten silicide film and the silicon oxide film. As a result, bores of boron due to such an interface do not occur, and the decrease in boron concentration inside the wiring due to the pores is prevented.

A method of manufacturing the semiconductor device will be described below with reference to FIGS. 2A to 2C. First, the element isolation film 2 is formed in the element isolation region on the surface of the silicon substrate 1 by a known local oxidation (LOCOS) method. The device isolation film may be formed by a method other than the LOCOS method. An element region is a region where the element isolation film 2 is not formed. By oxidizing the surface of each element region of the silicon substrate 1, a gate oxide film 4 is formed on each element region.

After the polycrystalline silicon film was deposited to cover the gate oxide film 4 by the reduced pressure chemical vapor deposition (LPCVD) method, boron as a p-type impurity was formed in the polycrystalline silicon film as shown in FIG. Ions are implanted with an acceleration energy of 20 KeV and a dose of 6 x 10 ¹⁵ cm ^-2 . In this way, the p ⁺ type first polycrystalline silicon film 5 is formed.

Next, as shown in FIG. 2 (b), after depositing the tungsten silicide film 6 on the p + type polysilicon film 5, another polysilicon film is deposited. Boron ions are implanted into the polycrystalline silicon film at an acceleration energy of 20 KeV and a dose of 6 × 10 ¹⁵ cm ⁻² . In this way, the p ⁺ type second polysilicon film 7 is formed on the tungsten silicide film 6.

Next, a silicon oxide film 8 is deposited on the p ⁺ type second polycrystalline silicon film 7. The first polycrystalline silicon film 5, the tungsten silicide film 6, the second polycrystalline silicon film 7 and silicon are deposited. The multilayer film made of the oxide film 8 is patterned into a desired wiring shape using known lithography and etching techniques. Thus, as shown in FIG. 2C, a polyside wiring (gate electrode) consisting of three layers of the first polycrystalline silicon film 5, the tungsten silicide film 6, and the second polycrystalline silicon film 7 (60)).

Next, using the element isolation film 2 and the gate electrode 6 as a mask, boron is implanted into the element region of the silicon substrate 1 at an acceleration energy of 10 KeV and a dose of 6 x 10 ¹⁵ cm ^-2 . The boron-infused region becomes the source and drain region 3 of the MOS transistor by the following annealing process. Since the region serving as the channel of the MOS transistor is covered with the gate electrode 60, boron is not implanted into the region. In this way, the channel region, the source and the drain region 3 are formed in self-alignment with respect to the gate electrode 60. In addition, the silicon oxide film 8 can function as an etching mask when etching the second polysilicon film 7 or the like, but is not necessarily an essential element in the present invention.

In addition, a sidewall spacer may be formed on the side surface of the gate electrode 60 before the ion implantation for forming the source and drain regions 3. Before forming the sidewall spacers, ion implantation for forming the LDD region may be performed. By forming the LDD region, the short channel effect can be suppressed, so that the MOS transistor can be further miniaturized. Miniaturization of the MOS transistors increases the operating speed of the transistors and helps to improve the integration degree of a semiconductor device including a large number of such transistors.

Next, after the silicon oxide film 9 is deposited to cover the transistors, the BPSG film 10 is deposited on the silicon oxide film 9. In order to planarize the surface of the BPSG film 10 and simultaneously activate the impurities, annealing at 900 ° C. is performed in a nitrogen atmosphere for 30 minutes. The conditions of this annealing can be arbitrarily set suitably. After forming a contact hole (not shown) in a predetermined portion of the BPSG film 10, a polyside wiring and wirings connected to the source and drain regions 3 are formed on the BPSG film 10. As shown in FIG.

According to this embodiment, since the boron concentration decreases inside the polyside wiring (gate electrode 60) by heat treatment, the threshold value of the MOS transistor does not change. The MOS transistor according to the present embodiment can be used as a switching transistor inside a memory cell having a semiconductor memory device such as a DRAM. In other words, the polyside interconnection having the above three-layer structure can be used as a word line of DRAM.

As described above, the tungsten silicide film 6 is the first p ⁺ polysilicon film 5 and the second p in the semiconductor device using a polyside whose gate electrode is a p ⁺ polysilicon. ^{Since the} polysilicon film 7 is present, the tungsten silicide film 6 does not come into contact with the silicon oxide film 8 or the silicon oxide film 10. That is, there is no interface between the high melting point metal silicide film and the insulating film in which a large amount of boron is packed. In this structure, the interface between the high melting point silicide film 6 and the p ⁺ polysilicon films 5 and 7 and the interface between the p ⁺ polysilicon 7 and the insulating film 8 are formed. As a result of the experiment, as shown in FIG. 4, it was found that there were very few holes at these interfaces.

As described above, by using the above-described configuration, bores of boron do not occur at the interface between the silicon tetraoxide film and the tungsten silicide film by the heat treatment in the subsequent step, and the boron concentration in the p ⁺ polyside film does not decrease. For this reason, neither the p-channel MOS transistor nor the n-channel MOS transistor has a change in threshold voltage (vt). Moreover, since 900 degreeC heat processing can be performed, planarization using a BPSG film | membrane is attained.

(Example 2)

3 shows a partial cross section of another embodiment of the present invention. In the semiconductor device shown in FIG. 1, the polyside wiring of the three-layer structure is used as the gate electrode of the MOS transistor and the wiring for connecting them. In the semiconductor device of this embodiment, the polyside of the three-layer structure is used. The wiring is used as the wiring for contacting the p-type impurity diffusion region in the semiconductor substrate. The polyside wiring shown in FIG. 3 can be used, for example, as a bit line of a DRAM.

The semiconductor device includes a silicon substrate (an n-type impurity diffused therein) 1, an element isolation film 2 formed in an element isolation region on the surface of the silicon substrate 1, and a surface of the silicon substrate 1. The p-type impurity diffusion region 3 formed in each of the plurality of device regions of the substrate, the interlayer insulating film 11 formed on the silicon substrate 1, the contact hole 12 formed in the interlayer insulating film 11, and the interlayer insulating film ( And a polyside wiring 61 formed over the contact hole 12 and in contact with the p-type impurity diffusion region 3.

The polyside wiring 61 of the present embodiment includes a p ⁺ type first polycrystalline silicon film (thickness: 100 nm) 13 and a tungsten silicide film (thickness: 200 nm) formed on the p ⁺ type polycrystalline silicon film 13 (14). ) And a p ⁺ type second polycrystalline silicon film (thickness: 200 nm) 15 formed on the tungsten silicide film 14.

The semiconductor device further includes a silicon oxide film 16 formed on the interlayer insulating film 11 so as to cover the polyside wiring 61 and a BPSG film 17 formed on the silicon oxide film 16.

According to the present embodiment, since the polyside wiring 61 does not substantially have an interface between the tungsten silicide film 14 and the silicon oxide film 16, the boron concentration in the polyside wiring 61 is reduced even after the heat treatment. I never do that. As a result, the diffusion of boron into the polyside wiring 61 from the p-type impurity diffusion region 3 in the silicon substrate 1 is suppressed. In this way, the boron concentration decrease in the p-type impurity diffusion region 3 and the polysilicon film 13 in the silicide substrate 1 is prevented. As described above, since the boron concentration in the p-type impurity diffusion region 3 and the polycrystalline silicon film 13 does not decrease, the contact resistance between the polyside wiring and the p-type impurity diffusion region 3 is kept low.

As the gate oxide film 4, for example, a nitride oxide film (ONO) film may be used. In addition, although p + polysilicon was formed using the ion implantation method, you may use the thermal diffusion method. Although tungsten silicide is used as the silicide, the same effect can be obtained even with a high melting point metal silicide film such as titanium silicide. In addition, although the structure of the MOS transistor of the embodiment was set to SD (single drain), even if it is a structure such as LDD, the effect of the present invention can be obtained similarly.

The manufacturing method of the present semiconductor device will be described below. First, an element isolation film 2 is formed in the element isolation region on the surface of the silicon substrate 1. The region where the device isolation film 2 is not formed is the small region. Thereafter, using the element isolation film 2 as a mask, boron is implanted into the element region of the silicon substrate 1 at an acceleration energy of 10 KeV and a dose of 6 x 10 ¹⁵ cm ^-2 . The boron-implanted region becomes the p-type impurity diffusion region 3 by the following annealing process.

Next, after the interlayer insulating film 11 is deposited to cover the small region, the contact hole 12 is formed in the interlayer insulating film 11 by using a conventional lithography and etching technique. By deep etching using an aqueous solution containing hydrofluoric acid, after removal of the natural oxide film present on the bottom surface of the contact hole 12, polysilicon wiring of the semiconductor device of FIG. The side wiring 61 is formed.

After the silicon oxide film 16 and the BPSG film 17 are deposited, the BPSG film 17 is annealed at 900 ° C. in a nitrogen atmosphere for 30 minutes in order to planarize and activate impurities. Next, a contact hole (not shown) reaching the polyside wiring 61 is formed in the BPSG film 17 and the silicon oxide film 16, and then connected to the polyside wiring 61 via the contact hole. Wiring (not shown) is formed on the BPSG film 17.

Before forming the interlayer insulating film 11, the MOS transistor of FIG. 1 may be formed in the small region. In this case, either of the source and drain regions 3 of the MOS transistor of FIG. 1 corresponds to the p-type impurity diffusion region 3 shown in FIG. When the semiconductor device having the MOS transistor of FIG. 1 and the polyside wiring of FIG. 3 is applied to a DRAM, either the word line or the bit line of the DRAM may be formed by a polyside wiring of a three-layer structure. As another application, there is a DRAM such that the word line is a word line having a conventional structure, and only the bit line is the polyside wiring 61 shown in FIG.

(Example 3)

4 shows a partial cross section of another embodiment of the present invention. In the semiconductor device of this embodiment, a polyside wiring 61 having a three-layer structure is used as the wiring for contacting the p-type impurity diffusion region 33a and the n-type impurity diffusion region 33b in the silicon substrate 1. The polyside wiring in contact with both the p-type impurity diffusion region 33a and the n-type impurity diffusion region 33b in the silicon substrate 1 is called a dual polyside wiring. The dual polyside wiring shown in FIG. 4 can be preferably used as wiring of a CMOS semiconductor device.

The semiconductor device of this embodiment includes a silicon substrate 1, n-type wells and p-type wells 200 formed in the silicon substrate 1, and elements formed in the element isolation regions on the surface of the silicon substrate 1; On the separator 2, the p-type impurity diffusion region 33a formed in the n-type well 100, the n-type impurity diffusion region 33b formed in the p-type well 200, and the silicon substrate 1 It is formed on the interlayer insulating film 11, the contact hole 12 formed in the interlayer insulating film 11, and the interlayer insulating film 11, and the p-type impurity diffusion region 33a and the n-type through the contact hole 12. A polyside wiring 61 is provided in contact with the impurity diffusion region 33b.

The polyside interconnection 61 of this embodiment is a tungsten silicide film (thickness: 200 nm) formed on the p ⁺ type first polycrystalline silicon film (thickness: 100 nm) 13 and the p ⁺ type polycrystalline silicon film 13 (14). And a p ⁺ type second polysilicon film (thickness: 200 nm) 15 formed on the tungsten silicide film 14.

4 is a cross-sectional view parallel to the plane along the direction in which the polyside wire 61 extends, so that the polyside wire 61 appears to completely cover the entire surface of the interlayer insulating film 11, but in reality, the wiring A polyside interconnection 61 having a shape is present on a predetermined region of the interlayer insulating film 11. This semiconductor device further includes another interlayer insulating film 20 formed on the interlayer insulating film 11 so as to cover the polyside wiring 61. The interlayer insulating film 20 may be a laminated film including a BPSG film or the like.

A method of manufacturing the semiconductor device will be described below with reference to FIGS. 5A to 5D. First, the device isolation film 2 is formed by the LOCOS method in the device isolation region of the surface of the semiconductor substrate 1 on which the p-type well 200 and the n-type well 100 are formed by a known method. As shown in (a), in order to form a pn junction in each of the wells 100 and 200, arsenic ions (n-type impurities) are implanted into the p-type well 200, and the n-type well 100 BF2 ion (p-type impurity) is injected into the. Arsenic ion and BF2 ion are inject | poured with acceleration energy 40KeV and dose amount 6 * 10 <^15> cm <^-2> , respectively.

The region implanted with arsenic ions becomes the n-type impurity diffusion region 33b, and the region implanted with BF 2 ions becomes the p-type impurity diffusion region 33a.

Next, as shown in FIG. 5B, an interlayer insulating film (thickness: 300 nm) 11 made of a silicon oxide film is deposited on the semiconductor substrate 1 using the LPCVD method. The contact holes 12 reaching the n-type impurity diffusion region 33b and the p-type impurity diffusion region 33a formed in each of the wells 100 and 200 are subjected to a conventional lithography process and an etching process. Is formed in the interlayer insulating film 11. The contact hole 12 has, for example, a size of 600 nm in diameter.

Next, a first polycrystalline silicon film (thickness: 500 nm) 13 is deposited on the interlayer insulating film 11 by the LPLCVD method. Thereafter, boron ions are selectively implanted into a portion of the first polycrystalline silicon film 13. Boron ions are implanted at an acceleration energy of 15 KeV and a dose of 6 × 10 ¹⁵ cm ⁻² . In addition, arsenic ions are selectively implanted into other portions of the first polysilicon film 13. Arsenic ions are implanted at an acceleration energy of 80 KeV and a dose of 1 × 10 ¹⁵ cm ⁻² . The order of implantation of boron ions and the implantation of arsenic ions may be the reverse of the order performed in this embodiment. In the first polysilicon film 13, the couple implanted with boron ions contact the p-type impurity diffusion region 33a in the n-type well 100, and the portion where the arsenic ion is implanted is the p-type well 200. ) Inside the n-type impurity diffusion region 33b.

Next, as shown in FIG. 5C, after the tungsten silicide film (thickness: 100 nm) 14 is deposited on the first polycrystalline silicon film 13 by the sputtering method, the second polysilicon film ( Thickness: 50 nm) 15 was deposited on the tungsten silicide film 14 by LPCVD. Thereafter, boron ions are implanted into the entire surface of the second polycrystalline silicon film 15 at an acceleration energy of 30 KeV and a dose of 6 × 10 ¹⁵ cm ⁻² .

As shown in FIG. 5 (d), by the usual lithography process and etching process, 3 composed of the second polycrystalline silicon film 5, the tungsten silicide film 14, and the first polycrystalline silicon film 13 The layer film is patterned into a wiring shape, and the three-layer dual polyside wiring 61 is formed. Using an atmospheric vapor phase chemical vapor deposition (APCVD) method, an interlayer insulating film 20 made of a silicon oxide film is deposited on the interlayer insulating film 11 so as to cover the dual polyside band 61. Thereafter, in an atmosphere of nitrogen, annealing at 900 ° C. is performed for 10 to 90 minutes. In this way, the semiconductor device shown in FIG. 4 is obtained.

6 shows the boron concentration (cm−) depending on the depth of the sandwich type three-layer polyside structure including a first polycrystalline silicon (Poly-Si) film, a tungsten silicide (WSi2) film, and a second polycrystalline silicon (Poly-Si) film. 3 shows the change of distribution. This polycylindrical structure is formed on a silicon substrate (Si-Sub) and covered by a silicon oxide film (SiO2). The impurity concentration distribution of FIG. 6 is obtained by secondary ion mass spectrometry (SIMS). For comparison, the distribution of impurity concentrations according to the depth of a conventional two-layer polyside structure composed of a polycrystalline silicon film and a tungsten silicide film is shown. The cross-sectional structure of each said polycide structure is typically shown by the graph of FIG. The boron ion was injected to the polycrystalline silicon positioned at the lowest layer of each polycide structure at an acceleration energy of 15 KeV and a dose of 6 × 10 ¹⁵ cm ⁻² , followed by annealing (900 ° C. for 60 minutes). In Fig. 6, the boron concentration distribution before the annealing step (just after the injection) is indicated by a dashed two-dot chain line.

As can be seen from FIG. 6, the boron concentration in the first polycrystalline silicon film in the sandwich-type three-layer polyside structure is compared with the boron concentration in the polycrystalline silicon film in the conventional polyside structure, and is higher by one digit. Have. This is because the sandwich type three-layer polyside structure does not substantially have an interface between the tungsten silicide film and the silicon oxide film. That is, boron does not condense at such an interface, and boron is not absorbed at such an interface.

On the other hand, in the conventional two-layer polyside structure, the interface between the polycrystalline silicon film and the silicon oxide film exists. The boron concentration at this interface exceeds ^{10x10 21} cm ^-3 . This indicates that boron is packed at the interface. This boron package causes a decrease in the boron concentration in the two-layer polyside structure.

FIG. 17 schematically shows such a dual polyside wiring having a conventional two-layer structure. This dual polyside wiring is composed of a polycrystalline silicon film 13 and a tungsten silicide film 14. The polyside wiring is formed on the interlayer insulating film 11 covering the silicon substrate 1 and is interposed with a contact hole formed in the interlayer insulating film 11, where n ⁺ impurity diffusion region and p ⁺ impurity of the silicon substrate 1 are formed. It is in contact with the diffusion region. In addition, the polyside wiring is covered by the silicon oxide film 20.

In such polyside wiring, bores of boron are generated between the silicon oxide film 20 and the tungsten silicide film 14. In addition, due to the lateral diffusion of boron and arsenic, the contact resistance increases or varies between the polyside wiring and the impurity diffusion region.

FIG. 7 shows the contact resistance between the p ⁺ type polyside wiring and the p type impurity diffusion region in the semiconductor substrate. The contact resistance (conventional example) of the normal polyside wiring is indicated by black squares, and the contact resistance (example) of the sandwich type three-layer polyside wiring is indicated by white squares. Boron is not injected into the second polycrystalline silicon of the sandwich type three-layer polyside wiring. The contact resistance (another embodiment) of the sandwich type three-layer polyside interconnection in which boron was implanted in the entire surface of the second polycrystalline silicon is indicated by a black diamond.

As can be seen from FIG. 7, the contact resistance of the sandwich type three-layer polyside wiring according to the present invention is lowered to less than half as compared with that of the conventional polyside wiring. In general, the contact resistance between the p ⁺ -type impurity diffusion region in the p ⁺ type poly-semiconductor substrate and the side wiring are strongly dependent on the impurity concentration in the lowest layer of the polycrystalline silicon film and the p ⁺ type diffusion region within, polycide wiring . In the polyside wiring according to the present invention, since the lowering of the boron concentration caused by the boron hole is prevented, as shown in FIG. 7, low contact resistance can be achieved. In particular, the sandwich type three-layer polyside wiring in which boron is injected into the entire surface of the second polycrystalline silicon film has an advantage that the contact resistance does not depend on the annealing time. This advantage suppresses fluctuations in contact resistance accompanying fluctuations in process conditions.

The characteristics of the sandwich-type three-layer polyside wiring according to the present invention are related to impurity movement (diffusion) crossing the interface existing in the polyside wiring, that is, impurity redistribution in the longitudinal direction (depth direction). In order to evaluate the characteristics of the dual polyside wiring, it is necessary to observe the impurity movement (diffusion) in the direction along the interface in the polyside wiring, that is, the impurity redistribution in the lateral direction. 8 shows a planar arrangement of samples for evaluating the impurity redistribution in the lateral direction. This sample is provided with the sandwich type three layer polyside wiring 65 which has the arsenic doped 1st part 65b and the boron doped 2nd part 65a. The second portion 65a of the polyside wiring 65 is in contact with the p ⁺ -type impurity diffusion region 30 in the semiconductor substrate via the contact hole 12. The first portion 65b has a sufficiently large volume as compared to the second portion 65a. The distance between the second portion 65b and the contact portion is set to the interval D. As the sample, a plurality of samples having various intervals D were produced, and annealing was performed at 900 ° C. for 90 minutes for each sample. After annealing, for each sample, the contact resistance was measured.

9 shows the relationship between the contact resistance and the interval D. FIG. For samples other than the sample having the sandwich type three-layer polyside wiring in which boron was injected into the entire surface of the second polycrystalline silicon film, the smaller the interval D, the higher the contact resistance. On the other hand, the contact resistance of the sample having the sandwich type three-layer polyside wiring in which boron was injected into the entire surface of the second polycrystalline silicon film is low without depending on the sample interval D. This indicates that in the sandwich type three-layer polyside wiring in which boron is injected into the entire surface of the second polycrystalline silicon film, the diffusion of boron from the contact portion to the second portion 65b in the transverse direction is suppressed. FIG. 10 shows annealing at 900 ° C. for 30 minutes in a sandwich-type polycide structure in which arsenic of each dose of 1 × 10 ¹⁵ , 3 × 10 ¹⁵ , and 6 × 10 ¹⁵ cm ⁻² is injected into the second polycrystalline silicon film. It then shows how boron redistributes. FIG. 11 shows that the arsenic of each dose of 1 × 10 ¹⁵ , 3 × 10 ¹⁵ , and 6 × 10 ¹⁵ cm ⁻² is injected into the first polycrystalline silicon film at 900 ° C. for 30 minutes at 900 ° C. It shows how arsenic redistributes after annealing.

As can be seen from FIGS. 10 and 11, boron is present in the tungsten silicide film more than the second polycrystalline silicon film. On the other hand, arsenic is present in the first polycrystalline silicon film more than the tungsten silicide film. By this, the following facts can be known.

(1) In the n-type polyside region of the dual polyside interconnection, boron implanted into the second polycrystalline silicon film is likely to remain in the second polycrystalline silicon film and hardly move in the tungsten silicide film.

(2) Therefore, boron implanted into the second polycrystalline silicon film does not adversely affect the contact characteristics of the n-type polyside portion and the n-type impurity region.

Since boron is injected into the entire surface of the second polycrystalline silicon film, boron in the second polycrystalline silicon film and boron diffused from there into the tungsten silicide film are distributed substantially uniformly in the transverse direction. For this reason, the diffusion of boron in the transverse direction is suppressed in the second polycrystalline silicon film and the tungsten silicide film.

(2) Boron in the contact portion between the p-type polyside region and the p-type impurity diffusion region is suppressed from flowing out from the p-type polyside region of the second polycrystalline silicon film to the n-type polyside region via the tungsten silicide film.

In the n-type polyside region of the dual polyside interconnection, arsenic in the first polycrystalline silicon film is less likely to migrate into the tungsten silicide film.

(2) Arsenic in the first polycrystalline silicon film is less likely to diffuse in the transverse direction than arsenic in the tungsten silicide film.

(3) Therefore, the outflow of arsenic from the contact portion between the n-type polyside region and the n-type impurity region by diffusion in the longitudinal direction and the transverse direction is suppressed. For this reason, the fall of arsenic concentration is prevented in the contact part of an n type polyside region and an n type impurity region. As such, the contact resistance between the n-type polyside region and the n-type impurity region is hardly deteriorated.

Boron has a characteristic that arsenic is difficult to diffuse into the impurity diffusion region in which high concentrations exist. FIG. 13 shows a change in the concentration distribution of boron and arsenic with the depth of the sandwich type three layer polyside interconnection. More specifically, the impurity concentration distribution after annealing treatment at 900 DEG C for 30 minutes in a polyside wiring in which arsenic is injected into the first polycrystalline silicon film and boron is injected into the second polycrystalline silicon film is shown. As can be seen from FIG. 13, boron hardly diffuses in the silicon substrate, and the arsenic concentration in the first polycrystalline silicon film is kept high.

In order to indicate that boron implanted into the second polysilicon film does not adversely affect the contact resistance of the n-type polyside portion and the n-type impurity region, n between the sandwich type three-layer polyside wiring and the n-type impurity diffusion region The type contact resistance was measured. FIG. 12 is a graph showing how the boron injection into the second polysilicon film affects the change of the n-type contact resistance as the annealing time elapses. As apparent from FIG. 12, boron injection into the second polycrystalline silicon film hardly increases the n-type contact resistance. At this time, the annealing temperature is 900 ° C.

(Example 4)

Referring to FIG. 14, a CMOS device having the polyside wiring of FIG. 5 will be described. 14A and 14B show an embodiment of the present invention using dual polyside wiring and a conventional example without using dual polyside wiring, respectively. 15 (a) and 15 (b) are cross sectional views of FIGS. 14 (a) and (b).

The CMOS semiconductor device of this embodiment is a two stage CMOS inverter having two n-channel MOS transistors and two p-channel MOS transistors. The two transistors located above FIG. 14A are all p-channel MOS transistors, and the transistors located below are all n-channel MOS transistors. As shown in Fig. 15A, each source of the p-channel MOS transistor is connected to the power supply wiring (not shown) via the metal wiring 69a. Each source of the n-channel MOS transistor is connected to the ground wiring (not shown) via the metal wiring 69b. As shown in Figs. 14A and 15A, a polyside wiring 63a or 63b is interposed between the source of the p-channel MOS transistor and the metal wiring 69a. Similarly, a polysite wiring 63c or 63d is interposed between the source of the n-channel MOS transistor and the metal wiring 69b.

The drain of the p-channel MOS transistor closer to the input terminal IN is connected to the drain of the corresponding n-channel MOS transistor (n-channel MOS transistor closer to the input terminal) via the dual polyside wiring 62. Connected. The drain of the p-channel MOS transistor near the output terminal OUT is mutually connected to the drain of the corresponding n-channel MOS transistor (n-channel MOS transistor near the output terminal) via the dual polyside wiring 63. Connected. The dual polyside wiring 63 may be an output terminal OUT. The gates of the p-channel and n-channel MOS transistors close to the input terminal IN are connected to the input terminal IN made of polyside wiring via the gate electrode 16a. The gates of the p-channel and n-channel MOS transistors close to the output terminal are connected to the output terminal OUT made of the polyside wiring 63 via the gate electrode 16b.

During the manufacturing process in the CMOS semiconductor device of this embodiment, impurity crowding in the polyside wiring is prevented, and lateral diffusion is suppressed. As a result, an increase in contact resistance is prevented.

As shown in Figs. 14 (b) and 15 (b), in the conventional example, not the drain of the p-channel MOS transistor, the drain of the n-channel MOS transistor, and the dual polyside wiring, but the metal wiring 72. And (73), they are interconnected. In addition, the input terminal is composed of a metal wiring 71. The interconnection between the source, power supply wiring and ground wiring of each MOS transistor is also performed by the metal wiring 70.

As shown in Figs. 14A and 14B, the CMOS semiconductor device of this embodiment has a smaller occupied area compared with the conventional example. For this reason, a compact CMOS semiconductor device in which contact characteristics are hardly deteriorated is realized. In addition, a high density integrated CMOS semiconductor device is provided. For simplicity, an embodiment of the present invention has been described with respect to a two-stage CMOS inverter, but the present invention can also be applied to other CMOS semiconductors.

According to the semiconductor device of the present invention, since boron crowding in the polyside wiring is prevented, the boron concentration in the polyside wiring does not decrease by heat treatment. As a result, the threshold value of the MOS transistor having such polyside wiring as the gate electrode is difficult to change. In addition, since the contact resistance between the polyside wiring and the p-type impurity diffusion region does not increase by heat treatment, stable contact characteristics can be obtained.

According to the present invention, a CMOS semiconductor device is provided in which the deterioration of contact characteristics is suppressed by preventing the horizontal diffusion of impurities in the dual polyside wiring.

Claims (16)

A semiconductor device having a semiconductor substrate, a p-type impurity diffusion region formed in the semiconductor substrate, and a polyside interconnection electrically connected to the p-type impurity diffusion region, wherein the polyside wiring includes: first polycrystalline silicon; A high melting point metal silicide film formed on the first polycrystalline silicon film, and a second polycrystalline silicon film formed on the high melting point metal silicide film. The semiconductor device according to claim 1, further comprising a p-channel MOS transistor formed on a semiconductor substrate, wherein the p-type impurity diffusion region is any one of a source and a drain of the p-channel MOS transistor. . The semiconductor device according to claim 1 or 2, wherein the first polycrystalline silicon film of the polyside wiring has both a portion where p-type impurities are diffused and a portion where n-type impurities are diffused. The semiconductor device according to claim 1 or 2, wherein the p-type impurity is diffused substantially uniformly in the lateral direction in the second polycrystalline silicon film of the polyside wiring. In a CMOS semiconductor device having a semiconductor substrate, an n-channel MOS transistor and a p-channel MOS transistor formed on the semiconductor substrate, the n-channel MOS transistor includes an n-type source and n consisting of an n-type impurity diffusion region formed in the semiconductor substrate. The p-channel MOS transistor has a p-type source and a p-type drain including a p-type impurity diffusion region formed in the semiconductor substrate. The semiconductor device includes a first polycrystalline silicon film and the first polycrystal. And a polyside interconnection having a high melting point metal silicide film formed on the silicon film and a second polycrystalline silicon film formed on the high melting point metal silicide film, wherein the first polycrystalline silicon film is connected to the n-type source or the n-type drain. And an n-type impurity diffusion portion connected to the p-type impurity diffusion portion connected to the p-type source or the p-type drain. And a CMOS semiconductor device, characterized in that. 6. The CMOS semiconductor device according to claim 5, wherein the p-type impurity is substantially uniformly diffused in the lateral direction in the second polycrystalline silicon film. A semiconductor device comprising a semiconductor substrate, a source and a drain formed in the semiconductor substrate, a gate insulating film formed on the semiconductor substrate, and a gate electrode formed on the gate insulating film, wherein the gate electrode comprises: a first polycrystalline silicon film; It has a high melting point metal silicide film formed on this 1st polycrystalline silicon film, and the 2nd polycrystal silicon film formed on this high melting point metal silicide film, and p-type impurity is spread | diffused substantially uniformly in this 2nd polycrystal silicon film | membrane. The semiconductor device characterized by the above-mentioned. 8. The semiconductor device according to claim 7, wherein the p-type impurity is diffused substantially uniformly in the lateral direction even in the high melting point metal silicide film. A method of manufacturing a semiconductor device comprising the steps of forming a p-type impurity diffusion region in a semiconductor substrate and a step of forming a polyside wiring connected to the p-type impurity diffusion region, wherein the step of forming the polyside wiring is Forming a first polycrystalline silicon film connected to the p-type impurity diffusion region, forming a high melting point metal silicide film on the first polycrystalline silicon film, and forming a second polycrystalline silicon film on the high melting point metal silicide film A manufacturing method of a semiconductor device comprising the step of. The method of manufacturing a semiconductor device according to claim 9, further comprising a step of doping a p-type impurity on the second polycrystalline silicon film. A semiconductor according to claim 10, wherein the step of doping the p-type impurity in the second polycrystalline silicon film is a step of injecting the p-type impurity into the entire surface of the second polycrystalline silicon film using an ion implantation method. Method of manufacturing the device. As a gate electrode of the p-channel MOS transistor formed on a semiconductor substrate, p ⁺ in the production method of the poly-semiconductor device having a silicon film and a high melting point silicide film is a multilayer film, and then a gate oxide film is formed, the first polysilicon film in the whole surface Forming a film, a step of doping a p-type impurity on the entire surface of the first polysilicon film, forming a high melting point metal silicide film on the whole surface, and forming a second polysilicon film on the whole surface And a step of doping the p-type impurity to the entire first polysilicon film, a step of forming an insulating film on the entire surface, and a step of performing heat treatment. and a semiconductor substrate having a p ⁺ diffusion layer, to prevent isolation of the first formed on the semiconductor substrate, the p ⁺ and wherein the contact hole is opened in the first insulating film in the above diffusion region, said p ⁺ to electrically slow the diffusion region a semiconductor device having a wiring formed p ⁺ polycide film, the p ⁺ polycide film structure, p ⁺ polysilicon film of the insulating film of the first above the first in the contact hole, and the first p ⁺ A semiconductor device comprising a high melting point metal silicide film on a polysilicon film and a second p + polysilicon film on the high melting point metal silicide film. and a semiconductor substrate having a p ⁺ diffusion layer, and a first insulating film formed on the silicon substrate, and the p ⁺ diffusion layer area, wherein the contact hole is opened in the first insulating film of the above and, as a wiring for connecting the p ⁺ diffusion region is electrically A semiconductor device manufacturing method for manufacturing a semiconductor device having a p ⁺ polyside film formed, the method comprising: forming a first polysilicon film on an entire surface after the contact hole is formed; and the entire first polysilicon film A step of doping the p-type impurity on the surface, a step of forming a high melting point metal silicide film on the entire surface, a step of forming a second polysilicon film on the entire surface, and a p on the entire surface of the second polysilicon film And a step of forming a second insulating film on the entire surface, and a step of performing a heat treatment. As a gate electrode of the p-channel MOS transistor formed on a semiconductor substrate, in the semiconductor device of p ⁺ type polysilicon film and a high having a refractory metal silicide film is a multilayer film (p ⁺ polycide film), the p ⁺ polycide film structure , composed by p ⁺ polysilicon film of claim 1 on the gate oxide film and a refractory metal silicide of the p ⁺ polysilicon makwi the first film and the refractory metal silicide the second p ⁺ polysilicon film of makwi A semiconductor device, characterized in that. 4. The semiconductor device according to claim 3, wherein the p-type impurity is diffused substantially uniformly in the lateral direction in the second polycrystalline silicon film of the polyside wiring.