KR970004530B1 - Adaptive Moving Target Filter - Google Patents

Abstract

No summary

Description

Adaptive Moving Target Filter

1 is a block diagram of a filter conventionally used.

2 is an output characteristic diagram of FIG.

3 is a reception signal of a moving target due to the Doppler effect.

4 is an overall block diagram of an adaptive mobile target filter according to the present invention.

5 is a detailed circuit diagram of the frequency analyzing means shown in FIG.

6 is a detailed circuit diagram of the frequency averaging means shown in FIG.

7 is a detailed circuit diagram of the frequency removing means shown in FIG.

* Description of the symbols for the main parts of the drawings *

10, 12: delay circuit 11, 13: differential operator

100: frequency analysis means 110, 120, 230, 330, 340: delay circuit

115: frequency analysis circuit 200: frequency averaging means

210: averaging circuit 220, 250, 260: memory device

240, 350, 360: adder 300: frequency removal means

310, 320: frequency cancellation circuit 400: signal delay means

The present invention relates to a tracking system, and more particularly, to an adaptive moving target filter capable of filtering a noisy signal of an unnecessary moving target from a detection signal for detecting a specific object.

In general, the tracking system transmits an appropriate signal to detect a specific object such as a flying object, and receives a carrier signal reflected from the specific object to filter a required signal.

The filtering process will be described in detail with reference to FIGS. 1 to 3 according to the prior art.

First, referring to the block diagram illustrated in FIG. 1, the input signal is applied to the input terminal of the first delay circuit 10 and at the same time the first differential signal is output together with the output signal of the first delay circuit 10. It is input to the calculator 11. The output signal of the first differential operator 11 is applied to the second delay circuit 12 and is input to the second differential operator 13 together with the output signal of the second delay circuit 12.

In the conventional filter having the above-described configuration, when the n-th signal is input, the n-th signal and the n-th input signal, which are first-delayed by the first delay circuit 10 and the n-th input signal, are compared in the first differential operator 11. Firstly remove signals with the same sign and the same magnitude. (A waveform diagram of FIG. 2) And the output signal of the first differential operator 11 outputs the filtered signal by repeating the above process in the second delay circuit 12 and the second differential operator 13. (B waveform of FIG. 2)

That is, the conventional filter has a configuration such as a double delay line remover, and removes the fixed target signal having the same sign by comparing the magnitude with the received signal input in the previous step each time the signal is input.

However, in the conventional filter, when the effective length of a propagation path between a transmission signal and an observation point is a carrier signal of a fixed target that does not change with time, the Doppler frequency is zero, so the magnitude and sign of the signal are received at every reception. Although the received signal of a moving target such as a non-cloud chaff, etc., the effective length of the propagation path varies with time, the Doppler frequency also changes with each reception and cannot be removed, as shown in FIG. There was a problem.

Accordingly, an object of the present invention is to provide an adaptive mobile target filter capable of outputting an accurate detection signal by filtering a received signal of an unnecessary moving target.

The present invention for achieving the above object is a signal delay device for inputting a first detection signal and a second detection signal that is delayed by 90 ° than the first detection signal inputted by a delay for a predetermined period, and the first, second A frequency analysis device that inputs a detection signal to analyze and output Doppler phase shift values of each signal, and calculates an average Doppler frequency according to the Doppler phase shift values of the first and second detection signals output from the frequency analyzer; A frequency averaging device for outputting Doppler phase shift values of first and second signals with respect to a Doppler frequency, and first and second detection signals which are delayed by the signal delay device for a predetermined time and output from the frequency averaging device And a frequency removing device for removing and outputting a signal equal to the Doppler phase shift value of the signal.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

First, referring to the overall schematic diagram of the present invention with reference to the entire block diagram of the adaptive moving target filter shown in FIG. 4, the input signal is separated into an I signal and a Q signal, and the input signal is conventional. The fixed target signal is removed from the filter and the Q signal is delayed by 90 ° than the I signal. Therefore, input signal I (n) = A cos Φ, Q (n) = A sin Φ, and the next input signal is I (n + 1) = A cos (Φ + ΔΦ), Q (n + 1) = A sin (Φ + ΔΦ), the terminology “I” signal and “Q” signal is sometimes used in describing the operation of the present invention.

The first and second inputs of the signal delay means 400 for delaying the input I and Q signals for a predetermined time period during which the Doppler frequencies Δθ and Δθ generated by the Doppler effect are calculated are input. While input to the terminal is input to the transmission period delay circuit (110, 120) and the frequency analysis circuit 115 provided in the frequency analysis means 100 for analyzing the frequency of the input signal. The frequency analysis circuit 115 inputs an input signal currently input and an input signal of a previous stage delayed by the transmission period delay circuits 110 and 120 to perform a predetermined task, and then an I signal generated by the Doppler effect. And a Doppler phase shift value ΔΦ of the Q signal.

The phase shift value (that is, the values of sinΔΦ and cosΔΦ) generated by the Doppler effect of the I and Q signals output from the frequency analyzing means 100 is input to the frequency averaging means 200 and generated by the Doppler effect. Doppler frequencies Δθ and Δθ are calculated. That is, the Doppler phase shift values (that is, the values of sinΔΦ and cosΔΦ) of the input I signal and the Q signal are input to the averaging circuit 210, and are received in the radar distance direction from the averaging circuit 210. The phase shift values (sinΔΦ and cosΔΦ) are averaged, and the average values (ΣsinΔΦ / L and ΣcosΔΦ / L) of the phase shift values of the I and Q signals are output. The output of the averaging circuit 210 is input to the memory device 220 in which the phase shift value of the moving target, that is, the Doppler frequency tanΔθ is stored, and the average value of the phase shift values of the I and Q signals (ΣsinΦ / L, ΣcosΦ / The phase shift value tanΔθ of the moving target corresponding to L) is output, and the output of the memory device 220 is input to the transmission period delay circuit 230 and the adder 240.

The transmission period delay circuit 230 outputs the Doppler frequency Δθ ₋₁ of the stored previous stage input signal to the adder 240 and simultaneously stores the sin and cos values of the average value of the phase shift values to the memory device 260. The memory device 260 outputs corresponding sin and cos values. The adder 240 adds the Doppler frequency tanΔθ of the current input signal output from the memory device 220 and the Doppler frequency tnaΔθ- ₁ of the previous stage applied by the transmission period delay circuit 230. The sin and cos values of the Doppler frequency (Δθ + Δθ ₋₁ ) are output to the memory device 250 storing the sin, cos (Δθ + Δθ ₋₁ ) values and cos (Δθ + Δθ). _-1 ) Output the value.

By the above process, the frequency averaging means 200 includes (Δθ + Δθ ₋₁ ) and cos (Δθ + Δθ ₋₁ ) values of the Doppler frequency included in the current input signal generated by the Doppler effect. Doppler frequency sin (Δθ) and cos (Δθ) values included in the input signal input in the previous step are output.

The output of the frequency averaging means 200 is input to the frequency removing means 300 to remove unnecessary frequencies of the moving target. First, the ID signal and the QD signal output from the signal delay means 400 are the frequency removing circuit 310. ) Is input to the transmission period delay circuit 330 and is output after being delayed for a predetermined time.

The frequency elimination circuit 310 has a sin (Δθ + Δθ ₋₁ ) value and cos (Δθ + Δθ ₋₁ ) according to the Doppler frequency of the current input signal output from the frequency averaging means 200 in the input I and Q signals. Remove the value and output only the detection signal according to the specific object you want. And the input signal of the previous stage output from the transmission period delay circuit 330 is input to another frequency elimination circuit 320, the frequency elimination circuit 320 is input I (n-1), Q (n- 1) A sin (Δθ) value and a cos (Δθ + Δθ ₋₁ ) value according to the Doppler frequency output from the frequency averaging means 200 are removed from the signal and output.

As described above, a signal of an unnecessary moving target signal which is removed according to the Doppler frequency is removed and output from the adders 350 and 360, and thus a detection signal from which the final Doppler frequency is removed is output.

The following describes the operation relationship of the present invention in more detail with reference to the detailed circuit diagram according to the present invention.

As described above, since the input Q signal is delayed by 90 ° than the I signal, the input signal is

I (n) = A cos Φ, Q (n) = A sin Φ (Equation 1)

And the next input signal is

I (n + 1) = A cos (Φ + ΔΦ), Q (n + 1) = A sin (Φ + ΔΦ) (Equation 2)

Can be expressed as

When the trigonometric function is applied to Equation 2 to calculate the Doppler phase shift values sin ΔΦ and cos ΔΦ of the input I and Q signals as described above,

I (n + 1) = A cosΦ cosΔΦ-sinΦ sinΔΦ),

Q (n + 1) = A sinΦ cosΔΦ + cosΦ sinΔΦ) (Equation 3)

It is expressed as Substituting (Equation 1) into the above (Equation 3),

I (n + 1) = I (n) cosΔΦ-Q (n) sinΔΦ,

Q (n + 1) = Q (n) cosΔΦ + I (n) sinΔΦ) (Equation 4)

Represented by, summarizing the above (Equation 4),

cosΔΦ = [I (n) I (n + 1) + Q (n) Q (n + 1)] / [I ² (n) + Q ² (n)]

and,

sinΔΦ = [I (n) Q (n + 1) -I (n + 1) Q (n)] / [I ² (n) + Q ² (n)]

As a result, phase change signals sinΔΦ and cosΔΦ changed over a predetermined time period of each input signal can be obtained.

5 is a hardware diagram of the above-described formula, and FIG. 5 is a detailed circuit diagram of the frequency analyzing means shown in FIG.

Looking at the configuration first, the input I (n) signal is a multiplier 150 through the memory device 110, the 14-bit shift register 410 and the latch 130, the cos value is stored through the latch (143) 151). The Q (n) signal is supplied to the multipliers 152 and 153 through the latch 144 through the memory device 120 and the 14-bit shift register 420 and the latch 133 in which a sine value is stored.

When the I (n) signal is input, the memory device 110 storing the cosine value outputs the stored I (n-1) signal value and I (n-1) of the memory device 110. ) The output value is output to the memory device 161 through which the multipliers 151 and 152 and the squared value I ² of the I signal are stored through the latch 131.

When the Q (n) signal is input, the memory device 120 storing the sine value outputs the stored Q (n-1) signal value, and the Q (n-1) output value of the memory device 120 The multipliers 150 and 153 and the squared Q ² value of the Q signal are output to the memory device 160 through the latch 132.

The output of the multiplier 150 is inverted in the latch 134 and applied to the adder 170, and the output of the multiplier 152 is applied to the adder 170 through the latch 135. The outputs of the multipliers 151 and 153 are applied to the adder 171 through the latches 136 and 137, respectively.

The output signal of the adder 170 is applied to the memory device 180 in which a log value is stored through the latch 140, and the memory device 180 outputs the corresponding log value. The output of the memory device 180 is applied to the adder 173 through the buffer 185 and the latch 145.

The output signal of the adder 171 which adds the outputs of the multipliers 151 and 153 is applied to the memory device 181 storing the log value through the latch 141, and the output signal of the memory device 181 is It is supplied to the adder 174 through the buffer 186 and the latch 146.

The output signals of the memory devices 160 and 161 in which the squares I ² and Q ^{2 of the} I and Q signals are stored are added to the adder 172 through the latches 138 and 139, respectively, and added to the adder. The output signal of 172 is applied to the log value storage memory device 182 through the latch 142. The log value obtained from the memory device 182 is inverted by the inverter 190, and the inverted output values are applied to the adders 173 and 174, respectively. That is, the output value subtracted by the inverted value is applied to the memory devices 195 and 196 where the antilog values are stored, and the output values output from the memory devices 195 and 196 are the Doppler phase shift values of the I and Q signals. (sinΔΦ, cosΔΦ).

In the operation of the frequency analyzing means configured as described above, when the I (n) Q (n) signal is input, the memory devices 110 and 120 output the value of I (n-1) Q (n-1). The multiplier 150 multiplies the input I (n) signal by Q (n-1) and outputs the multiplier. The multiplier 151 multiplies the I (n) signal input through the latch 130 and the I (n-1) signal output from the memory device 110 and outputs the multiplier 152. The I (n-1) signal output from the memory device 110 and the Q (n) signal applied through the latch 133 are multiplied and output. The multiplier 153 also multiplies the Q (n-1) signal output from the memory device 120 with the Q (n) signal applied through the latch 133 and outputs the multiplier 153.

The output signal I (n) * Q (n-1) of the multiplier 150 is inverted while passing through the latch 134, and the inverted signal and the output signal I (n-1) of the multiplier 152 are inverted. ) Q (n) is added by the adder 170 to output a signal of I (n-1) Q (n) -I (n) Q (n-1). The log value of the output value of the adder 170 is obtained by using the memory device 180 that is already set and stored.

In addition, an adder 171 I (n) that adds the I (n-1) * I (n) output signal of the multiplier 151 and the Q (n-1) * Q (n) output signal of the multiplier 153. -1) A signal of I (n) + Q (n-1) Q (n) is output, and a log value of the output value of the adder 171 is obtained using the memory device 181.

Then, I ² and Q ² are obtained from the memory devices 160 and 161 that store the squares of the output signals of the memory devices 110 and 120, and the sum of the two signals is obtained from the adder 172. The log value corresponding to the output value of the adder 172 is obtained from the memory device 182.

The log values of the memory devices 180 and 181 obtained by the above process are applied to the adders 173 and 174, and the output of the memory device 182 is inverted by the inverter 190 to be added to the adder 173. 174), the result is subtraction. That is, the subtracted output value is applied to the memory devices 195 and 196 in which the antilog values are stored, and the antilog output values output from the memory devices 195 and 196 are the Doppler phase shift values sinΔΦ, I and Q signals. cosΔΦ).

The phase shift values sinΔΦ and cosΔΦ of the received signal generated by the Doppler effect of the I and Q signals output through the above process are applied to the scan number averaging means 200, and are applied to the Doppler frequency of the current input signal. Sin (Δθ + Δθ ₋₁ ) and cos (Δθ + Δθ ₋₁ ), and sin (Δθ) and cos (Δθ) for Doppler frequency of the input signal in the previous step. .

The operation of the frequency averaging means 200 will be described in detail with reference to the detailed circuit diagram of the frequency averaging means shown in FIG.

Looking at the configuration first, the phase change signal (sin ΔΦ, cosΔΦ) changed for a predetermined time is input to the 16-bit shift register (201, 202) while being input to the adders (209, 211) through the latch (203, 204), The outputs of the shift registers 201 and 202 are inverted in the inverters 205 and 206 and applied to the adders 207 and 208. The outputs of the home appliances 207 and 208 are input to the adders 209 and 211 provided at the next stage, and the outputs of the adders 209 and 211 are added to the adders 207 and 208 through the latches 212 and 213. Is returned to the log value storage memory 214,215.

The output signal of the memory device 214 storing the log value for the sine value is supplied to the adder 218 through the latch 216, and the output signal of the memory device 215 for storing the log value for the cosine value. The output signal is inverted at the latch 217 and supplied to the adder 218. The adder 218 adds two input signals and outputs a signal to the memory device 219 in which a tan ⁻¹ value is stored.

The output of the memory device 219 is applied to the transmission period delay circuit 230 through the latch 211 and to the adder 240 through the latch 223. The output signal of the transmission period delay circuit 230 is applied to the adder 240 through the latch 222 and the sine value and the cosine value of the sine value and the cosine value of the Doppler frequency Δθ + Δθ ₋₁ through the latch 224. Supplied to 260. The output signal of the adder 240 is supplied to the storage memory device 250 having a sine value and a cosine value having a Doppler frequency of Δθ + Δθ ₋₁ . The outputs of the memory devices 250 and 260 may have sinΔθ and cosΔθ values according to the Doppler frequency through the latches 225 and 227, and sin (Δθ + Δθ ₋₁ ) according to the Doppler frequency through the latches 226 and 228. A value and a cos (Δθ + Δθ ₋₁ ) value are output to the frequency removing unit 300.

The operation of the frequency average circuit having the above configuration will be described.

The phase change signals sinΔΦ and cosΔΦ that have been changed for a predetermined time output from the frequency analyzing means are applied to the adders 209 and 211 and the 16-bit shift registers 201 and 202. The shift registers 201 and 202 temporarily store the input signals sinΔΦ and cosΔΦ while the next signal is applied, and output the phase change signals sinΔΦ ₋₁ and cosΔΦ ₋₁ . The output signals of the shift registers 201 and 202 are inverted by the inverters 205 and 206 and input to the adders 207 and 208, and the adders 207 and 208 are fed back to the next stage. The output signal of the shift register 201 is subtracted from the output signal of 211 and output to the adders 209 and 211. The adders 209 and 211 add output signals of the adders 207 and 208 and phase change signals sinΔΦ and cosΔΦ inputted in various values in the radar distance direction L to add the output values to the adders 207 and 208. The average signal ΣsinΔΦ / L value and ΣcosΔΦ / L value are output based on the accumulated value.

The average signal ΣsinΔΦ / L and ΣcosΔΦ / L are input to the memory devices 214 and 215 to output corresponding log values, and the log value for the ΣsinΔΦ / L values is added through the latch 216 to the adder 218. ), And the log value for the ΣcosΔΦ / L value is inverted in the latch 217 and outputted to the adder 218.

Therefore, the adder 218 subtracts and outputs the log value of ΣcosΔΦ / L from the log value of ΣsinΔΦ / L input through the latch 216, and the output of the adder 218 is applied to the memory device 219. The final Doppler frequency is determined by outputting the antilog value. In other words, in order to process the division required for the circuit configuration, the general formula for the log is used, that is, the log value of the number of jets and the number of jets is calculated, and the change over time is performed by taking an anti-log on the signal output through the subtraction circuit. One phase change, the Doppler frequency (Δθ) can be obtained.

When the Doppler frequency Δθ output from the memory device 219 is input to the transmission period delay circuit 230 and is input to the adder 240, the transmission period delay circuit 230 receives the signal Δθ. The Doppler frequency Δθ ₋₁ input and temporarily stored in the previous step is output to the adder 240 and the memory device 260.

The adder 240 adds the Doppler frequency Δθ ₋₁ applied by the transmission period delay circuit 230 and the Doppler frequency Δθ output from the memory device 219, and the Doppler frequency Δθ ₋₁ + Δθ. Is output to the memory device 250, and the memory device 250 outputs a sine value and a cosine value with respect to the input Doppler frequency ((Δθ ₋₁ + Δθ), and the memory device 260 is also input. The sine and cosine of the frequency Δθ are output.

The sine and cosine of the Doppler frequency (Δθ ₋₁ + Δθ) and the sine and cosine of the Doppler frequency (Δθ) output through the above process are input to the frequency removing unit 300 and input. This eliminates the Doppler frequencies of the signal and the Q signal.

The frequency removing means will be described in detail with reference to FIG. 7.

Looking at the configuration first, the I signal delayed for a predetermined time in the 16-bit shift register 410 is input to the transmission period delay circuit 331 through the latch 311 and at the same time the cos (Δθ _-1 output from the frequency averaging means 200) A second input terminal of the multiplier 301 that inputs a value of + Δθ) to the first input terminal. The Q signal delayed for a predetermined time in the 16-bit shift register 460 is input to the transmission period delay circuit 332 through the latch 312 and at the same time, the sin (Δθ ₋₁ + Δθ) value output from the frequency averaging means 200. Is input to the multiplier 302 which serves as the first input.

The cos (Δθ ₋₁ + Δθ) value output from the frequency averaging means 200 is input to the first input terminal of the multiplier 304, and the second input terminal of the multiplier 304 is the shift register ( A Q signal, which is an output signal of 420, is input, and a sin (Δθ ₋₁ + Δθ) value output from the frequency averaging means 200 is input to the first input terminal of the multiplier 303, and the multiplier ( The second input terminal of 303 inputs an I signal which is an output signal of the shift register 410.

The output signals of the multipliers 301 and 302 are input to the adder 305, and the signals of the multiplier 303 inverted by the inverter 307 and the signal output from the multiplier 304 are added to the adder ( At 306). The output signals of the adders 305 and 306 are applied to the first input terminals of the adders 362 and 352 through the latches 308 and 309.

The I and Q signals which are firstly delayed by the transmission period delay circuits 331 and 332 are input to the transmission period delay circuits 341 and 342 for the second signal delay through the latches 313, 314, 315, and 316. The output signals of the transmission period delay circuits 341 and 342 are applied to the second input terminals of the adders 362 and 352 through the latches 318, 317, 319, and 357.

The cos (Δθ) output from the frequency averaging means 200 is applied to the first input terminals of the multipliers 321 and 324, and the second input terminal of the multipliers 321 and 324 is the transmission period delay circuit. The primary delayed I and Q signals, which are the output signals of 331 and 332, are input, respectively. In addition, sin (Δθ) output from the frequency averaging means 200 is applied to the first input terminal of the multipliers 322 and 323, and the second input terminal of the multipliers 322 and 323 is the transmission period delay circuit. The primary delayed I and Q signals, which are the output signals of 331 and 332, are input, respectively.

The output signals of the multipliers 321 and 322 are added by the adder 327, and the output signals of the multipliers 323 which are inverted by the inverter 325 and the output signals of the multipliers 324 are the adders 326. ) Is added. The output signals of the adders 326 and 327 are inverted at the latches 328 and 329 and applied to the adders 361 and 351, and the output signals of the adders 362 and 352 are 1/2 times the multipliers 353 and 354. And the second input terminal of the adders 361 and 351 through the latches 355 and 356. The output signals of the adders 351 and 361 are outputted through the latches 358 and 359, and the original detection signal from which the Doppler frequency generated by the Doppler effect is removed is removed.

The operation of the frequency removing means by the above configuration will be described below.

Currently input signals are I (n) = A cos (θ + Δθ + Δθ ₋₁ ) and Q (n) = A sin (θ + Δθ + Δθ ₋₁ ), and the signal input in the previous step is I (n) -1) = A cos (θ + Δθ) and Q (n−1) = A sin (θ + Δθ).

And the cos (Δθ + Δθ ₋₁ ) and sin (Δθ + Δθ ₋₁ ) values for the Doppler frequency in the current input signal output from the frequency averaging means 200, and the Doppler frequency in the signal input in the previous step. The cos (Δθ) and sin (Δθ) values for are input.

Therefore, since the purpose of the frequency removing means is to remove the Doppler phase frequencies Δθ and Δθ ₋₁ due to the Doppler effect, unnecessary signals are removed using the output value of the frequency averaging means 200.

As an example, the process of removing the Doppler frequency is described with the (n-1) th I signal and the Q signal, and the multiplier 321 is a cos (Δθ) signal output from the frequency averaging means 200 and the first delayed I. Cos (Δθ) * A cos (θ + Δθ) is output by multiplying the signal A cos (θ + Δθ). The multiplier 322 multiplies the sin (Δθ) signal output from the frequency averaging means 200 with A sin (θ + Δθ), which is the first-delayed Q signal, and sin (Δθ) * A sin (θ + Δθ). Outputs The multiplier 323 multiplies the sin (Δθ) signal output from the frequency averaging means 200 with A cos (θ + Δθ), which is the first delayed I signal, to obtain sin (Δθ) * A cos (θ + Δθ). The multiplier 324 outputs a cos (Δθ) + A sin (θ + Δθ) signal.

The output signals of the multipliers 321 and 322 are added by the adder 327 and output as A cos (θ + Δθ) * cos (Δθ) + A sin (θ + Δθ) * sin (Δθ). The output of the multiplier 323 and the output of the multiplier 324 passing through 325 are added in the adder 326 to be A sin (θ + Δθ) * cos (Δθ) -A cos (θ + Δθ) * It is output as sin (Δθ).

When the output signal of the adder 327 is arranged using a trigonometric function, it is expressed as A cos [(θ + Δθ)-(Δθ)], and the output signal of the adder 326 is arranged using a trigonometric function. In view of this, it is expressed as A sin [(θ + Δθ) − (Δθ)]. That is, the output signals of the adders 327 and 326 are sin (Δθ), which is the Doppler frequency, from sin (θ + Δθ), which is the nth I-th signal, and cos (θ + Δθ), which is the Q signal. The signal minus cos (Δθ) is output.

The above process is applied to the multipliers 301, 302, 303, 304, the inverters 307, and the adders 305, 306 for inputting the n-th I signal and the Q signal, and thus the adder 305 , The output signal of 306 is removed after the Doppler frequency Δθ + Δθ ₋₁ is output, and the frequency is multiplied by a predetermined amount by the 1/2 multipliers 353 and 354. The n-th Doppler frequency through the 1/2 multipliers 353 and 354 is removed, and the n-th Doppler frequency output from the adders 326 and 327 and inverted by the latches 328 and 329 is removed. The added signal is added by the adders 361 and 351 and output.

As described above, the present invention removes unnecessary signals according to a fixed target signal using a conventional filter from a received detection signal, and removes unnecessary targets such as rain and clouds from the detection signal from which the fixed target signal is removed. Since the Doppler frequency according to the signal can be removed, the accurate detection signal of the moving object can be output.

Claims (5)

A signal detecting means for inputting a first detection signal and a second detection signal which is delayed by 90 ° from the first detection signal and delaying the input signal for a predetermined period, and outputting the first and second detection signals to input the first and second detection signals. And a Doppler phase of the first and second signals with respect to the calculated Doppler frequency by calculating an average Doppler frequency according to the Doppler phase shift values of the first and second detection signals outputted from the frequency analysis means. A frequency averaging means for outputting a shift value and first and second detection signals delayed by the signal delay means for a predetermined time to remove the same signal as the doppler phase shift value of the first and second signals output from the frequency averaging means; Adaptive moving target filter, characterized in that it comprises a frequency removing means for outputting. 2. The apparatus of claim 1, wherein the frequency averaging means comprises: averaging means for averaging one or two Doppler phase shift values of the frequency analyzing means analyzed and output in the detection distance direction, and a Doppler frequency according to the output of the averaging means; And a Doppler phase shift value storage means for outputting first and second Doppler phase shift values stored according to the Doppler frequency output from the calculation means. 3. The apparatus of claim 2, wherein the frequency averaging means comprises: delay means for delaying and outputting the Doppler frequency output from the frequency calculating means for a predetermined time, and adding and outputting the output of the delay means and the output of the frequency calculating means. Adaptive moving target filter, characterized in that it further comprises means. 4. The apparatus of claim 3, wherein the Doppler phase shift value storage means comprises: first storage means for outputting Doppler phase shift values of first and second signals according to the output Doppler frequency of the delay means, and an output Doppler frequency of the adder means; And second storage means for outputting the Doppler phase shift values of the first and second signals according to the present invention. 5. The apparatus of claim 4, wherein the frequency removing means comprises: delay means for delaying and outputting the output signal of the signal delay means, and outputting the output signal of the second storage means by removing the output signal from the signal delay means; First removing means, second removing means for removing and outputting the output signal of the first storage means from the output signal of the delaying means, second delay means for delaying the output signal of the delaying means for a predetermined time and outputting it; And adding means for adding and outputting the output signal of the second delay means and the output signals of the first and second removing means.