KR970004076B1 - Column Redundancy Device for Semiconductor Memory Devices - Google Patents

Abstract

none.

Description

Column Redundancy Device for Semiconductor Memory Devices

1 is a detailed circuit diagram of a column redundancy device of a conventional semiconductor memory device.

2 is a detailed circuit diagram of a column redundancy device of a semiconductor memory device according to the present invention.

* Description of the symbols for the main parts of the drawings *

1: Normal decoder 2: Redundant decoder

3A and 3B: first and second memory cell arrays

4A and 4B: first and second logical signal generator

Tr-nd1 and Tr-nd2: first and second transfer transistors

Tr-sd1 and Tr-sd2: third and fourth transfer transistors

in1 and in2: first and second memory cell array block selection signals

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a column redundancy device of a semiconductor memory device. In particular, when a column address signal line is commonly used in a dynamic random access memory (DRAM), one memory cell array is used. In the event of a defect, the defective column is converted into a preliminary column. The output signals of two or more programmable redundancy decoders are commonly used for one line, and a regular data output line and a preliminary data line are used for each memory cell array. The present invention relates to a column redundancy device of a semiconductor memory device capable of increasing redundancy efficiency by connecting data output lines and selecting output paths of a normal data column and a preliminary data column as a memory cell array block selection signal.

In general, a column redundancy device of a semiconductor memory device has a normal decoder and a redundancy decoder connected to each memory cell array using a column address signal line in common and one data from the memory cell array. The output lines are connected to each other. However, since one data output line is connected to each memory cell array, the redundancy efficiency is low. Next, a column rendition device of a conventional semiconductor memory device will be described with reference to FIG. 1.

In the case of normal operation without repair, the redundancy decoder 2 is not selected and the normal decoder 1 corresponding to the column address is selected. For example, when the first normal decoder 1 is selected, the memory cell array is selected. Bit lines b11 and b21 of the memory cells corresponding to the output signal Y1 of the normal decoder 1 are selected from 3A and 3B to store data stored in the cells connected to the selected bit lines b11 and b21. The first data output line and the second data output line are respectively output. In addition, when the repair is performed but the normal column address signal is input instead of the repaired column address, the operation is the same as described above.

However, when a repaired and repaired column address signal is input, the redundancy decoder 2 corresponding to the repaired column address is selected. For example, when the first redundancy decoder is selected, the memory cell arrays 3A and 3B are selected. ), The bit lines rb1 and rb3 of the memory cells corresponding to the output signal SY1 of the redundancy decoder 2 are selected, and the data stored in the cell connected to the selected bit lines rb1 and rb3 is the first data output line. And a second data output line.

However, when the address signal lines for selecting columns are commonly used as described above, when a defect occurs in one memory cell array, the defective column must be converted into a spare column. In this case, the regular column is changed to a spare column in another memory cell array. Therefore, only the number of redundancy decoders connected to the column address signal lines can be converted. That is, if a column address signal line is commonly used for n memory cell arrays and there are m redundancy decoders in each memory cell array, the total number of spare columns is (m × n), but only m defective columns are found. Can be converted into a preliminary column.

Therefore, in the present invention, the output signals of two or more programmable redundancy decoders are commonly used on one line, and normal data is connected to each memory cell array by connecting the output line and the preliminary data output line, respectively, to the normal data as the memory cell array block selection signal. It is an object of the present invention to provide a column redundancy device for a device of a semiconductor memory capable of increasing redundancy efficiency by selecting output paths of columns and preliminary data columns.

In order to achieve the above object, the present invention provides a plurality of normal decoders 1 to receive a regular column address signal, a repaired spare column address signal and a memory cell array block selection signal, and each connected to a common output signal line. A plurality of redundant decoders 2, first switching means for switching normal bit lines by the output signal of the normal decoder 1, and spare bit lines by the output signals of the redundancy decoder 2 A first logic signal generator comprising a second switching means for inputting the first memory cell array block selection signal and a plurality of logic elements that receive two output logic signals from the redundancy decoder 2; 4A) and the spare bit line and the first data output line of the first memory chamber array block 3A are switched in accordance with the output signal of the first logical signal generator 4A. Fourth switching means for switching the normal bit line and the first data output line of the first memory cell array block 3A in accordance with a third switching means and another output signal of the first logical signal generator 4A. And a second logic signal generator 4B comprising a plurality of logic elements for receiving a second memory cell array block signal signal and an output signal of the redundancy decoder 2 and outputting two different logic signals; Fifth switching means for switching the preliminary bit line and the second data output line of the second memory cell array 3B according to the output signal of the second logical signal generator 4B, and the second logical signal generator 4B. And sixth switching means for switching the normal bit line and the second data output line of the second memory cell array 3B according to another output signal.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

FIG. 2 is a detailed circuit diagram of a column redundancy device of a semiconductor memory device according to the present invention. In the normal operation, when the normal decoder 1 is selected by the column address signal, the transistors Q1 and Q2 are turned on. Since there is no input of the block selection signals in1 and in2, the outputs of the NAND gates G1 and G2 become "High", and the outputs of the inverting gates G3 and G5 become "Low", so that the first and second transfer transistors ( Tr-nd1 and Tr-nd2 are turned on to output data stored in memory cells connected to bit lines b11 and b21 through the first and second data output lines, respectively.

On the other hand, when the redundancy decoder 2 is selected by the repaired column address signal, for example, when the first memory cell array block selection signal in1 is input to the selected redundancy decoder 2, the transistors Q3 and Q4) is turned on, and the output of the NAND gate G1 becomes "Low", and the third transfer transistor Tr-sd1 is turned on by the "Low" potential via the inversion gates G3 and G4, thereby turning on the bit line ( Data stored in the memory cell connected to rb11 is output through the first data output line.

In addition, when the redundancy decoder 2 is selected by the repaired column address signal and the second memory cell array block selection signal in2 is input to the predetermined redundancy decoder 2, the transistors Q3 and Q4 are turned on. Since the signal via the NAND gate G2 and the inverting gates G5 and G6 is kept in the “Low” state, the fourth transfer transistor Tr-sd2 is turned on and stored in the memory cell connected to the bit line rb21. Data is output via the second data output line.

As described above, according to the present invention, the output signals of two or more programmable redundancy decoders are commonly used in one line, and a regular data output line and a spare data output line are formed in each memory cell array to select a memory cell array block selection signal. By selecting the output paths of the rectified data column and the preliminary data column, there is an excellent effect of increasing the redundancy efficiency.

Claims (9)

In a column redundancy device of a semiconductor memory device, a plurality of normal decoders (1) that receive a regular column address signal, a repaired spare column address signal, and a memory cell array block selection signal are input to each of which is connected to a common output signal line. A plurality of redundant decoders 2, first switching means for switching normal bit lines by the output signal of the normal decoder 1, and spare bit lines by the output signals of the redundancy decoder 2 A first logic signal generator comprising a second switching means for inputting the first memory cell array block selection signal and a plurality of logic elements for receiving two output signals from the redundancy decoder 2 and outputting two different logic signals 4A and the spare bit line and the first data output of the first memory cell array block 3A in accordance with the output signal of the first logical signal generator 4A. Third switching means for switching a line, and switching the normal bit line and the first data output line of the first memory cell array block 3A according to another output signal of the first logical signal generator 4A. A second logic signal generator 4B comprising four switching means, a plurality of logic elements for receiving a second memory cell array block selection signal and an output signal of the redundancy decoder 2 and outputting two different logic signals; Fifth switch means for switching the spare bit line and the second data output line of the second memory cell array 3B according to the output signal of the second logical signal generator 4B, and the second logical signal generator ( And a sixth switching means for switching the normal bit line and the second data output line of the second memory cell array (3B) in accordance with another output signal of 4B). 2. The transistor according to claim 1, wherein the first switching means is connected between the first normal bit line and the fourth switching means and is switched in accordance with an output signal of the normal decoder 1 and the second normal bit. And a transistor (Q2) connected between the line and the sixth switching means and switched according to the output signal of the normal decoder (1). 2. The transistor according to claim 1, wherein the second switching means is connected between the first preliminary bit line and the third switching means and is switched in accordance with an output signal of the redundancy demodulator 2 and the second preliminary. And a transistor (Q4) connected between the bit line and the fifth switching means and switched according to the output signal of the redundancy decoder (2). 2. The transistor of claim 1, wherein the third switching means comprises a transistor (Tr-sd1) connected between the transistor Q3 and the first data output line and switched in accordance with an output signal of the first logical signal generator 4A. The column redundancy device of a semiconductor memory device, characterized in that. The transistor (Tr-nd1) according to claim 1, wherein said fourth switching means is connected between said transistor (Q1) and a first data output line and switched in accordance with another output signal of said first logical signal generator (4A). A column redundancy device of a semiconductor memory device, characterized in that consisting of. 2. The transistor of claim 1, wherein the fifth switching means comprises a transistor Tr-sd2 connected between the transistor Q4 and the second data output line and switched in accordance with an output signal of the second logical signal generator 4B. The column redundancy device of a semiconductor memory device, characterized in that. The transistor Tr-nd2 according to claim 1, wherein the sixth switching means is connected between the transistor Q2 and the second data output line and switched according to another output signal of the second logical signal generator 4B. Column redundancy device of a semiconductor memory device, characterized in that consisting of. The NAND gate generator of claim 1, wherein the first logical signal generator 4A includes a NAND gate G1 that receives the first memory cell array block selection signal and an output signal of the redundant decoder 2, and the NAND gate G1. And a reversal gate (G3 and G4) connected in series with each other. 2. The NAND gate generator of claim 1, wherein the second logical signal generator 4B includes a NAND gate G2 that receives the second memory cell array block selection signal and an output signal of the redundancy decoder 2, and the NAND gate G2. And a redundancy gate (G5 and G6) connected in series from each other.