[go: up one dir, main page]

KR970003189A - Semiconductor Memory Device with Multiple Ground Power Supplies - Google Patents

Semiconductor Memory Device with Multiple Ground Power Supplies Download PDF

Info

Publication number
KR970003189A
KR970003189A KR1019950015221A KR19950015221A KR970003189A KR 970003189 A KR970003189 A KR 970003189A KR 1019950015221 A KR1019950015221 A KR 1019950015221A KR 19950015221 A KR19950015221 A KR 19950015221A KR 970003189 A KR970003189 A KR 970003189A
Authority
KR
South Korea
Prior art keywords
voltage
voltage level
level
power supply
ground voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
KR1019950015221A
Other languages
Korean (ko)
Other versions
KR0142972B1 (en
Inventor
이상보
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950015221A priority Critical patent/KR0142972B1/en
Publication of KR970003189A publication Critical patent/KR970003189A/en
Application granted granted Critical
Publication of KR0142972B1 publication Critical patent/KR0142972B1/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
    • G11C5/146—Substrate bias generators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/08—Control thereof

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dram (AREA)

Abstract

1. 청구범위에 기재된 발명이 속한 기술분야1. TECHNICAL FIELD OF THE INVENTION

반도체 메모리장치.Semiconductor memory device.

2. 발명이 해결하려고 하는 기술적 과제2. The technical problem to be solved by the invention

반도체 메모리 장치에 서로 다른 전압레벨을 갖는 두 종류의 접지전압을 공급하여 반도체 메모리장치의 동작을 안정화시키고 전력소모를 감소시킴.By supplying two types of ground voltages having different voltage levels to the semiconductor memory device, the operation of the semiconductor memory device is stabilized and power consumption is reduced.

3. 발명의 해결 방법의 요지3. Summary of the Solution of the Invention

내부접지전압을 동작전원으로 입력하는 제1회로들과 외부접지전압을 동작전원으로 입력하는 제2회로들로 구성되며, 상기회로들이 메모리코어 및 주변회로들인 반도체 메모리장치가, 제1전압레벨을 갖는 외부전원전압과, 제4 전압레벨을 갖는외부접지전압과, 제2전압레벨의 내부전원전압을 발생하는 수단과, 제3전압레벨의 내부접지전압을 발생하는 수단들을 구비하여, 내부접지전압을 칩내부의 접지전압으로 공급하고 외부접지전압을 칩 내부의 특정 회로에 공급하여 전압 스윙폭을작게 유지하므로써 전력 소모를 감소시킴.And a first circuit for inputting an internal ground voltage as an operating power source and a second circuit for inputting an external ground voltage as an operating power source, wherein the semiconductor memory device, wherein the circuits are memory cores and peripheral circuits, sets the first voltage level. An internal ground voltage comprising an external power supply voltage having an external power supply voltage, an external ground voltage having a fourth voltage level, means for generating an internal power supply voltage having a second voltage level, and means for generating an internal ground voltage having a third voltage level. Supply power to the ground voltage inside the chip and supply the external ground voltage to a specific circuit inside the chip to keep the voltage swing width small to reduce power consumption.

4. 발명의 중요한 용도4. Important uses of the invention

반도체 메모리장치에서 서로 다른 레벨의 접지전압을 공급하여, 별도의 백바이어스전원발생기를 사용하지 않으며, 승압전압을 효율적으로 발생하고, 메모리셀의 누설전류를 감소시키는 동시에 센스앰프의 감지속도를 향상시킴.Provides ground voltages of different levels in semiconductor memory devices, eliminating the need for a separate back bias power generator, efficiently generating boosted voltages, reducing leakage current in memory cells, and improving the detection speed of sense amplifiers. .

Description

복수의 접지전원을 갖는 반도체 메모리장치Semiconductor Memory Device with Multiple Ground Power Supplies

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명에 따른 반도체 메모리장치의 블럭 구성을 도시하는 도면, 제2도는 제1도 중 액티브 모드에서 내부 전원전압을 발생하는 회로의 구성을 도시하는 도면, 제3도는 제1도 중 대기모드에서 내부 전원전압을 발생하는 회로의 구성을 도시하는 도면, 제4도는 본 발명에 따라 제1도에서 내부 접지전압과 외부접지전압 EVss의 레벨을 쉬프트하는 회로의 구성을 도시하는 도면이고, 제4B도는 상기 제4A 도의 각 부 동작 특성을 도시하는 파형도.FIG. 1 is a block diagram showing a semiconductor memory device according to the present invention, FIG. 2 is a block diagram showing a circuit for generating an internal power supply voltage in an active mode of FIG. 1, and FIG. 4 is a diagram showing the configuration of a circuit for generating an internal power supply voltage in the mode; FIG. 4 is a diagram showing a configuration of a circuit for shifting the levels of the internal ground voltage and the external ground voltage EVss in FIG. 1 according to the present invention; 4B is a waveform diagram showing respective sub-operation characteristics of FIG. 4A.

Claims (14)

내부접지전압을 동작전원으로 입력하는 제1회로들과 외부접지전압을 동작전원으로 입력하는 제2회로들로구성되며, 상기 회로들이 메모리코어 및 주변회로들인 반도체 메모리장치에 있어서, 제1전압레벨을 갖는 외부전원전압을입력하는 단자와, 제4전압레벨을 갖는 외부접지전압을 입력하는 단자와, 차동증폭기 구성을 가지며, 제2전압레벨의 기준전압과 출력전압의 레벨을 비교하여 상기 제2전압레벨을 유지하는 내부전원전압을 발생하는 수단과, 차동증폭기 구성을가지며, 제3전압레벨의 기준전압과 출력전압의 레벨을 비교하여 상기 제3전압레벨을 유지하는 내부접지전압을 발생하는수단과, 상기 제1회로들과 제2회로들 사이에 연결되며, 상기 내부접지전압의 레벨을 외부접지전압의 레벨로 쉬프트하는수단을 구비하여, 상기 내부접지전압을 칩 내부의 접지전압으로 공급하고 상기 외부접지전압을 칩 내부의 특정 회로에 공급하여 전압 스윙폭을 작에 유지하므로서 전력 소모를 감소시키는 것을 특징으로 하는 반도체 메모리장치.A semiconductor memory device comprising first circuits for inputting an internal ground voltage to an operating power supply and second circuits for inputting an external ground voltage to an operating power source, wherein the circuits are memory cores and peripheral circuits, wherein the first voltage level is provided. A terminal for inputting an external power supply voltage having a voltage, a terminal for inputting an external ground voltage having a fourth voltage level, and a differential amplifier configuration, and comparing the reference voltage of the second voltage level with the level of the output voltage Means for generating an internal power supply voltage for maintaining the voltage level, and means for generating an internal ground voltage for maintaining the third voltage level by comparing the reference voltage of the third voltage level with the level of the output voltage. And means for shifting the level of the internal ground voltage to a level of the external ground voltage connected between the first circuits and the second circuits, thereby converting the internal ground voltage into a chip. Supply voltage to a ground portion, and the semiconductor memory device, comprising a step of reducing the power consumption hameuroseo maintain the voltage swing width supplied by the operation of the external ground voltage to a particular circuit of the chip. 제1항에 있어서, 상기 내부접지전압을 발생하는 수단이, 전류구동능력이 큰 차동증폭기의 구성을 가지며,액티브모드신호에 의해 활성화되어 상기 제3전압레벨로 액티브모드의 내부접지전압을 발생하는 수단과, 전류구동능력이상대적으로 작은 차동증폭기의 구성을 가지며, 대기모드신호에 의해 활성화되어 상기 제3전압레벨로 대기모드의 내부접지전압을 발생하는 수단으로 구성된 것을 특징으로 하는 반도체 메모리장치.The method of claim 1, wherein the means for generating the internal ground voltage has a configuration of a differential amplifier having a large current driving capability, and is activated by an active mode signal to generate an internal ground voltage in an active mode at the third voltage level. Means and a means for generating a differential amplifier with a current amplifier having a relatively small current driving capability, the means being activated by a standby mode signal to generate an internal ground voltage in the standby mode at the third voltage level. 제1항 또는 제2항에 있어서, 상기 레벨쉬프트수단이, 상기 내부전원전압으로 풀업하는 트랜지스터와 상기내부접지전압으로 풀다운하는 트랜지스터가 직렬연결되는 입력단과, 상기 내부전원전압으로 풀업하는 트랜지스터와 상기외부접지전압으로 풀다운하는 트랜지스터가 직렬연결되며, 상기 풀다운 트랜지스터의 드레인전극이 출력노드가 되는 출력단으로 구성되며,상기 입력단의 풀업트랜지스터의 게이트전극이 입력신호에 연결되고 상기 출력단의 풀업트랜지스터의 게이트전극이 반전된 입력신호에 연결되며, 상기 풀다운트랜지스터들의 게이트전극이 각각 상대 풀다운 트랜지스터의 드레인전극에 연결되는 것을 특징으로 하는 반도체 메모리장치.The power supply according to claim 1 or 2, wherein the level shifting means comprises: an input terminal to which a transistor pulled up to the internal power supply voltage and a transistor pulled down to the internal ground voltage are connected in series; a transistor pulled up to the internal power supply voltage; A transistor pulled down to an external ground voltage is connected in series, and a drain electrode of the pull-down transistor is configured as an output node. The gate electrode of the pull-up transistor of the input terminal is connected to an input signal and the gate electrode of the pull-up transistor of the output terminal. And a gate electrode of the pull-down transistors is connected to a drain electrode of a relative pull-down transistor. 제3항에 있어서, 상기 제4전압레벨이 OV이고, 상기 제3전압레벨이 1V이며, 상기 제2전압레벨이 2.5V이고,상기 제1전압레벨이 3.5V인 것을 특징으로 하는 반도체 메모리장치.4. The semiconductor memory device of claim 3, wherein the fourth voltage level is OV, the third voltage level is 1V, the second voltage level is 2.5V, and the first voltage level is 3.5V. . 제1전압레벨의 외부전원전압을 입력하는 수단과, 제2전압레벨의 내부전원전압을 발생하는 수단과, 제3전압레벨의 내부접지전압을 발생하는 수단과, 제4전압레벨의 외부접지전압을 입력하는 수단을 구비하는 반도체 메모리장치의백바이어스전원 공급회로에 있어서, 상기 내부전원전압과 출력노드 사이에 연결되며 게이트전극이 입력신호에 연결되는풀업트랜지스터와, 상기 출력노드와 내부접지전압 사이에 연결되며 게이트전극이 상기 입력신호에 연결되고 백게이트전극이 상기 외부접지전압에 연결되는 풀다운트랜지스터를 구비하여, 내부접지전압을 접지전압으로 사용하는 회로에서 상기외부전원전압을 백바이어스전원을 사용하는 것을 특징으로 하는 반도체 메모리장치의 백바이어스전원 공급회로.Means for inputting an external power supply voltage at a first voltage level, means for generating an internal power supply voltage at a second voltage level, means for generating an internal ground voltage at a third voltage level, and external ground voltage at a fourth voltage level. A back bias power supply circuit of a semiconductor memory device, comprising: a pull-up transistor connected between the internal power supply voltage and an output node and having a gate electrode connected to an input signal, and between the output node and the internal ground voltage. A pull down transistor having a gate electrode connected to the input signal and a back gate electrode connected to the external ground voltage, wherein the external power voltage is used as a back bias power source in a circuit using an internal ground voltage as a ground voltage. A back bias power supply circuit for a semiconductor memory device, comprising: 제5항에 있어서, 상기 제4전압레벨이 0V이고, 상기 제3전압레벨이 1V이며, 상기 제2전압레벨이 2.5V이고,상기 제1전압레벨이 3.5V인 것을 특징으로 하는 반도체 메모리장치의 백바이어스전원 공급회로.The semiconductor memory device according to claim 5, wherein the fourth voltage level is 0V, the third voltage level is 1V, the second voltage level is 2.5V, and the first voltage level is 3.5V. Back bias power supply circuit. 제1전압레벨의 외부전원전압을 입력하는 수단과, 제2전압레벨의 내부전원전압을 발생하는 수단과, 제3전압레벨의 내부접지전압을 발생하는 수단과, 제4전압레벨의 외부접지전압을 입력하는 수단을 구비하는 반도체 메모리장치의센스앰프에 있어서, 제1비트라인과 접속노드 사이에 연결되며 게이트전극이 제2비트라인에 연결되는 제1모오스트랜지스터들과, 상기 접속노드와 제2비트라인 사이에 연결되며 게이트전극이 상기 제1비트라인에 연결되는 제2모오스트랜지스터들과, 상기 접속점들과 상기 외부접지전압 사이에 연결되며 게이트전극이 제1제어신호에 연결되는 제3모오스트랜지스터와,상기 접속점들과 상기 내부접지전압 사이에 연결되며 게이트전극이 제2제어신호에 연결되는 제4모오스트랜지스터로 구성되어, 초기 센스앰프 구동시 상기 제1제어신호를 활성화시켜 초기 센스앰프의 구동속도를 증가시키고 데이타 재저장시 상기 제2제어신호를 활성화시켜 전류 소모를 감소시키는 것을 특징으로 하는 반도체 메모리장치의 센스앰프.Means for inputting an external power supply voltage at a first voltage level, means for generating an internal power supply voltage at a second voltage level, means for generating an internal ground voltage at a third voltage level, and external ground voltage at a fourth voltage level. A sense amplifier of a semiconductor memory device having a means for inputting a semiconductor device comprising: first MOS transistors connected between a first bit line and a connection node and a gate electrode connected to a second bit line, and the connection node and the second node; Second MOS transistors connected between the bit lines and having a gate electrode connected to the first bit line, and a third MOS transistor connected between the connection points and the external ground voltage and having a gate electrode connected to the first control signal. And a fourth MOS transistor connected between the connection points and the internal ground voltage and having a gate electrode connected to a second control signal, wherein the first sense amplifier is driven when the initial sense amplifier is driven. And activating a control signal to increase the driving speed of the initial sense amplifier and reducing the current consumption by activating the second control signal when restoring data. 제7항에 있어서, 상기 센스앰프가 엔센스앰프인 것을 특징으로 하는 반도체 메모리장치의 센스앰프.8. The sense amplifier of claim 7, wherein the sense amplifier is an sense amplifier. 제8항에 있어서, 상기 제4전압레벨이 OV이고, 상기 제3전압레벨이 1V이며, 상기 제2전압레벨이 2.5V이고,상기 제1전압레벨이 3.5V인 것을 특징으로 하는 반도체 메모리장치의 백바이어스전원 공급회로.The semiconductor memory device of claim 8, wherein the fourth voltage level is OV, the third voltage level is 1V, the second voltage level is 2.5V, and the first voltage level is 3.5V. Back bias power supply circuit. 제1전압레벨의 외부전원전압을 입력하는 수단과, 제2전압레벨의 내부전원전압을 발생하는 수단과, 제3전압레벨의 내부접지전압을 발생하는 수단과, 제4전압레벨의 외부접지전압을 입력하는 수단을 구비하여 반도체 메모리장치의 승압전압발생회로에 있어서, 외부전원전압과 내부접지전압의 레벨로 스윙되는 펌핑입력신호를 외부전원전압과 외부접지전압의 레벨로 쉬프트하는 수단과, 상기 외부전원전압과 외부접지전압 사이에 연결되며 상기 레벨쉬프트수단의 출력단에 입력단이 연결되는 인버터회로와, 상기 인버터회로의 출력단과 출력노드 사이에 연결되는 펌핑 캐패시터와, 상기 외부전원전압과 출력노드 사이에 연결되는 다이오드 접속의 트랜지스터로 구성된 것을 특징으로 하는 반도체 메모리장치의 승압전압발생회로.Means for inputting an external power supply voltage at a first voltage level, means for generating an internal power supply voltage at a second voltage level, means for generating an internal ground voltage at a third voltage level, and external ground voltage at a fourth voltage level. A booster voltage generation circuit of a semiconductor memory device, comprising: means for shifting a pumping input signal swinging at a level of an external power supply voltage and an internal ground voltage to a level of an external power supply voltage and an external ground voltage; An inverter circuit connected between an external power supply voltage and an external ground voltage and having an input terminal connected to an output terminal of the level shift means, a pumping capacitor connected between an output terminal and an output node of the inverter circuit, and between the external power voltage and an output node. A boosted voltage generation circuit of a semiconductor memory device, characterized in that it comprises a transistor of diode connection connected to. 제10항에 있어서, 상기 레벨쉬프트수단이, 상기 내부전원전압으로 풀업하는 트랜지스터와 상기 내부접지전압으로 풀다운하는 트랜지스터가 직렬연결되는 입력단과, 상기 내부전원전압으로 풀업하는 트랜지스터와 상기 외부접지전압으로 풀다운 하는 트랜지스터가 직렬연결되며, 상기 풀다운 트랜지스터의 드레인전극이 출력노드가 되는 출력단으로구성되며, 상기 입력단의 풀업트랜지스터의 게이트전극이 입력신호에 연결되고 상기 출력단의 풀업트랜지스터의 게이트전극이 반전된 입력신호에 연결되며, 상기 풀다운트랜지스터들의 게이트전극이 각각 상대 풀다운 트랜지스터의 드레인전극에 연결되는 것을 특징으로 하는 반도체 메모리장치의 승전압발생회로.11. The method of claim 10, wherein the level shifting means comprises: an input terminal to which a transistor pulled up to the internal power supply voltage and a transistor pulled down to the internal ground voltage are connected in series, a transistor pulled up to the internal power supply voltage and the external ground voltage; The pull-down transistor is connected in series, and the drain electrode of the pull-down transistor is configured as an output node. The input electrode of the pull-up transistor of the input terminal is connected to an input signal and the gate electrode of the pull-up transistor of the output terminal is inverted. And a gate electrode of each of the pull-down transistors is connected to a drain electrode of a relative pull-down transistor. 제11항에 있어서, 상기 제4전압레벨이 0V이고 ,상기 제3전압레벨이 1V이며, 상기 제2전압레벨이 2.5V이고, 상기 제1전압레벨이 3.5V인 것을 특징으로 하는 반도체 메모리장치의 승압전압발생회로.The semiconductor memory device of claim 11, wherein the fourth voltage level is 0V, the third voltage level is 1V, the second voltage level is 2.5V, and the first voltage level is 3.5V. Step-up voltage generator circuit. 제1전압레벨의 외부전원전압을 입력하는 수단과, 제2전압레벨의 내부전원전압을 발생하는 수단과, 제3전압레벨의 내부접지전압을 발생하는 수단과, 제4전압레벨의 외부접지전압을 입력하는 수단을 구비하는 반도체 메모리장치의 메모리셀에 있어서, 비트라인과 스토리지노드 사이에 연결되며 게이트전극이 워드라인에 연결되는 메모리셀 트랜지스터와, 상기 스토리지노드와 기판전압 사이에 연결되는 메모리셀 캐패시터로 구성되며, 상기 기판전압이 상기 비트라인의프리차지전압과 동일한 전압레벨을 가지며, 상기 프리차지전압이 상기 내부전원전압과 내부접지전압의 중간전압레벨인 것을 특징으로 하는 반도체 메모리장치의 메모리셀.Means for inputting an external power supply voltage at a first voltage level, means for generating an internal power supply voltage at a second voltage level, means for generating an internal ground voltage at a third voltage level, and external ground voltage at a fourth voltage level. A memory cell of a semiconductor memory device having a means for inputting a memory cell, comprising: a memory cell transistor connected between a bit line and a storage node and a gate electrode connected to a word line, and a memory cell connected between the storage node and a substrate voltage Wherein the substrate voltage has the same voltage level as the precharge voltage of the bit line, and the precharge voltage is an intermediate voltage level between the internal power supply voltage and the internal ground voltage. Cell. 제13항에 있어서, 상기 제4전압레벨이 0V이고, 상기 제3전압레벨이 1V이며, 상기 제2전압레벨이 2.5V이고, 상기 제1전압레벨이 3.5V인 것을 특징으로 하는 반도체 메모리장치의 메모리셀.The semiconductor memory device according to claim 13, wherein the fourth voltage level is 0V, the third voltage level is 1V, the second voltage level is 2.5V, and the first voltage level is 3.5V. Memory cell. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950015221A 1995-06-09 1995-06-09 Semiconductor memory apparatus Expired - Fee Related KR0142972B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950015221A KR0142972B1 (en) 1995-06-09 1995-06-09 Semiconductor memory apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950015221A KR0142972B1 (en) 1995-06-09 1995-06-09 Semiconductor memory apparatus

Publications (2)

Publication Number Publication Date
KR970003189A true KR970003189A (en) 1997-01-28
KR0142972B1 KR0142972B1 (en) 1998-08-17

Family

ID=19416771

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950015221A Expired - Fee Related KR0142972B1 (en) 1995-06-09 1995-06-09 Semiconductor memory apparatus

Country Status (1)

Country Link
KR (1) KR0142972B1 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100352767B1 (en) * 2000-07-19 2002-09-16 삼성전자 주식회사 interface circuit for use in high speed semiconductor device and method therefore
KR100365428B1 (en) * 1999-06-30 2002-12-18 주식회사 하이닉스반도체 Data bus line sense amp
KR100798764B1 (en) * 2004-10-30 2008-01-29 주식회사 하이닉스반도체 Semiconductor memory device and internal voltage generation method thereof
KR101013199B1 (en) * 2010-04-02 2011-02-10 선광엘티아이 주식회사 Surge Protector Prevents Internal Thermal Explosion and Prevents Surge Inflow with Low Temperature Soldering

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100365428B1 (en) * 1999-06-30 2002-12-18 주식회사 하이닉스반도체 Data bus line sense amp
KR100352767B1 (en) * 2000-07-19 2002-09-16 삼성전자 주식회사 interface circuit for use in high speed semiconductor device and method therefore
KR100798764B1 (en) * 2004-10-30 2008-01-29 주식회사 하이닉스반도체 Semiconductor memory device and internal voltage generation method thereof
KR101013199B1 (en) * 2010-04-02 2011-02-10 선광엘티아이 주식회사 Surge Protector Prevents Internal Thermal Explosion and Prevents Surge Inflow with Low Temperature Soldering

Also Published As

Publication number Publication date
KR0142972B1 (en) 1998-08-17

Similar Documents

Publication Publication Date Title
US6489796B2 (en) Semiconductor device provided with boost circuit consuming less current
US5267201A (en) High voltage boosted word line supply charge pump regulator for DRAM
KR100298159B1 (en) Charge pump
US20020075706A1 (en) Boosted voltage supply
JP2942202B2 (en) Semiconductor memory device using a plurality of internal power supply voltages
KR970063244A (en) Flexible memory regulator control method for large changes in supply voltage
JP2004005777A5 (en)
KR940010104A (en) Voltage generator and internal step-down converter
JP2007150761A (en) Semiconductor integrated circuit and leakage current reducing method
JP3494488B2 (en) Semiconductor device
JP4413689B2 (en) Semiconductor integrated circuit device having power supply startup sequence
KR970012752A (en) Semiconductor integrated circuit
KR960025732A (en) Semiconductor Memory Devices Reduce Operating Current Consumption
KR960042726A (en) A semiconductor memory device having a boost circuit adapted to an external control signal.
KR970003189A (en) Semiconductor Memory Device with Multiple Ground Power Supplies
KR20010004222A (en) Power supply control device for changing power line connection type corresponding to operation mode in semiconductor memory device
KR970051254A (en) Sense Amplifier Circuit of Semiconductor Memory Device
KR100230372B1 (en) Internal voltage converter for semiconductor memory device
JP3554638B2 (en) Semiconductor circuit
KR960043522A (en) Semiconductor Memory Device Stable to Power Fluctuations
JP2613579B2 (en) Generator circuit in integrated semiconductor circuit
JP3903532B2 (en) Semiconductor memory device
KR200162272Y1 (en) Drive control circuit of memory cell
KR20110047892A (en) Integrated circuits and their driving methods
KR20000051064A (en) Wordline driving circuit for semiconductor memory

Legal Events

Date Code Title Description
A201 Request for examination
PA0109 Patent application

Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 19950609

PA0201 Request for examination

Patent event code: PA02012R01D

Patent event date: 19950609

Comment text: Request for Examination of Application

PG1501 Laying open of application
E701 Decision to grant or registration of patent right
PE0701 Decision of registration

Patent event code: PE07011S01D

Comment text: Decision to Grant Registration

Patent event date: 19980330

GRNT Written decision to grant
PR0701 Registration of establishment

Comment text: Registration of Establishment

Patent event date: 19980406

Patent event code: PR07011E01D

PR1002 Payment of registration fee

Payment date: 19980406

End annual number: 3

Start annual number: 1

PG1601 Publication of registration
PR1001 Payment of annual fee

Payment date: 20010308

Start annual number: 4

End annual number: 4

PR1001 Payment of annual fee

Payment date: 20020318

Start annual number: 5

End annual number: 5

PR1001 Payment of annual fee

Payment date: 20030307

Start annual number: 6

End annual number: 6

PR1001 Payment of annual fee

Payment date: 20040308

Start annual number: 7

End annual number: 7

PR1001 Payment of annual fee

Payment date: 20050310

Start annual number: 8

End annual number: 8

PR1001 Payment of annual fee

Payment date: 20060307

Start annual number: 9

End annual number: 9

PR1001 Payment of annual fee

Payment date: 20070327

Start annual number: 10

End annual number: 10

PR1001 Payment of annual fee

Payment date: 20080401

Start annual number: 11

End annual number: 11

PR1001 Payment of annual fee

Payment date: 20090316

Start annual number: 12

End annual number: 12

FPAY Annual fee payment

Payment date: 20100315

Year of fee payment: 13

PR1001 Payment of annual fee

Payment date: 20100315

Start annual number: 13

End annual number: 13

LAPS Lapse due to unpaid annual fee
PC1903 Unpaid annual fee

Termination category: Default of registration fee

Termination date: 20120309