KR970002187B1 - Register file memory structure with multiple ports - Google Patents

Abstract

None.

Description

Register file memory structure with multiple ports

1 is a schematic block diagram showing a three-port register file memory as an embodiment of the invention.

2 is a block diagram showing a 16x8 register file of the present invention.

3A and 3B are block diagrams showing a three-port file of the present invention.

* Explanation of symbols for main parts of the drawings

110: 3 port file memory 210, 220, 230, 360: 8 bit register

310, 320, 330, 340: register files 410, 420, 430: decoder

The present invention relates to a register file memory structure having a plurality of ports, and in particular, to the operation of other CPUs in address, data and control signal communication between a plurality of CPUs and a single memory. It also relates to a register file memory structure that allows shared memory to be used at a desired time without giving.

Typically, when multiple CPUs share one port of memory, an address buffer and a data buffer are required, and there is a separate conflict to prevent another CPU from using the shared memory while one CPU communicates with the shared memory. Prevention circuitry is required.

When the CPU wishes to use the common memory, the bus request signal (B / R) is output to the outside, and after receiving the bus use permission signal (READY or Acknowledge; / ACK) from the outside, the bus is used. Can communicate with the memory.

In the communication between the CPU and the memory as described above, especially when real time processing is required, such as a digital signal processing apparatus (DSP), since a large amount of time is required for the use of the bus, the efficiency of CPU operation is substantially increased. This decreases.

In addition, as a prior art, a two-port memory typically has a capacity of 1x by 8 bits or more, or a memory required to exchange information between CPUs having a capacity of 4 by 4 bits or less by 16 by 8 bits. If you want to implement two-port memory or three-port memory, the capacity is more than necessary when using 1K × 8 two-port memory, and eight memory is required when using 4 × 4 two-port memory. There were disadvantages such as large area.

Therefore, in the present invention, when a register file memory including a plurality of CPUs and a common memory is to be implemented, address, data, and control signals can be communicated with each other without affecting power loss without any additional buffer. Its purpose is to provide a register file memory structure with multiple ports that improves the efficiency of the CPU.

The above and other objects and advantages of the present invention will be apparent from the preferred embodiments of the present invention with reference to the accompanying drawings.

A register file memory structure having a plurality of ports in accordance with the present invention comprises a register file memory structure having a plurality of ports, comprising: an input for inputting at least two address, data, selection, read and write signals; An output stage for outputting the input data by the received recording signal through the at least two input terminals; And a control signal input terminal for inputting a control signal for an input control clock pulse signal and a data output permission signal to control the input and output of the data.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a schematic block diagram illustrating a three-port register file memory structure in a register file memory structure having a plurality of ports according to the present invention. As shown in FIG. Ports 111-115, 116-120, 121-125, and the register files 310, 320, 330, 340 and decoders 410, 420, 430 shown in FIG. Built-in, reading and writing are possible by three CPUs (first to third CPUs) at the same time.

First, the first ports 111 to 115 communicate with the first CPU, and the signal line 111 represents a line through which address signals 0 to 4 of the first CPU, that is, signals C1AB [0,4] are communicated. The signal communicated through the signal line 111 is a position for reading data in the three-port file memory 110 or a position designation signal for recording and storing data. The input 411 of the decoder 410 of FIG. It designates one of the register files 310, 320, 330, and 340 of FIG. 3A, and simultaneously selects one of 16 8-bit registers in the selected register file.

In addition, the signal line 112 indicates a line through which the data signals 0 through 7 of the first CPU, that is, the C1DB [0.7] signal are communicated, which means that the data to be recorded and stored in the three-port file memory 110 by the first CPU or The data to be read are communicated and are the same signal lines as those of the signal line 311 of FIG. 3A described later.

In addition, the signal line 113 indicates a signal line through which the selection signal of the first CPU, that is, the / C1CS signal is communicated, and a signal of '0' is input when the first CPU writes or reads data into the three-port file memory 110. It is the same signal line as the signal line 412 of FIG. 3B mentioned later.

The signal line 114 is a signal line through which a read signal of the first CPU, that is, a / C1RD signal is communicated, and a signal of '0' is input when the first CPU reads data from the 3-port file memory 110.

Finally, the signal line 115 represents a line through which the recording signal of the first CPU, that is, / C1WR is communicated.

Meanwhile, the signals transmitted through the signal lines 111, 112, 113, 114, and 115 and the operations thereof will be described below.

When the signal / C1CS input to the selection signal line 113 described above is logic '0' and the read signal / C1RD input to the signal line 114 is logic '0', the above-described address signal C1AB [0 4)), the contents (C1DB [0,7]) of the 8-bit register in the register file designated by [0112] are read out and output to the data signal line 112 described above.

When the signal / C1CS input to the selection signal line 113 is logic '0' and the write signal / C1WR input to the signal line 115 is logic '0', the above-described address signal C1AB [0]. (4) stores data C1DB [0,7] received by the data signal line 112 described above.

In addition, the second ports 116 to 120 communicate with the second CPU, and the signal line 116 communicates the address signals (0 to 4) of the second CPU, that is, the signal (C2AB [0,4]). A signal C2AB [0,4], which is communicated through the signal line 116, is a position to read data in the three-port file memory 110 or a position designation signal for recording and storing data. It acts as an input 421 of the decoder 420 of FIG. 3 to designate one of the register files 310 and 320 of FIG. 3A, and simultaneously selects one of the sixteen 8-bit registers in the selected register file.

In addition, the signal line 117 indicates a line through which the data signals (0 to 7) of the second CPU, that is, the (C2DB [0,7]) signal are communicated, which is a three-port file memory 110 by the second CPU. The data to be recorded and stored in the data or the data to be read (C2DB [0,7]) are communicated, which is the same signal line as the signal line 316 of FIG. 3A described later.

In addition, the signal line 118 indicates a signal line through which the selection signal of the second CPU, that is, the / C2CS signal is communicated, and when the second CPU writes or reads data into the three-port file memory 110, a signal of '0' It is input and is the same signal line as the signal line 422 of FIG. 3B mentioned later.

The signal line 119 is a signal line through which the read signal of the second CPU, that is, the / C2RD signal is communicated, and a signal of '0' is input when the second CPU reads data from the 3-port file memory 110. This signal line is the same as the signal line 423 of FIG. 3B.

Finally, the signal line 120 represents a line through which the recording signal of the second CPU, that is, / C2WR is communicated, which is the same signal line as the signal line 424 of FIG. 3B described later.

Meanwhile, the signals transmitted through the signal lines 116, 117, 118, 119, and 120 and the operations thereof will be described below.

When the signal / C2CS input to the selection signal line 117 described above is logic '0' and the read signal / C2RD input to the signal line 118 is logic '0', the aforementioned address signal C2AB [0 4)), the contents (C2DB [0, 7]) of the 8-bit register in the register file designated by [0112] are read out and output to the data signal line 117 described above.

When the signal / C2CS input to the selection signal line 117 is a logic '0' and the write signal / C2WR input to the signal line 120 is a logic '0', the above-described address signal C2AB [0. 4) stores the data C2DB [0,7] received by the data signal line 116 described above in the register file position selected by "

The third ports 121 to 125 are for communicating with the third CPU, and the signal lines 121 are for communicating the address signals 0 to 4 of the third CPU, that is, the lines through which the C3AB [0,4] signals are communicated. The signal communicated via the signal line 121 is a position to read data in the three-port file memory 110 or a position designation signal for recording and storing data. The input 431 of the decoder 430 of FIG. It designates one of the register files 330 and 340 of FIG. 3A, and simultaneously selects one of 16 eight-bit registers in the selected register file.

In addition, the signal line 122 represents a line through which the data signals 0 through 7 of the third CPU, that is, the C3DB [0,7] signal are communicated, which are written to the three-port file memory 110 by the third CPU. The data to be stored or the data to be read are communicated and are the same signal lines as the signal line 319 of FIG. 3A described later.

The signal line 123 indicates a signal line through which the selection signal of the third CPU, that is, the / C3CS signal is communicated, and a signal of '0' when the third CPU writes or reads data into the three-port file memory 110. Is input and is the same signal line as the signal line 432 of FIG. 3B to be described later.

The signal line 124 is a signal line through which the read signal / C3RD of the third CPU is communicated, and a signal of '0' is input when the third CPU reads data from the three-port file memory 110.

Finally, the signal line 125 represents a line through which the recording signal / C3WR of the third CPU is communicated.

Meanwhile, the signals transmitted through the signal lines 121, 122, 123, 124, and 125 and the operations thereof will be described below.

When the signal / C3CS input to the selection signal line 123 described above is logic '0' and the read signal / C3RD input to the signal line 124 is logic '0', the aforementioned address signal C3AB [0 4)), the contents (C3DB [0, 7]) of the 8-bit register in the register file selected by " are read out and output to the data signal line 112 described above.

When the signal / C3CS input to the selection signal line 123 is logic '0' and the write signal / C3WR input to the signal line 125 is logic '0', the above-described address signal C3AB [0 4)) stores the data C3DB [0,7] received by the data signal line 122 described above.

Next, referring to FIG. 2, FIG. 2 is a detailed block diagram of a 16x8 register file according to the present invention. As shown, the 16x8 register file is comprised of sixteen 8-bit registers 210-360. do. Here, the signal line 211 connected to the (DI) terminal of the 8-bit register 210 indicates the data input signal lines 0 to 7 and is connected to the data output (DO) terminal of the 8-bit register 210. The signal line 213 shown represents the data output signals Q0 to 8. Also, signal lines 212, 215, 217, which are input to the clock pulse CP terminals to the 8-bit registers 210, 220, ..., 360. Reference numeral 243 denotes a data input control clock pulse signal of each of the 8-bit registers 210, 220, ..., 360, and the signal line 214, which is input to the terminal 10E of the 8-bit register, 216, 218, ..., 244 denote data output permission signals for each register.

In the 16x8 register file configured in the above-described form, for example, when the clock signal is in a logic '1' state, the contents of the data input signals 0 through 7 are transferred to the 8-bit register 210 through the signal line 211. ), While the data output allowance signal is in the 'low' level, the information (data output signals 0 to 7) stored in the 8-bit register 210 is output through the signal line 213.

Referring to FIG. 3, FIG. 3 illustrates a three-port register file memory structure as a preferred embodiment of the present invention. As shown in FIG. 3A, four 16x8 register files composed of 16 8-bit registers are shown, and in FIG. 3B, three control signal decoders 410 to 430 are shown.

First, in FIG. 3A, each register file 310, 320, 330, 340 has the same structure, and one register file is composed of 16 8-bit registers as shown in FIG. 2.

The signal line 311 represents a signal line through which the data signals 0 to 7, that is, the C1DB (0,7) signals are communicated, and are respectively coupled to the files 1 to 4 (310 to 340), which are shown in FIG. This is the same signal line as the signal line 112.

The signal line 312 indicates a signal line to which an input control clock pulse signal (0 to 15), that is, an input control clock signal (0 to 15 (C1CP [0.15])) signal of the first CPU is input to the register file 310. These are 16 signals among the signals C1CP [0,31] transmitted through the signal line 415 of FIG. 3b, which will be described later. These signals C1CP0 through C1CP15 are the signal lines 212, 215, 217, and 243 shown in FIG. It is provided to the 8-bit register (210, 220, ..., 230, 360) through to serve as the clock pulse signal (CP0 to CP15) of the 8-bit register (210, 220, 230, 360.) In addition, the signal line 313 is provided to the register file 330 1 indicates the signal line to which the input control clock pulse signals 16 to 31 of the CPU, that is, the (C1CP [16,31]) signal are input, and these signals C1CP16 to C1CP31 are also shown in FIG. 212, 215, 217, ..., 243 to 8-bit registers 210, 220, 230, ..., 360 to provide the 8-bit registers 210, 220, 230, ... 360. It serves as a clock pulse signal CP0 to CP15.

On the other hand, the signal lines 314 and 315 are provided in the data output permission signals C1OE [0,15], C1OE [16,31] of the first CPU, that is, the register file 320 and the register file 340. A signal line to which the allowable signals (0 to 15, 16 to 31) for outputting data are transmitted is transmitted, and a signal among the data output allowance signals (C1OE [0,15]) to the first CPU transmitted through the signal line 314. C1OE0 serves as a signal OE0 transmitted through the signal line 214 shown in FIG. 2, and the signal C1OE1 serves as a signal OE1 transmitted through the signal line 216. , Signal C1OE15 serves as signal OE15 transmitted through signal line 244. Also, the output allowance signals C1OE [16,31] of the first CPU transmitted through the signal line 315 are transmitted through the signal line 214 shown in FIG. The signal C1OE17 is transmitted through the signal line 216 shown in FIG. 2 to play the role of the signal OE1, and the signal C1OE31 is the signal line 244 shown in FIG. It is transmitted through the to perform the role of the signal (OE15).

In addition, the signal line 317 represents a signal line to which the data output allowance signal C2CP [0,15] of the second CPU is transmitted. The data output allowance signal of the second CPU is transmitted through the signal line 426 of FIG. 3B. Is the same as Each of these signals C2CP0, C2CP1, C2CP2, and C2CP15 is transmitted to the respective 8-bit registers 210, 220, 230, ..., 360 through the signal lines 214, 216, ..., 244 shown in FIG. , OE1, OE2, ..., OE15).

The signal line 318 is provided with an input control clock pulse signal (0 to 15), that is, an input control clock pulse signal (0 to 15 (C2CP [0, 15])) of the second CPU, to the register file 320. A signal line is shown, which is a signal C2CP [0,16] transmitted through the signal line 425 of FIG. 3b, which will be described later. These signals C2CP0 to (C2CP15) are shown in the signal lines 212, 215, 217, ..., 243 are provided to the 8-bit registers 210, 220, 230, and 360 to serve as clock pulse signals CP0 to CP15 of the 8-bit registers 210, 220, 230, ..., 360.

The signal line 320 transmits the data output allowance signal C3OE [0,15] of the third CPU, that is, the same signal as the signal transmitted through the signal line 436 of FIG. 3B. The signals C3OE0, C3OE1, C3OE2 and C3OE15 are transmitted to respective 8-bit registers 210, 220, 230, ..., 360 through signal lines 214, 216, ..., 244, respectively, and serve as output allowable signals OE0, OE1, ..., OE15.

The signal line 321 transmits the same signal as the signal transmitted through the input control clock pulse signal C3CP [0,15] of the third CPU, that is, the signal line 435 of FIG. 3b. The signals C3CP1, C3CP2, C3CP3, and C3CP15 are transferred to the respective 8-bit registers 210, 220, 230, and 360 through signal lines 212, 215, ..., 243, respectively, and serve as clock pulse signals CP0, CP1, ..., CP15.

The register file 310 is used when the first CPU transmits data to the second CPU, and the register file 320 is used when transferring data from the second CPU to the first CPU. The register file 330 is used when the first CPU transmits data to the third CPU, and the register file 340 is used when transferring data from the third CPU to the first CPU.

In FIG. 3B, the decoder 410 writes an address signal from the first CPU through the signal lines 111 and 411, a selection signal through the signal lines 113 and 412, a read signal through the signal lines 114 and 413, and a read signal transmitted through the signal lines 115 and 414. A signal is input to select one of four register files 310, 320, 330, 340 to which the first CPU writes and stores data, and generates a signal C1CP [0, 31] for selecting sixteen 8-bit registers in the selected register file. And a signal (C1CP) for selecting one of the four register files 310, 320, 330 and 340 of FIG. 3A to which the first CPU reads data and selecting 16 eight-bit registers in the selected register file. [0,31] is generated and transmitted to the signal lines 314 and 315 of FIG. 3a.

The decoder 420 inputs an address signal through the signal lines 116 and 421, a selection signal through the signal lines 118 and 422, a read signal through the signal lines 119 and 423, and a write signal through the signal lines 120 and 424 from the second CPU. The CPU selects one of the two register files 310 and 320 shown in FIG. 3A to store data, and generates a signal C2CP [0,15] for selecting 16 eight-bit registers in the selected register file. A signal (C2OE [0,15]) for selecting one of two register files 310,320 to be transmitted to the signal line 318 and also for the second CPU to read data and selecting sixteen 8-bit registers in the selected register file. Is generated and transmitted to the signal line 317 of FIG. 3a.

The decoder 430 inputs an address signal through the signal lines 121 and 431, a selection signal through the signal lines 123 and 432, a read signal through the signal lines 124 and 433, and a write signal through the signal lines 125 and 434 from the third CPU. The CPU selects one of the two register files 330 and 340 of FIG. 3A to store data, and generates a signal C3CP [0,15] for selecting 16 eight-bit registers in the selected register file. A signal C3CP [0,15 for selecting one of two register files 330, 340 to which data is to be read by the third CPU and for selecting sixteen 8-bit registers in the selected register file. ) Is generated and transmitted to the signal line 320 of FIG. 3a.

On the other hand, the signal line 411 indicates a signal line through which address signals 0 through 4 are input to the decoder 410, and the signal line 412 indicates a signal line through the decoder 410 through which a selection signal is input. In addition, the signal line 413 represents a line through which the read signal is transmitted to the decoder 410, and the signal line 414 represents a signal line through which the recording signal is input to the decoder 410. Signal lines 415 and 416 represent output lines for transmitting a control clock signal and a data output permission signal from decoders 410 to blocks 310 to 340 described above.

In the decoder 410 configured as described above, if the selection signal input through the signal line 412 is in a logic '0' state and the read signal input through the signal line 413 is in a logic '0', the signal line 411 is input to the signal line 411. One of the 32 8-bit registers is selected according to the input address signals (0 to 4), and one of the output permission signals (0 to 31) from the signal line 416 is a logic '0' to control the selected 8-bit register. It is in a state.

On the other hand, the output permission signal (0 to 31) output through the output line 416 is separately connected to the 8-bit register of each of the above-described files (1 to 4), one of the output permission signal (0 to 31) The authorized 8-bit register outputs the stored data information to the signal line 311 of the file 1 310.

In addition, if the selection signal to the signal line 412 is in a logic '0' state and the write signal to the signal line 414 is in a logic '0', one of the 32 8-bit registers according to the address signal to the signal line 411. Is selected, and one of the input control clock pulse signals (0 to 31) output through the signal line 415 becomes a logic '1' state to control the selected 8-bit register. Here, the input control clock pulse signals 0 to 31 are separately connected to respective 8 bit registers, and the 8 bit register 310 to which one of the input control clock pulse signals (0 to 31) is applied is a signal line 311. Data information entered in) is stored.

Further, according to the present invention, each register file is composed of 16 8-bit registers as shown in FIG. 2, and each of the 8-bit registers has eight data input signal lines 211 and eight data output signal lines ( 213), one input control clock pulse signal, and one data output allowable signal are connected.

On the other hand, as described above, in the present invention, since one register is connected and used for each port, even when two CPUs write data to the same address of the memory (WRITE), No crash In other words, data provided from two CPUs can be simultaneously written to the same address of the shared memory.

Therefore, the register file memory structure having a plurality of ports according to the present invention has the advantage of improving the efficiency of the CPU by allowing the common memory to be used at a time that requires no relation to the operation of another CPU. In addition, communication between multiple CPUs and one common memory can be performed by connecting address data and control signals without adding any additional device, thereby minimizing the number of components and the mounting area, as well as the same in two CPUs. Even when data is simultaneously written to an address, there is a big advantage that data can be recorded without data collision.

Claims (4)

A register file memory structure having a plurality of ports, comprising: an input for inputting at least two address, data, select, read and write signals; An output terminal for outputting the input data by the received recording signal through the at least two input terminals; And a control signal input stage for inputting a control signal for an input control clock pulse signal and a data output permission signal to control input and output of the data. The method of claim 1, wherein the input control clock pulse signal and the data output permission signal generation include receiving the at least two address, data, read and write signals to generate corresponding control clock pulse and data output permission signals, respectively. A register file memory structure comprising at least two control signal decoders. 3. The register file memory structure of claim 2, wherein the address, data, and control signals are configured to be separated in operation for each port. 3. The register file memory structure of claim 2, wherein the read and write signals operate separately for each port.