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KR960705354A - Edge connectable metal package - Google Patents

Edge connectable metal package

Info

Publication number
KR960705354A
KR960705354A KR1019960701854A KR19960701854A KR960705354A KR 960705354 A KR960705354 A KR 960705354A KR 1019960701854 A KR1019960701854 A KR 1019960701854A KR 19960701854 A KR19960701854 A KR 19960701854A KR 960705354 A KR960705354 A KR 960705354A
Authority
KR
South Korea
Prior art keywords
package
base component
periphery
component
leadframe
Prior art date
Application number
KR1019960701854A
Other languages
Korean (ko)
Inventor
알 호프만 폴
엠. 포프레웰 제임스
에스. 브라던 제프레이
Original Assignee
폴 와인스타인
오린 코포레이션
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 폴 와인스타인, 오린 코포레이션 filed Critical 폴 와인스타인
Publication of KR960705354A publication Critical patent/KR960705354A/en

Links

Classifications

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

본 발명은 모서리가 연결가능한 전자장치 팩키지(90)에 관한 것이다. 상기 팩키지(90)은 유전층에 의해 적어도 부분적으로 피복된 금속 베이스(92)를 구비한다. 리드프레임 또는 회로궤적 형태를 갖는 상호연결 수단(96)은 내장된 반도체 장치(94)에 전기적으로 상호연결된다. 상기 상호연결 수단(96)의 대향단부는 소켓 또는 외부 리드에 대한 브레이징 상호연결하기 위하여 팩키지 주변으로 연장된다.The present invention relates to an electronic device package (90) capable of connecting corners. The package 90 has a metal base 92 at least partially covered by a dielectric layer. Interconnection means 96 in the form of leadframes or circuit trajectories are electrically interconnected to the embedded semiconductor device 94. The opposite end of the interconnecting means 96 extends around the package for brazing interconnection to a socket or external lead.

Description

모서리가 연결가능한 금속 팩키지(Edge connectable metal package)Edge connectable metal package

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제4도는 중앙에 위치한 다이 부착패드를 부착하는 다중칩 모듈을 도시하는 단면도.4 is a cross-sectional view illustrating a multichip module attaching a die attach pad located in the center.

Claims (13)

하나 이상의 전자장치(94)를 내장하기 위한 팩키지(90)에 있어서, 제1주변을 가진 베이스 구성품(92)과; 상기 제1주변보다 더 작은 크기의 제2주변을 가진 커버 구성품(100) 및; 상기 커버 구성품(100)과 베이스 구성품 사이에 배치된 리드프레임(96)을 포함하고, 상기 리드프레임(96)의 외부 (104)는 제1주변근처에서 종결되는 것을 특징으로 하는 하나 이상의 전자장치를 내장하기 위한 팩키지.A package (90) for embedding one or more electronic devices (94), comprising: a base component (92) having a first periphery; A cover component (100) having a second periphery of a smaller size than the first periphery; At least one electronic device comprising a leadframe 96 disposed between the cover component 100 and the base component, wherein the exterior 104 of the leadframe 96 terminates near a first perimeter. Package to embed. 제1항에 있어서, 상기 베이스 구성품(92)은 금속, 금속합금 및 금속합성물로 구성된 그룹으로부터 선택되는 것을 특징으로 하는 하나 이상의 전자장치를 내장하기 위한 팩키지.2. The package of claim 1 wherein the base component (92) is selected from the group consisting of metals, metal alloys and metal composites. 제2항에 있어서, 상기 베이스 구성품(92)은 알루미늄, 알루미늄 합금 또는 알루미늄 합성물인 것을 특징으로 하는 하나 이상의 전자장치를 내장하기 위한 팩키지.3. The package of claim 2, wherein the base component (92) is aluminum, an aluminum alloy or an aluminum composite. 제2항 또는 제3항에 있어서, 상기 베이스 구성품(92)은 유전층으로 적어도 부분적으로 피복되는 것을 특징으로 하는 하나 이상의 전자장치를 내장하기 위한 팩키지.4. The package of claim 2 or 3, wherein the base component (92) is at least partially covered with a dielectric layer. 제4항에 있어서, 상기 베이스 구성품(92)의 결합두께, 리드프레임(96)의 외부 및 상기 리드프레임(96)에 베이스 구성품(92)을 결합하는 유전성 밀봉체(98)은 외부소켓에 팩키지(90)를 전기적으로 상호연결하는 데에 효과적인 것을 특징으로 하는 하나 이상의 전자장치를 내장하기 위한 팩키지.5. A dielectric seal (98) as claimed in claim 4, wherein the dielectric seal (98) for coupling the thickness of the base component (92) to the outside of the lead frame (96) and the base component (92) to the lead frame (96) is packaged in an external socket. A package for containing one or more electronics, characterized in that it is effective to electrically interconnect 90. 하나 이상의 전자장치(128)를 내장하기 위한 팩키지(120)에 있어서, 유전층(124)에 의해 적어도 부분적으로 피복된 베이스 구성품(122)과; 커버 구성품(136)과; 상기 베이스 구성품(122)과 커버 구성품 (136) 사이에 배치된 리드프레임(132) 및; 상기 유전층(124)에 부착되어 상기 전자장치(128)와 리드프레임(132)에 전기적으로 상호연결되는 하나 이상의 회로궤적(126)을 포함하는 것을 특징으로 하는 하나 이상의 전자장치를 내장하기 위한 팩키지.A package (120) for embedding one or more electronic devices (128), comprising: a base component (122) at least partially covered by a dielectric layer (124); Cover component 136; A leadframe 132 disposed between the base component 122 and the cover component 136; And one or more circuit traces (126) attached to the dielectric layer (124) and electrically interconnected to the electronic device (128) and the leadframe (132). 제6항에 있어서, 상기 베이스(122)는 알루미늄, 알루미늄 합금 또는 알루미늄 합성물이며, 상기 유전층(124)는 양극층인 것을 특징으로 하는 하나 이상의 전자장치를 내장하기 위한 팩키지.7. The package of claim 6, wherein the base (122) is aluminum, an aluminum alloy or an aluminum composite, and the dielectric layer (124) is an anode layer. 제7항에 있어서, 상기 회로궤적(126)은 연소된 금속, 은으로 충진된 중합체 및 도전성 잉크로 구성된 그룹으로부터 선택되는 것을 특징으로 하는 하나 이상의 전자장치를 내장하기 위한 팩키지.8. The package of claim 7, wherein the circuit trace (126) is selected from the group consisting of burned metal, silver filled polymer and conductive ink. 하나 이상의 전자장치(128)를 내장하기 위한 팩키지(120,140)에 있어서, 양극층에 의해 적어도 부분적으로 피복되고 제1주변을 가진 알루미늄합금 베이스 구성품(122)과;제2주변을 가진 커버 구성품(136) 및; 상기 양극층(124)에 부착되고 상기 제1주변에 대하여 연장되는 하나 이상의 회로궤적(126)을 포함하는 것을 특징으로 하는 하나 이상의 전자장치를 내장하기 위한 팩키지.A package (120, 140) for embedding one or more electronic devices (128), comprising: an aluminum alloy base component (122) covered at least in part by an anode layer and having a first periphery; and a cover component (136) having a second periphery; ) And; And one or more circuit traces (126) attached to the anode layer (124) and extending with respect to the first periphery. 제9항에 있어서, 상기 회로궤적(126)은 연소된 금속, 은으로 충진된 중합체 및 도전성 잉크로 구성된 그룹으로부터 선택되는 것을 특징으로 하는 하나 이상의 전자장치를 내장하기 위한 팩키지.10. The package of claim 9, wherein the circuit trace (126) is selected from the group consisting of burned metal, silver filled polymer and conductive ink. 제9항에 있어서, 상기 제1주변은 제2주변보다 더 큰 것을 특징으로 하는 하나 이상의 전자장치를 내장하기 위한 팩키지.10. The package of claim 9, wherein the first peripheral is larger than the second peripheral. 제9항에 있어서, 상기 제1주변은 제2주변과 동일한 것을 특징으로 하는 하나 이상의 전자장치를 내장하기 위한 팩키지.The package of claim 9, wherein the first peripheral portion is the same as the second peripheral portion. 제11항 또는 제12항에 있어서, 리드프레임(144)은 상기 제1주변근처에서 회로궤적(126)의 모서리에 납땜되는 것을 특징으로 하는 하나 이상의 전자장치를 내장하기 위한 팩키지.The package according to claim 11 or 12, wherein the lead frame (144) is soldered to the edge of the circuit trace (126) near the first periphery. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019960701854A 1993-10-12 1994-09-26 Edge connectable metal package KR960705354A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US134,993 1987-12-18
US13499393A 1993-10-12 1993-10-12
PCT/US1994/010388 WO1995010853A1 (en) 1993-10-12 1994-09-26 Edge connectable metal package

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FR2501414A1 (en) * 1981-03-06 1982-09-10 Thomson Csf MICROBOITIER FOR ENCAPSULATION OF SEMICONDUCTOR PELLETS, TESTABLE AFTER WELDING ON A SUBSTRATE
JPS5815241A (en) * 1981-07-20 1983-01-28 Sumitomo Electric Ind Ltd Substrate for semiconductor device
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JPS58190046A (en) * 1982-04-30 1983-11-05 Fujitsu Ltd Semiconductor device
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JPH09503888A (en) 1997-04-15
EP0723703A1 (en) 1996-07-31

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