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KR960704264A - 영역 및 범용 신호 루팅을 갖는 프로그램가능 논리 디바이스(programmable logic device with regional and universal signal routing) - Google Patents

영역 및 범용 신호 루팅을 갖는 프로그램가능 논리 디바이스(programmable logic device with regional and universal signal routing) Download PDF

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KR960704264A
KR960704264A KR1019960700013A KR19960700013A KR960704264A KR 960704264 A KR960704264 A KR 960704264A KR 1019960700013 A KR1019960700013 A KR 1019960700013A KR 19960700013 A KR19960700013 A KR 19960700013A KR 960704264 A KR960704264 A KR 960704264A
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logic
region
logic cell
bus lines
bus
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KR100312801B1 (ko
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제임스 씨. 케이. 홍
웬디 이. 뮐러
죠 유
닐 버거
케이스 에이치. 구저
제프리 에스. 공워
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제이. 마이클 로스
아트멜 코오포레이숀
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H03K19/1735—Controllable logic circuits by wiring, e.g. uncommitted logic arrays
    • H03K19/1736—Controllable logic circuits by wiring, e.g. uncommitted logic arrays in which the wiring can be modified
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H03K19/1737—Controllable logic circuits using multiplexers

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  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
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  • Computational Mathematics (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Logic Circuits (AREA)

Abstract

별도의 논리영역(1l-11N)을 한정하는 그룹으로 배치돈 복수의 논리영역(15l-15N)과, 영역(19l-19N)과 복수 영역(13) 버스 라인과, 2개 이상의 버스 신호를 논리적으로 조합하는 일 없이 즉, 프로덕트텀을 형성하는 일 없이 논리셀(31l-31j)의 입력에 버스 라인(39l-39j와 40l-40L)으로부터의 신호가 향하도록 하는 작용만하는 교점 스위치 매트릭스(37)를 가진 프로그램가능 논리 디바이스, 모든 논리는 그 자신들의 논리셀(31l-31j)에 의해 수행된다. 특히 스위치 매트릭스(37)는 각 버스라인(39l-39j와 40l-40L)이 하나 이상의 논리셀 입력에 접속될 수 있지만 각각의 논리셀 입력은 쇼트되는일 없이 하나의 버스 라인에만 접속될 수 있도록 구성된다. 한 실시예에서 각각의 논리셀(31l-31j)은 하나의 논리신호(41l-41j)를 영역 버스 라인(19l)에 피드백해서 그 영역의 범용 선택 매트릭스(47)를 통해 범요 버스 라인(13)에 다른 논리 신호를 포텐셜하게 피드백할 수 있다. 선택 매트릭스(47)는 범용 버스(13)에 영역의 포텐셜 피드백 신호의 서브세트를 접속한다.

Description

영역 및 범용 신호 루팅을 갖는 프로그램가능 논리 디바이스(PROGRAMMABLE LOGIC DEVICE WITH REGIONAL AND UNIVERSAL SIGNAL ROUTING)
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 울트라 프로그램가능 논리 디바이스(울트라 PLD)의 칩레벨 아키텍쳐를 나타내는 블록도이다,
제2도는 제1도에 나타낸 울트라 PLD 내의 논리 영역중 하나에 대한 상세를 나타내는 블록도이다,
제3a도와 제3b도는 제2도의 논리영역내의 논리셀중 하나에 대한 게이트 레벨 구조를 나타내는 블록도이며,
제3b도는 논리셀의 피드백 선택부로서, 조합 신호라인 E와, 레지스터 출력 Q 및 제3a도의 I/O핀에 접속된다.

Claims (3)

  1. 논리셀 입력을 통해 입력 신호를 수신하며 셀의 별도의 논리 영역을 한정하는 그룹으로 배치된 복수의 논리셀과; 버스 라인내의 신호를 전도하는 복수의 버스라인과; 상기 논리셀 입력에 버스 라인을 프로그램가능하게 접속하기 위한 교점 스위치를 구비하는데, 상기 각 버스 라인은 상기 매트릭스로 된 한세트의 교점 스위치를 통해 적어도 하나의 논리셀 영역의 논리셀 입력에 접속되고, 상기 복수의 버스라인은 복수의 논리영역내의 논리셀 입력에 접속되는 복수 영역 버스 라인이고, 상기 버스 라인중 일부는 단지 하나의 논리 영역에서 논리셀입력에 접속되는 영역 버스 라인이고, 각각의 논리셀은 영역 피드백신호를 상기 영역 버스 라인중 하나에 공급하며; 복수의 피드백 선택 매트릭스를 구비하는 데, 각각의 논리 영역당 하나인 각각의 선택 매트릭스는 그 대응하는 논리 영역의 상기 논리 영역으로부터 포텐셜 복수 영역 피드백신호를 수신하는 입력과 상기 포텐셜 복수 영역 피드백신호의 프로그램가능하게 선택된 서브 세트를 상기 복수 영역 버스 라인에 공급하는 출력을 갖는 것을 특징으로 하는 프로그램가능 논리 디바이스(PLD).
  2. 제1항에 있어서, 적어도 하나의 복수 영역 버스 라인은 논리 영역 마다의 논리셀 입력에 접속하는 범용 버스라인인 것을 특징으로 하는 프로그램가능 논리 디바이스(PLD).
  3. 제1항에 있어서, 각 논리셀은 상기 영역 버스라인중 하나에 제1스위치 출력에서 공급된 영역 피드백 신호로서 상기 프디백신호의 하나를 선택하고 상기 논리셀의 논리 영역에 대응하는 피드백 선택 매트릭스에 제2스위치 출력에서 공급된 포텐셜 복수 영역 피드백 신호로서 상기 피드백신호의 다른 하나를 선택하기 위해 스위치 입력에서 2개의 피드백신호를 수신하는 프로그램가능 스위치 수단을 갖는 것을 특징으로 하는 프로그램가능 논리 디바이스(PLD).
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019960700013A 1994-05-04 1995-05-02 영역및범용신호경로를갖는프로그램가능논리소자 Expired - Fee Related KR100312801B1 (ko)

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US23815694A 1994-05-04 1994-05-04
US238156 1994-05-04
PCT/US1995/005436 WO1995030952A1 (en) 1994-05-04 1995-05-02 Programmable logic device with regional and universal signal routing

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US (1) US5594366A (ko)
EP (1) EP0707721B1 (ko)
JP (1) JP3570724B2 (ko)
KR (1) KR100312801B1 (ko)
CN (1) CN1086815C (ko)
DE (1) DE69525210T2 (ko)
WO (1) WO1995030952A1 (ko)

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CN1128070A (zh) 1996-07-31
WO1995030952A1 (en) 1995-11-16
JPH09500516A (ja) 1997-01-14
KR100312801B1 (ko) 2001-12-28
EP0707721A4 (en) 1998-06-17
EP0707721B1 (en) 2002-01-30
DE69525210T2 (de) 2002-11-28
JP3570724B2 (ja) 2004-09-29
CN1086815C (zh) 2002-06-26
US5594366A (en) 1997-01-14
DE69525210D1 (de) 2002-03-14
EP0707721A1 (en) 1996-04-24

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