[go: up one dir, main page]

KR960038628A - Priority adjuster - Google Patents

Priority adjuster Download PDF

Info

Publication number
KR960038628A
KR960038628A KR1019950008791A KR19950008791A KR960038628A KR 960038628 A KR960038628 A KR 960038628A KR 1019950008791 A KR1019950008791 A KR 1019950008791A KR 19950008791 A KR19950008791 A KR 19950008791A KR 960038628 A KR960038628 A KR 960038628A
Authority
KR
South Korea
Prior art keywords
priority
shift register
heartbeat
station
master station
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
KR1019950008791A
Other languages
Korean (ko)
Other versions
KR0146058B1 (en
Inventor
류형렬
Original Assignee
문정환
엘지반도체 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 문정환, 엘지반도체 주식회사 filed Critical 문정환
Priority to KR1019950008791A priority Critical patent/KR0146058B1/en
Publication of KR960038628A publication Critical patent/KR960038628A/en
Application granted granted Critical
Publication of KR0146058B1 publication Critical patent/KR0146058B1/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
    • G06F13/372—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control using a time-dependent priority, e.g. individually loaded time counters or time slot
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
    • G06F13/376—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control using a contention resolving method, e.g. collision detection, collision avoidance

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Small-Scale Networks (AREA)

Abstract

본 발명의 우선순위조정장치는, 데이타 충돌에 관한 정보로서 전송상태 레지스터의 칼럼 비트를 입력으로 하여 하트비트가 천이할때마다 쉬프트시키기 위한 쉬프트 레지스터와, 하트비트신호에 동기되어 클럭신호를 카운팅하기 위한 슬롯타임 카운터와, 상기 쉬프트 레지스터와 슬롯타임 카운터의 출력을 논리조합하여 그 결과를 마스터 스테이션에 전송함으로써 충돌이 발생한 스테이션에 우선권을 주기 위한 논리회로부를 포함하여 구성되며, 자신의 충돌에 관한 정보를 칼럼라인을 통해 상기 마스터스테이션에 전송하여 우선순위를 받음으로써 재전송으로 인한 전송실패를 보상해줄 수 있으며, 우선순위 조절시간을 단축시킬 수 있을 뿐만 아니라 이와 같이 네트웍의 성능을 향상시킴으로써 신뢰성있는 근거리 통신망을 구현할 수 있는 효과가 있다.The priority adjusting device according to the present invention includes a shift register for shifting each time the heartbeat transitions by inputting a column bit of the transfer status register as information on a data collision, and counting a clock signal in synchronization with the heartbeat signal. And a logic circuit unit for giving priority to the station where a collision occurred by logically combining the outputs of the shift register and the slot time counter and transmitting the result to the master station. By receiving the priority through the column line to the master station to compensate for the transmission failure due to retransmission, it is possible to shorten the priority adjustment time, as well as improve the performance of the network in this way, reliable local area network Has the effect of implementing All.

Description

우선순위 조정장치Priority adjuster

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제3도는 본 발명에 의한 우선순위조정장치의 회로도, 제4도는 본 발명에 의한 전송상태레지스터의 구성도, 제5도는 본 발명에 의한 다수의 스테이션과 호스트간의 연결 블럭도.3 is a circuit diagram of a priority adjusting apparatus according to the present invention, FIG. 4 is a block diagram of a transmission state register according to the present invention, and FIG. 5 is a connection block diagram between a plurality of stations and a host according to the present invention.

Claims (1)

데이타 충돌에 관한 정보로서 전송상태 레지스터의 칼럼 비트를 입력으로 하여 하트비트가 천이할때마다 쉬프트시키기 위한 쉬프트 레지스터와, 하트비트신호에 동기되어 클럭신호를 카운팅하기 위한 슬롯타임 카운터와, 상기 쉬프트 레지스터와 슬롯타임 카운터의 출력을 논리조합하여 그 결과를 마스터 스테이션에 전송함으로써 충돌이 발생한 스테이션에 우선권을 주기 위한 논리회로부를 포함하여 구성된 것을 특징으로 하는 우선순위조정장치A shift register for shifting each time the heartbeat transitions by inputting a column bit of the transfer status register as information on a data collision, a slot time counter for counting a clock signal in synchronization with the heartbeat signal, and the shift register And a logic circuit for logically combining the output of the slot time counter and transmitting the result to the master station to give priority to the station where the collision occurred.
KR1019950008791A 1995-04-14 1995-04-14 Priority Adjuster Expired - Fee Related KR0146058B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950008791A KR0146058B1 (en) 1995-04-14 1995-04-14 Priority Adjuster

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950008791A KR0146058B1 (en) 1995-04-14 1995-04-14 Priority Adjuster

Publications (2)

Publication Number Publication Date
KR960038628A true KR960038628A (en) 1996-11-21
KR0146058B1 KR0146058B1 (en) 1998-09-15

Family

ID=19412193

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950008791A Expired - Fee Related KR0146058B1 (en) 1995-04-14 1995-04-14 Priority Adjuster

Country Status (1)

Country Link
KR (1) KR0146058B1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102010022B1 (en) 2017-06-30 2019-08-12 이길헌 Emergency Rescue System for the Elderly Living Alone using Wearable Device and Mobile Device
KR102032427B1 (en) 2019-03-25 2019-10-15 차진호 A system that automatically sends rescue requests in the event of an accident or a crime

Also Published As

Publication number Publication date
KR0146058B1 (en) 1998-09-15

Similar Documents

Publication Publication Date Title
US3519750A (en) Synchronous digital multiplex communication system including switchover
US3906484A (en) Decoder input circuit for receiving asynchronous data bit streams
KR940000981A (en) Computer system, system expansion unit, bus combiner and bus access control method
KR940002717A (en) Serial interface module and method
US3688036A (en) Binary data transmission system and clocking means therefor
GB1357028A (en) Data exchanges system
US5854816A (en) Loop back device of packet communication T1 network
CA2330012A1 (en) Hub port without jitter transfer
KR960038628A (en) Priority adjuster
JPH04137935A (en) Device and method for clock generation and data transmission-reception
CA1279729C (en) Method and apparatus for transferring data between two data processing equipments each driven by an independent clock
KR0158902B1 (en) Device and method for transmitting / receiving serial data between master / slave board
KR102415074B1 (en) Delay circuit, controller for asynchronous pipeline, method of controlling the same, and circuit having the same
JP2655460B2 (en) Clock switching method
KR960020147A (en) Bus Arbitration Control Device in Serial Bus Network
KR100210780B1 (en) Data matching circuit of time slot switch between processor and device
JPH02262739A (en) Method of transmitting information through bidirectional link, and device to implement this method
KR920003696A (en) Data transmission device of multi system
KR950023107A (en) Bus occupancy arbitration device on public bus
KR100222041B1 (en) Signal processing apparatus
JP2538682B2 (en) Reference clock source automatic switching method
JPS6055755A (en) Loop transmitter
KR930004419B1 (en) Synthetic Clock Generation Circuit
GB2299918A (en) Serial link for synchronous and asynchronous transmission
JPH0223104B2 (en)

Legal Events

Date Code Title Description
A201 Request for examination
PA0109 Patent application

St.27 status event code: A-0-1-A10-A12-nap-PA0109

PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

R17-X000 Change to representative recorded

St.27 status event code: A-3-3-R10-R17-oth-X000

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U11-oth-PR1002

Fee payment year number: 1

PG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-PG1601

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R13-asn-PN2301

St.27 status event code: A-5-5-R10-R11-asn-PN2301

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 4

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 5

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 6

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 7

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R11-asn-PN2301

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R14-asn-PN2301

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R11-asn-PN2301

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R14-asn-PN2301

FPAY Annual fee payment

Payment date: 20050422

Year of fee payment: 8

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 8

LAPS Lapse due to unpaid annual fee
PC1903 Unpaid annual fee

St.27 status event code: A-4-4-U10-U13-oth-PC1903

Not in force date: 20060509

Payment event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

PC1903 Unpaid annual fee

St.27 status event code: N-4-6-H10-H13-oth-PC1903

Ip right cessation event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

Not in force date: 20060509

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000