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KR960036564A - Ccd 카메라의 디펙트 보상회로 - Google Patents

Ccd 카메라의 디펙트 보상회로 Download PDF

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Publication number
KR960036564A
KR960036564A KR1019950007046A KR19950007046A KR960036564A KR 960036564 A KR960036564 A KR 960036564A KR 1019950007046 A KR1019950007046 A KR 1019950007046A KR 19950007046 A KR19950007046 A KR 19950007046A KR 960036564 A KR960036564 A KR 960036564A
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KR
South Korea
Prior art keywords
signal
delay
bit
comparison
control
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Application number
KR1019950007046A
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English (en)
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KR0181286B1 (ko
Inventor
김성훈
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950007046A priority Critical patent/KR0181286B1/ko
Priority to JP8066650A priority patent/JPH08275032A/ja
Priority to US08/623,145 priority patent/US5920344A/en
Publication of KR960036564A publication Critical patent/KR960036564A/ko
Application granted granted Critical
Publication of KR0181286B1 publication Critical patent/KR0181286B1/ko

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/38—Transmitter circuitry for the transmission of television signals according to analogue transmission standards
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
    • H04N25/68—Noise processing, e.g. detecting, correcting, reducing or removing noise applied to defects
    • H04N25/683—Noise processing, e.g. detecting, correcting, reducing or removing noise applied to defects by defect estimation performed on the scene signal, e.g. real time or on the fly detection
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/14—Picture signal circuitry for video frequency region
    • H04N5/21—Circuitry for suppressing or minimising disturbance, e.g. moiré or halo

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)
  • Picture Signal Circuits (AREA)

Abstract

본 발명은 디지탈 시그널 프로세스(Digital Signal Process)를 사용하는 카메라 시스템에서 CCD 카메라의 닥크 디펙트(Dark Defect)를 보상해 주도록 하는 CCD 카메라의 디펙트 보상회로에 관한 것으로, 본 발명은 픽셀입력신호를 비트 단위로 지연시키는 지연 수단과, 입력신호와 1비트 지연된 신호를 감산시키는 감산수단과, 감산결과를 일정레벨과 비교하여 일정레벨 이상일 경우 콘트롤 신호를 출력시키는 비교수단과, 비교수단에 일정레벨의 비교값을 인가시키는 콘트롤 수단과, 비교수단의 콘트롤 신호에 의해 스위칭되고 1비트 지연신호 또는 2 비트지연 신호를 선택하여 출력시키는 스위칭 수단을 구비시킴으로써 카메라의 화질을 개선 시키게 된다.

Description

CCD 카메라의 디펙트 보상회로
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 실시회로도, 제2도는 본 발명의 일시시예 회로도, 제3도는 본 발명의 또다른 실시예 회로도.

Claims (4)

  1. 픽셀입력신호를 비트 단위로 지연시키는 지연 수단과, 입력신호와 지연수단에서 1비트 지연된 신호를 감산시키는 감산수단과, 감산수단의 감산결과를 일정레벨과 비교하여 일정레벨 이상일 경우 콘트롤 신호를 출력시키는 비교수단과, 비교수단에 일정레벨의 비교값을 인가시키는 콘트롤 수단과, 비교수단의 콘트롤 신호에 의해 스위칭되고 1비트 지연신호 또는 2비트지연신호를 선택하여 출력시키는 스위칭 수단을 구비하여 이루어지는 것을 특징으로 되는 CCD 카메라의 디펙트 보상회로.
  2. 픽셀 입력신호를 1비트 지연시키는 지연수단과, 입력신호와 지연수단에서 1 비트지연된 신호를 감산시키는 감산수단과, 감산수단의 감산결과를 일정레벨과 비교하여 일정레벨이상일 경우 콘트롤 신호를 출력시키는 비교 수단과, 비교수단에 일정레벨의 비교값을 인가시키는 콘트롤 수단과, 비교수단의 콘트롤 신호에 의해 스위칭되는 스위칭 소자와, 콘트롤 신호의 콘트롤에 의해 2가지 게인값을 저장하는 저장 수단과, 스위칭 소자에 의해 선택된 게인을 승산하는 승산수단을 구비하여 이루어지는 것을 특징으로 하는 CCD카메라의 디펙트 보상회로.
  3. 제1항에 있어서, 스위칭 수단에 인가되는 1 비트지연신호와 2 비트 지연 신호 및 콘트롤 신호 입력 라인에는 지연시간을 보상하는 지연보상수단을 구비시킨 것을 특징으로 하는 CCD 카메라의 디펙트 보상회로.
  4. 제2항에 있어서, 지연수단과 비교수단의 출력측에는 지연시간을 보상하는 지연 보상 수단을 구비시킨 것을 특징으로 하는 CCD카메라의 디펙트 보상회로.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950007046A 1995-03-28 1995-03-28 Ccd 카메라의 디펙트 보상회로 KR0181286B1 (ko)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1019950007046A KR0181286B1 (ko) 1995-03-28 1995-03-28 Ccd 카메라의 디펙트 보상회로
JP8066650A JPH08275032A (ja) 1995-03-28 1996-03-22 Ｃｃｄカメラの欠陥補償装置
US08/623,145 US5920344A (en) 1995-03-28 1996-03-28 CCD camera defective pixel compensation using stored gain values

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950007046A KR0181286B1 (ko) 1995-03-28 1995-03-28 Ccd 카메라의 디펙트 보상회로

Publications (2)

Publication Number Publication Date
KR960036564A true KR960036564A (ko) 1996-10-28
KR0181286B1 KR0181286B1 (ko) 1999-05-01

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US (1) US5920344A (ko)
JP (1) JPH08275032A (ko)
KR (1) KR0181286B1 (ko)

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US6985180B2 (en) * 2001-06-19 2006-01-10 Ess Technology, Inc. Intelligent blemish control algorithm and apparatus
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US4473845A (en) * 1983-01-24 1984-09-25 Eastman Kodak Company Method and apparatus for processing signals from a solid-state image sensor
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Also Published As

Publication number Publication date
KR0181286B1 (ko) 1999-05-01
US5920344A (en) 1999-07-06
JPH08275032A (ja) 1996-10-18

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