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KR960036023A - Semiconductor device manufacturing method - Google Patents

Semiconductor device manufacturing method Download PDF

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Publication number
KR960036023A
KR960036023A KR1019950006824A KR19950006824A KR960036023A KR 960036023 A KR960036023 A KR 960036023A KR 1019950006824 A KR1019950006824 A KR 1019950006824A KR 19950006824 A KR19950006824 A KR 19950006824A KR 960036023 A KR960036023 A KR 960036023A
Authority
KR
South Korea
Prior art keywords
poly1
forming
semiconductor device
poly
source
Prior art date
Application number
KR1019950006824A
Other languages
Korean (ko)
Inventor
조주환
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019950006824A priority Critical patent/KR960036023A/en
Publication of KR960036023A publication Critical patent/KR960036023A/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/811—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using FETs as protective elements

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

본 발명은 반도체소자 제조방법에 관한 것으로, 반도체기판 상부에 폴리1인 게이트전극을 형성하고 상기 폴리1과 폴리1 사이에 소오스/드레인영역을 형성한 다음, 상기 소오스/드레인영역에 접속되는 폴리2를 형성하되 상기 폴리1과 일정거리를 유지하는 중첩도를 유지하고 상기 폴리2 상부에 상기 폴리2와 같은 중첩도로 제1금속층을 형성함으로써 ESD 능력을 향상시켜 반도체소자의 특성 및 신뢰성을 향상시킬 수 있는 기술이다.The present invention relates to a method of manufacturing a semiconductor device, comprising: forming a gate electrode of poly1 on a semiconductor substrate, forming a source / drain region between the poly1 and poly1, and then connecting the poly2 to the source / drain region By forming a but maintaining the overlap with the poly1 to maintain a certain distance and by forming the first metal layer with the same overlap as the poly2 on the poly2 to improve the ESD capability to improve the characteristics and reliability of the semiconductor device It is a skill.

Description

반도체 소자 제조방법Semiconductor device manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명의 실시예에 따른 반도체소자 제조방법 도시한 단면도, 제3도는 중첩도 조정에 따른 온도특성을 도시한 그래프도.2 is a cross-sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention, and FIG. 3 is a graph showing temperature characteristics according to overlapping degree adjustment.

Claims (3)

ESD 능력을 향상시키기 위한 반도체소자 제조방법에 있어서, 반도체기판의 활성영역에 폴리1을 형성하는 공정과, 상기 폴리1과 폴리1 사이에 소오스/드레인영역을 형성하는 공정과, 상기 소오스/드레인 영역에 접속되는 폴리2를 형성하되, 상기 폴리1과 일정거리의 중첩도를 유지하는 공정을 포함하는 반도체소자 제조방법.A method of manufacturing a semiconductor device for improving ESD capability, the method comprising: forming a poly1 in an active region of a semiconductor substrate, forming a source / drain region between the poly1 and the poly1, and the source / drain region A method of manufacturing a semiconductor device, the method comprising: forming a poly 2 connected to the poly 2 and maintaining a degree of overlap of the poly 1 with a predetermined distance. 제1항에 있어서, 상기 폴리1 및 폴리2는 다결정실리콘으로 형성되는 것을 특징으로 하는 반도체소자 제조방법.The method of claim 1, wherein the poly 1 and poly 2 are formed of polycrystalline silicon. 제1항에 있어서, 상기 일정거리는 0.5 내지 1.0㎛인 것을 특징으로 하는 반도체소자 제조방법.The method of claim 1, wherein the predetermined distance is 0.5 to 1.0 μm. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950006824A 1995-03-29 1995-03-29 Semiconductor device manufacturing method KR960036023A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950006824A KR960036023A (en) 1995-03-29 1995-03-29 Semiconductor device manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950006824A KR960036023A (en) 1995-03-29 1995-03-29 Semiconductor device manufacturing method

Publications (1)

Publication Number Publication Date
KR960036023A true KR960036023A (en) 1996-10-28

Family

ID=66553130

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950006824A KR960036023A (en) 1995-03-29 1995-03-29 Semiconductor device manufacturing method

Country Status (1)

Country Link
KR (1) KR960036023A (en)

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Legal Events

Date Code Title Description
PA0109 Patent application

Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 19950329

PG1501 Laying open of application
PC1203 Withdrawal of no request for examination
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid