KR960027808A - ATM cell multiplexer - Google Patents

Abstract

The present invention stores ATM cells in a buffer in a B-ISDN, which can accommodate a variety of services while providing vast bandwidth, extracts buffer level information, and gives priority to signal and maintenance cells. The present invention relates to an ATM cell multiplexer that multiplexes at high speed, and is an ATM cell multiplexer that can be commonly used in ATM terminal devices, network access nodes, and B-NT systems in a B-ISDN environment. In addition to multiplexing based on cell priority, minimizing losses, the multiplexer first inserts a port identifier into each cell that is truncated at each input port to provide a multiplexer that can distinguish cells transmitted from different ports. There is.

Description

ATM cell multiplexer

Since this is an open matter, no full text was included.

1 is an ATM cell multiplexer block diagram.

Claims (6)

Input cell receiving means (11) for receiving cells from a plurality of input ports, storing the cells in a buffer and extracting flags; Processor interface means 12 for constructing a cell from the processor data transferred from the microprocessor, storing the cell in a buffer, extracting a cell interrupt, configuring a control and a state register, and reporting and controlling the state of the multiplexer to the microprocessor; Internal clock generating means (13) for generating a cell clock and a design number clock to synchronize the multiplexer on a cell-by-cell basis; Scheduling control means (14) for receiving a flag extracted by the input cell receiving means (11) and a cell interrupt extracted by the processor interface means (12) and outputting a predetermined buffer selection signal for determining a cell transmission order; And cell output control means (15) for supplying a buffer read signal to the buffer to read a cell stored in the buffer and inserting a port identifier corresponding to the separator of each input port in the cell header upon receiving the buffer selection signal. ATM cell multiplexer, characterized in that. The input cell receiving logic (21) of claim 1, wherein the input cell receiving unit (11) generates a counter increment signal after receiving a signal for receiving cell input data from each input port and one cell. A buffer write controller 22 for controlling the writing of the buffers; A cell counter (24) for counting the number of cells stored in the buffer (23) by receiving the counter increment output from the input cell receiving logic (21) and the buffer selection signal output from the scheduling control means (14); And a cell number comparator (25) for receiving the number of cells from said cell counter (24) and extracting flags. 2. The processor as claimed in claim 1, wherein said processor interface means (12) comprises: an address decoder (31) for making a register selector and a buffer selector for selecting each register using an 8-bit address and a chip selector transferred from a microprocessor; Using the register selector received from the address decoder 31 as each register selection signal, processor data is input to the corresponding register, and then each component of the multiplexer is controlled, and a full flag FF from the input cell receiving means 11 is obtained. A state and control register (32) for receiving a value indicating whether the buffer 23 is full or not as a register value; And a signal and a maintenance cell arrive after a random (53 bytes) byte is input while storing processor data from the buffer selector output from the address decoder 31 in the buffer 23 through the cell interrupter. ATM cell multiplexer, characterized in that it comprises a buffer control logic (33) to inform the tumbling control means (14). 2. The internal clock generating means (13) according to claim 1, further comprising: a counter (41) for continuously countering 53 in synchronization with a system clock; A cell count signal generator 42 for generating a cell count clock that is held high every 30th clock from the counter output of the counter 41; And a cell output synchronous signal generator (43) for generating a cell clock held high every 53th clock. 2. The scheduling control means (14) according to claim 1, wherein the scheduling control means (14) takes the cell interrupt transmitted from the processor interface means (12) and the n AFFs and NEFs transmitted from the input cell receiver (11) as inputs. A priority comparator 51 for outputting a predetermined (n + 1) cell selection signal according to the ranking; And a cell selection and feedback logic (52) for outputting a buffer selection signal asserted for 53 bytes from the cell selection signal of the priority comparator (51). The buffer read controller (61) according to claim 1, wherein said cell output control means (15) outputs a buffer read signal for one buffer (23) enabled from predetermined (n + 1) buffer selection signals. ); And inserting a port identifier into the buffer output data and the processor output data output by the buffer read signal of the buffer read controller 61, and inserting a port identifier into the output port together with a control signal (byte clock, cell enable, cell sink) for 53 bytes of cells. And a port identifier insertion logic (62) for transmitting output data. ※ Note: The disclosure is based on the initial application.