[go: up one dir, main page]

KR960026597A - Device Separation Method of Semiconductor Device - Google Patents

Device Separation Method of Semiconductor Device Download PDF

Info

Publication number
KR960026597A
KR960026597A KR1019940039098A KR19940039098A KR960026597A KR 960026597 A KR960026597 A KR 960026597A KR 1019940039098 A KR1019940039098 A KR 1019940039098A KR 19940039098 A KR19940039098 A KR 19940039098A KR 960026597 A KR960026597 A KR 960026597A
Authority
KR
South Korea
Prior art keywords
oxide film
thermal oxide
trench
forming
silicon substrate
Prior art date
Application number
KR1019940039098A
Other languages
Korean (ko)
Other versions
KR0179555B1 (en
Inventor
박상훈
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019940039098A priority Critical patent/KR0179555B1/en
Publication of KR960026597A publication Critical patent/KR960026597A/en
Application granted granted Critical
Publication of KR0179555B1 publication Critical patent/KR0179555B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76294—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using selective deposition of single crystal silicon, i.e. SEG techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)

Abstract

본 발명은 반도체 장치의 소자 분리방법에 관한 것으로, 특히 소자분리영역을 최소화 하여 활성영역을 충분히 확보할 수 있는 소자 분리방법으로, 이와 같은 본 발명은 실리콘 기판상에 제1열산화막과 질화막을 증착한 다음 소정의 트렌치를 형성하여 소자 분리 영역을 구축하는 단계, 상기 소자 분리 영역의 트렌치에 제2열산화막을 형성하는 단계, 상기 제2열산화막을 비등성 식각하여 트렌치 저면의 실리콘 기판을 노출시키는 단계, 상기 노출된 실리콘 기판을 성장시켜 트렌치에 단결정 에피택셜 실리콘층을 형성하는 단계, 및 상기 제1열산화막과 질화막을 제거하여 소정의 필드 산화막을 형성하는 단계로 이루어진다.The present invention relates to a device isolation method of a semiconductor device, and more particularly, to a device isolation method capable of sufficiently securing an active region by minimizing device isolation regions. The present invention is to deposit a first thermal oxide film and a nitride film on a silicon substrate. Forming a device isolation region by forming a predetermined trench; forming a second thermal oxide film in the trench of the device isolation region; Forming a single crystal epitaxial silicon layer in the trench by growing the exposed silicon substrate; and forming a predetermined field oxide layer by removing the first thermal oxide layer and the nitride layer.

Description

반도체 장치의 소자 분리방법Device Separation Method of Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도의 (가)(나)(다)(라)(마)는 본 발명의 소자 분리방법을 설명하기 위한 공정 수순도.(A) (b) (c) (d) (e) of FIG.

Claims (12)

실리콘 기판상에 제1열산화막과 질화막을 증착한 다음 소정의 트렌치를 형성하여 소자 분리 영역을 구축하는 단계, 상기 소자 분리 영역의 트렌치에 제2열산화막을 형성하는 단계, 상기 제2열산화막을 비등성 식각하여 트렌치 저면의 실리콘 기판을 노출시키는 단계, 상기 노출된 실리콘 기판을 성장시켜 트렌치에 단결정 에피택셜 실리콘층을 형성하는 단계, 및 상기 제1열산화막과 질화막을 제거하여 소정의 필드 산화막을 형성하는 단계로 이루어지는 반도체 장치의 소자 분리방법.Forming a device isolation region by depositing a first thermal oxide film and a nitride film on a silicon substrate, forming a predetermined trench, forming a second thermal oxide film in the trench of the device isolation region, and forming the second thermal oxide film. Exposing the silicon substrate on the bottom of the trench by boiling etching, growing the exposed silicon substrate to form a single crystal epitaxial silicon layer in the trench, and removing the first thermal oxide film and the nitride film to form a predetermined field oxide film. A device separation method of a semiconductor device comprising the step of forming. 제1항에 있어서, 상기 제1열산화막은 100~300Å의 두께로 형성하는 것을 특징으로 하는 반도체 장치의 소자 분리방법.The method of claim 1, wherein the first thermal oxide film is formed to a thickness of 100 to 300 kPa. 제1항 또는 제2항에 있어서, 상기 질화막은 1000~2000Å의 두께로 형성하는 것을 특징으로 하는 반도체 장치의 소자 분리방법.The device isolation method according to claim 1 or 2, wherein the nitride film is formed to a thickness of 1000 to 2000 GPa. 제1항 또는 제2항에 있어서, 상기 트렌치의 깊이는 0.3~1.2㎛로 형성하는 것을 특징으로 하는 반도체 장치의 소자 분리방법.The method of claim 1, wherein the trench has a depth of about 0.3 μm to about 1.2 μm. 제4항에 있어서, 상기 트렌치는 사진 식각법으로 형성하는 것을 특징으로 하는 반도체 장치의 소자 분리방법.The method of claim 4, wherein the trench is formed by a photolithography method. 제1항 또는 제2항에 있어서, 상기 제2열산화막은 3000~8000Å의 두께로 형성하는 것을 특징으로 하는 반도체 장치의 소자 분리방법.The device isolation method according to claim 1 or 2, wherein the second thermal oxide film is formed to a thickness of 3000 to 8000 kPa. 제6항에 있어서, 제2열산화막의 증착시 요홈부가 형성되도록 진행하는 것을 특징으로 하는 반도체 장치의 소자 분리방법.The method of claim 6, wherein the recess is formed to form a recess when the second thermal oxide film is deposited. 제1항 또는 제2항에 있어서, 트렌치 저면의 실리콘 기판을 노출시키기 위한 제2열산화막의 식각시 반응가스로 CF4, CHF3또는 Ar에 의한 가스를 사용하는 것을 특징으로 하는 반도체 장치의 소자 분리방법.3. The device of claim 1, wherein a gas of CF 4 , CHF 3, or Ar is used as a reaction gas during etching of the second thermal oxide film for exposing the silicon substrate on the bottom surface of the trench. Separation Method. 제1항 또는 제2항에 있어서, 상기 단결정 에피택셜 실리콘층은 제1열산화막을 장벽으로 제1열산화막까지 성장시켜 형성하는 것을 특징으로 하는 반도체 장치의 소자 분리방법.The method of claim 1, wherein the single crystal epitaxial silicon layer is formed by growing a first thermal oxide film as a barrier to the first thermal oxide film. 제1항 또는 제2항에 있어서, 제1열산화막과 질화막의 제거는 습식 식각법에 의하는 것을 특징으로 하는 반도체 장치의 소자 분리방법.The method of claim 1 or 2, wherein the removal of the first thermal oxide film and the nitride film is performed by a wet etching method. 제10항에 있어서, 제1열산화막의 식각액으로 인산용액을, 질화막의 식각액으로는 불화수소용액을 사용하는 것을 특징으로 하는 반도체 장치의 소자 분리방법.The method of claim 10, wherein a phosphoric acid solution is used as an etchant of the first thermal oxide film and a hydrogen fluoride solution is used as an etchant of the nitride film. 제1항 또는 제2항에 있어서, 필드 산화막이 실리콘 기판의 표면으로 노출되는 부위보다 실리콘 기판의 내부에 매장된 부위가 더 크게 형성되는 것을 특징으로 하는 반도체 장치의 소자 분리방법.The method of claim 1 or 2, wherein a portion buried in the silicon substrate is formed larger than a portion where the field oxide film is exposed to the surface of the silicon substrate. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940039098A 1994-12-30 1994-12-30 Isolation method of semiconductor device KR0179555B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940039098A KR0179555B1 (en) 1994-12-30 1994-12-30 Isolation method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940039098A KR0179555B1 (en) 1994-12-30 1994-12-30 Isolation method of semiconductor device

Publications (2)

Publication Number Publication Date
KR960026597A true KR960026597A (en) 1996-07-22
KR0179555B1 KR0179555B1 (en) 1999-04-15

Family

ID=19405279

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940039098A KR0179555B1 (en) 1994-12-30 1994-12-30 Isolation method of semiconductor device

Country Status (1)

Country Link
KR (1) KR0179555B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100672760B1 (en) * 2000-08-18 2007-01-22 주식회사 하이닉스반도체 Trench isolation film formation method for semiconductor devices

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100639198B1 (en) * 2000-06-01 2006-10-31 주식회사 하이닉스반도체 Method of forming device isolation film in semiconductor device
KR100842487B1 (en) * 2005-12-28 2008-07-01 동부일렉트로닉스 주식회사 Device Separator Formation Method of Semiconductor Device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100672760B1 (en) * 2000-08-18 2007-01-22 주식회사 하이닉스반도체 Trench isolation film formation method for semiconductor devices

Also Published As

Publication number Publication date
KR0179555B1 (en) 1999-04-15

Similar Documents

Publication Publication Date Title
JPS6340337A (en) Method of isolating integrated circuit
KR960043106A (en) Method of forming insulating film in semiconductor device
KR970060447A (en) Isolation method of semiconductor device
KR870004523A (en) Method of forming dielectric embedded device isolation groove in semiconductor device
KR880014691A (en) Manufacturing Method of Semiconductor Device
US6194286B1 (en) Method of etching thermally grown oxide substantially selectively relative to deposited oxide
US5061653A (en) Trench isolation process
KR960026597A (en) Device Separation Method of Semiconductor Device
KR100209714B1 (en) Isolation film of semiconductor device and method for forming the same
JP3680521B2 (en) Manufacturing method of semiconductor device
KR960026585A (en) Method for manufacturing device isolation oxide film of semiconductor device
KR960026608A (en) Field oxide film formation method of semiconductor device
JP2786259B2 (en) Method for manufacturing semiconductor device
KR960026729A (en) Device Separating Method of Semiconductor Device
KR980006083A (en) Method for forming an element isolation film of a semiconductor element
KR950029849A (en) Device Separator Formation Method
KR960026727A (en) Manufacturing method of high frequency semiconductor device
KR970053437A (en) Device isolation film formation method using trench
KR960026595A (en) Device Separation Method of Semiconductor Device
KR100396792B1 (en) Method for chemical mechanical polishing isolation region of semiconductor device
KR960026592A (en) Device Separation Method of Semiconductor Device
KR970054111A (en) Manufacturing method of semiconductor device
JPH0258848A (en) Manufacture of semiconductor device
KR920007149A (en) How to remove bird beak shape in semiconductor device manufacturing process
KR970003800A (en) Device Separating Method of Semiconductor Device

Legal Events

Date Code Title Description
PA0109 Patent application

Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 19941230

A201 Request for examination
PA0201 Request for examination

Patent event code: PA02012R01D

Patent event date: 19950426

Comment text: Request for Examination of Application

Patent event code: PA02011R01I

Patent event date: 19941230

Comment text: Patent Application

PG1501 Laying open of application
E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

Comment text: Notification of reason for refusal

Patent event date: 19980528

Patent event code: PE09021S01D

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

Patent event code: PE07011S01D

Comment text: Decision to Grant Registration

Patent event date: 19980828

GRNT Written decision to grant
PR0701 Registration of establishment

Comment text: Registration of Establishment

Patent event date: 19981127

Patent event code: PR07011E01D

PR1002 Payment of registration fee

Payment date: 19981127

End annual number: 3

Start annual number: 1

PG1601 Publication of registration
PR1001 Payment of annual fee

Payment date: 20011017

Start annual number: 4

End annual number: 4

PR1001 Payment of annual fee

Payment date: 20021018

Start annual number: 5

End annual number: 5

PR1001 Payment of annual fee

Payment date: 20031017

Start annual number: 6

End annual number: 6

PR1001 Payment of annual fee

Payment date: 20041116

Start annual number: 7

End annual number: 7

PR1001 Payment of annual fee

Payment date: 20051021

Start annual number: 8

End annual number: 8

PR1001 Payment of annual fee

Payment date: 20061024

Start annual number: 9

End annual number: 9

PR1001 Payment of annual fee

Payment date: 20071018

Start annual number: 10

End annual number: 10

PR1001 Payment of annual fee

Payment date: 20081017

Start annual number: 11

End annual number: 11

PR1001 Payment of annual fee

Payment date: 20091016

Start annual number: 12

End annual number: 12

PR1001 Payment of annual fee

Payment date: 20101019

Start annual number: 13

End annual number: 13

PR1001 Payment of annual fee

Payment date: 20111024

Start annual number: 14

End annual number: 14

FPAY Annual fee payment

Payment date: 20121022

Year of fee payment: 15

PR1001 Payment of annual fee

Payment date: 20121022

Start annual number: 15

End annual number: 15

FPAY Annual fee payment

Payment date: 20131017

Year of fee payment: 16

PR1001 Payment of annual fee

Payment date: 20131017

Start annual number: 16

End annual number: 16

PC1801 Expiration of term

Termination date: 20150629

Termination category: Expiration of duration