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KR960026152A - Method of Forming Flattened Metal Wiring of Semiconductor Device - Google Patents

Method of Forming Flattened Metal Wiring of Semiconductor Device Download PDF

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Publication number
KR960026152A
KR960026152A KR1019940032591A KR19940032591A KR960026152A KR 960026152 A KR960026152 A KR 960026152A KR 1019940032591 A KR1019940032591 A KR 1019940032591A KR 19940032591 A KR19940032591 A KR 19940032591A KR 960026152 A KR960026152 A KR 960026152A
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South Korea
Prior art keywords
metal layer
deposition
forming
temperature metal
layer
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KR1019940032591A
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KR0151229B1 (en
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김헌도
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김주용
현대전자산업 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846—Layer combinations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76847—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned within the main fill metal

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체 소자의 제조 공정중 반도체 기판 또는 제1전도층에 절연층을 증착하고 예정된 부위에 콘택홀을 형성한 다음 확산 방지층과 열처리 공정을 수행하는 단계와, 평탄화를 위한 제2전도층, 저온 금속층 증착 및 고온 금속층 증착을 진공파괴없이 순차적으로 진행하는 평탄화된 금속 배선 형성 방법에 있어서, 상기 고온 금속층 증착은 콜리메이터를 이용하지 않고 수행하는 것을 특징으로 하여, 층덮힘을 개선하고, 전체 공정 속도를 증가시키며, 이에 따라 공정 비용을 최소화함과 동시에 고단차 콘택에서도 알루미늄 합금의 평탄화를 이룰 수 있는 등의 효과가 있는 반도체 소자의 평탄화된 금속 배선 형성 방법에 관한 것이다.The present invention is a step of depositing an insulating layer on a semiconductor substrate or a first conductive layer during the manufacturing process of a semiconductor device, forming a contact hole in a predetermined portion, and then performing a heat treatment process with a diffusion barrier layer, a second conductive layer for planarization, In the method of forming a planarized metal line, wherein the low temperature metal layer deposition and the high temperature metal layer deposition are sequentially performed without vacuum destruction, the high temperature metal layer deposition is performed without using a collimator, thereby improving layer covering and increasing the overall process speed. The present invention relates to a method of forming a planarized metal wiring of a semiconductor device having an effect such as minimizing a process cost and achieving planarization of an aluminum alloy even at a high step contact.

Description

반도체 소자의 평탄화된 금속 배선 형성 방법Method of Forming Flattened Metal Wiring of Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도 내지 제6도는 본 발명에 따른 평탄화된 금속 배선 공정 단계를 나타낸 단면도.1 through 6 are cross-sectional views illustrating the planarized metallization process steps according to the present invention.

Claims (8)

반도체 소자의 제조 공정중 반도체 기판 또는 제1전도층에 절연층을 증착하고 예정된 부위에 콘택 홀을 형성한 다음 확산 방지층과 열처리 공정을 수행하는 단계와, 평탄화를 위한 제2전도층, 저온 금속층 증착 및 고온 금속층 증착을 진공파괴없이 순차적으로 진행하는 평탄화된 금속 배선 형성 방법에 있어서, 상기 저온 금속층 증착은 콜리메이터를 이용하여 수행하고, 상기 고온 금속층 증착은 콜리메이터를 이용하지 않고 수행하는 것을 특징으로 하는 반도체 소자의 평탄화된 금속 배선 형성 방법.Depositing an insulating layer on a semiconductor substrate or a first conductive layer during the fabrication process of the semiconductor device, forming a contact hole in a predetermined site, performing a heat treatment process with a diffusion barrier layer, and depositing a second conductive layer and a low temperature metal layer for planarization And forming a planarized metal line by sequentially performing high temperature metal layer deposition without vacuum destruction, wherein the low temperature metal layer deposition is performed using a collimator, and the high temperature metal layer deposition is performed without using a collimator. A method of forming planarized metal wiring of a device. 제1항에 있어서, 상기 제2전도층과 확산 방지 금속층은, 그 일부를 콜리메이터 공정을 이용하여 증착하는 것을 특징으로 하는 반도체 소자의 평탄화된 금속 배선 형성 방법.The method of claim 1, wherein a portion of the second conductive layer and the diffusion preventing metal layer is deposited by using a collimator process. 제1항에 있어서, 상기 저온 금속층 증착은, 100℃이하의 어느 한 온도에서 수행하는 것을 특징으로 하는 반도체 소자의 평탄화된 금속 배선 형성 방법.The method of claim 1, wherein the low-temperature metal layer deposition is performed at a temperature of about 100 ° C. or less. 제1항에 있어서, 상기 고온 금속층 증착은, 450 내지 600℃의 온도에서 콜리메이터 없이 수행하는 것을 특징으로 하는 반도체 소자의 평탄화된 금속 배선 형성 방법.The method of claim 1, wherein the deposition of the high temperature metal layer is performed without a collimator at a temperature of 450 to 600 ° C. 7. 제4항에 있어서, 상기 증착은, 웨이퍼를 소정 시간동안 가열한 후 수행하는 것을 특징으로 하는 반도체 소자의 평탄화된 금속 배선 형성 방법.The method of claim 4, wherein the deposition is performed after heating the wafer for a predetermined time. 제5항에 있어서, 상기 웨이퍼 가열은, 60 내지 180초 동안 수행하는 것을 특징으로 하는 반도체 소자의 평탄화된 금속 배선 형성 방법.The method of claim 5, wherein the wafer heating is performed for 60 to 180 seconds. 제1항에 있어서, 상기 고온 금속층 상부에, 반사 방지층을 진공 파괴없이 증착하는 것을 특징으로 하는 반도체 소자의 평탄화된 금속 배선 형성 방법.The method of claim 1, wherein an anti-reflection layer is deposited on the high-temperature metal layer without vacuum destruction. 제4항 또는 제7항에 있어서, 상기 증착공정시 공정 압력은, 2.0mTorr 이하 중 어느 한 값으로 유지하는 것을 특징으로 하는 반도체 소자의 평탄화된 금속 배선 형성 방법.The method of claim 4 or 7, wherein the process pressure during the deposition process is maintained at any one of 2.0 mTorr or less. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940032591A 1994-12-02 1994-12-02 Method of forming flat metal wire in semiconductor device Expired - Fee Related KR0151229B1 (en)

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Application Number Priority Date Filing Date Title
KR1019940032591A KR0151229B1 (en) 1994-12-02 1994-12-02 Method of forming flat metal wire in semiconductor device

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Application Number Priority Date Filing Date Title
KR1019940032591A KR0151229B1 (en) 1994-12-02 1994-12-02 Method of forming flat metal wire in semiconductor device

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KR960026152A true KR960026152A (en) 1996-07-22
KR0151229B1 KR0151229B1 (en) 1998-12-01

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100244432B1 (en) * 1996-11-19 2000-03-02 김영환 A method for forming aluminum layer in semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100244432B1 (en) * 1996-11-19 2000-03-02 김영환 A method for forming aluminum layer in semiconductor device

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Publication number Publication date
KR0151229B1 (en) 1998-12-01

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