KR960015589B1 - Multi-processor communication system and its data communication method - Google Patents

Abstract

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Description

Multiprocessor Communication System and Its Data Communication Method

1 is a block diagram of a conventional multiprocessor communication system.

2 is a block diagram of the central control module shown in FIG.

3 is a block diagram of ancillary modules shown in FIG.

4 is a block diagram of a multiprocessor communication system according to the present invention.

5 is a block diagram of the central control module shown in FIG.

6 is a block diagram of ancillary modules shown in FIG.

7 is a block diagram of the data input / output control unit shown in FIGS. 5 and 6;

* Designation of symbols for the main parts of the drawing

40: central control module 50a ~ 50n: secondary module

A-N: local processor 60, 70: data input / output controller

61, 71: CPU 62, 72: Memory

The present invention relates to a multiprocessor communication system. In particular, the present invention relates to a system for preventing communication interruption of a whole system even when some data transmission / reception paths fail and at the same time improving circuit density and recovering errors during data transmission. A multiprocessor communication system and its data communication invention.

In general, a system such as an electronic switchboard is provided with a plurality of processors, and the processors perform functions assigned to themselves while transmitting and receiving data with each other.

As described above, a conventional multiprocessor communication system in which a plurality of processors transmit and receive data to and from each other is shown. As can be seen in FIG. 1, the central control module 10 is connected with a plurality of subsidiary modules 20a-20n via a parallel bus (PB), and a plurality of local processors for each subsidiary module 20a-20n. (local processor) is connected, and a plurality of local processors A1 to An are connected to the subsidiary module 20a, and a plurality of local processors B1 to Bn are connected to the subsidiary module 20b. ) Are connected to a plurality of local processors (N1-Nn). For example, when the local processor A1 transmits data to the local processor Nn, the local processor A1 transmits the data to be transmitted to the submodule 20a, and the submodule 20a transmits the data to the local processor A1. The data received from) is transmitted to the central control module 10 through the parallel bus (PB). The central control module 10 divides the data received through the parallel bus BP from the secondary module 20a and transmits the data to the secondary module 20n via the parallel bus PB, and the secondary module 20n controls the central control. The data received from the module 10 is transmitted to the local processor Nn side. In addition, when the local processor Nn transmits data to the local processor A side, it is transmitted in the reverse order described above, and is transmitted to the local processor A1 side via the local processor 20a.

The central control module 10 and the subsidiary modules 20a to 20n shown in FIG. 1 have the same structure. The central control module 10 is configured as shown in FIG. 2 and the subsidiary modules 20a to 20n have the same structure. It is comprised as FIG. As can be seen in FIG. 2, the central control module 10 is connected to the buffers 30 and 32, the latch 31, the memory 33, the CPU 34, and the timing controller 35. The buffer 30 outputs the data received from the subsidiary modules 20a to 20n to the latch 31 side, and the latch 31 is supplied from the buffer 30 in accordance with a control signal supplied from the timing controller 35. Data is output to the memory 33 side, and the memory 33 stores data supplied from the latch 31 in accordance with a control signal from the timing controller 35. At this time, when the interrupt signal INT is supplied to the CPU 34, the CPU 34 reads and analyzes the data stored in the memory 33 and outputs it to the memory 33 side. The memory 33 is a timing controller. The data supplied from the CPU 34 side is output to the buffer 32 side in accordance with the control signal from the 35, and the buffer 32 is output from the memory 33 in accordance with the control signal from the timing controller 35. The supplied data is output to the subsidiary modules 20a to 20n.

As can be seen in FIG. 3, each of the subsidiary modules 20a-20n is connected to the buffer 40, 42, the latch 41, the memory 43, the CPU 44, and the timing controller 45. The buffer 40 outputs data received from the central control module 10 to the latch 41 side, and the latch 41 receives data supplied from the buffer 40 in accordance with a control signal supplied from the timing controller 45. Output to the memory 43 side, the memory 43 stores the data supplied from the latch 41 in accordance with the control signal from the timing controller 45. At this time, when the interrupt signal INT is supplied to the CPU 44, the CPU 44 reads and analyzes the data stored in the memory 43 and outputs the data to the memory 43 side. The memory 43 is a timing controller. The data supplied from the CPU 44 side is output to the buffer 42 in accordance with the control signal from the 45. The buffer 42 is supplied from the memory 43 according to the control signal from the timing controller 45. Output data to the central control module 10 side.

As described above, in the conventional multiprocessor communication system, since the central control module 10 and the plurality of subsidiary modules 20a to 20n are physically connected through one parallel bus PB, they are provided in the parallel bus PB. If a fault occurs on any one line, the entire system is interrupted in communication. The circuit configuration of the central control module 10 and the subsidiary modules 20a to 20n is complicated and the circuit density is lowered. There was a problem that the performance of the entire system is reduced because there is no ability to recover from the error.

The present invention has been made in view of the above-described problems, and even if a failure occurs in some lines connected between the central control module and the plurality of submodules, the central control module and the plurality of submodules do not affect the entire system. It is an object of the present invention to provide a multiprocessor communication system and a data communication method thereof in which a circuit is simply configured to increase circuit density and recover an error when an error occurs during communication.

In order to achieve the above object, the present invention provides a data communication method of a multiprocessor communication system having a plurality of submodules in a central control module and a plurality of local processors connected to each of the plurality of submodules. Each of the accessory modules is connected to the central control module through independent serial communication lines, and the accessory module and the central control module convert the serial data supplied from the serial communication line into parallel to receive the received data after dividing them in units of frames. And store the stored data in the memory means in order, read the data stored in the memory means, transmit the data in frame units, convert the data transmitted in the frame units into serial data, and output the data to the serial communication line. It provides a data communication method of a communication system.

The present invention also provides a multiprocessor communication system including a plurality of submodules connected to a central control module and a plurality of local processors connected to each of the plurality of submodules, wherein the central control module is configured to transmit and receive data. CPU 61 for managing, a data input / output control unit 60 for outputting data received from the submodule to the CPU 61, and outputting data supplied from the CPU 61 to the submodule; A memory (62) for storing data read from and applied to the data input / output control section (60) and outputting the stored data to the data input / output control section (60) through the CPU (61); Each of the plurality of subsidiary modules outputs the data received from the CPU 71 and the central control module to the CPU 71 and manages the data supplied from the CPU 71. A data input / output control unit 70 which outputs to the module side, and stores data which is read and applied from the data input / output control unit 70 by the CPU 71 and stores stored data through the CPU 71 through the data input / output control unit ( A memory 72 for outputting to the 70) side; The central control module and the plurality of subsidiary modules provide a multiprocessor communication system, each of which transmits and receives data through an independent serial communication line.

By such a method and configuration, the present invention can easily configure the circuits of the central control module and the auxiliary module without affecting the entire system even if a failure occurs in some lines connected between the central control module and the plurality of accessory modules. This can increase circuit density and recover from errors in the event of a communication.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4 is a block diagram of a multiprocessor communication system according to the present invention, FIG. 5 is a block diagram of a central control module shown in FIG. 4, FIG. 6 is a block of ancillary modules shown in FIG. 4, and FIG. Fig. 5 is a block diagram of the data input / output control unit shown in Figs. As shown in FIG. 4, the multiprocessor data communication system according to the present invention comprises a central control module 40, a plurality of submodules 50a to 50n, and a plurality of local processors A to N. As shown in FIG. A plurality of subsidiary modules 50a to 50n are connected to the central control module 40. The plurality of subsidiary modules 50a to 50n are connected to the central control module 40 through independent serial communication lines, respectively. A plurality of local processors A1 to An are connected to each other, and a plurality of local processors B1 to Bn are connected to the auxiliary module 50b, and a plurality of processors N1 to Nn are connected to the auxiliary module 50n. do. For example, when the local processor A2 wants to transmit data to the local processor N1, the local processor A2 transmits the data to be transmitted to the submodule 50a, and the submodule 50a transmits the local processor. The data received from (A2) is transmitted to the central control module 40 through the serial communication line. The central control module 40 analyzes the data received from the secondary module 50a and transmits the data to the secondary module 50n. The secondary module 50n transmits the data received from the central control module 40 to the local processor N1. To the side. In addition, when the local processor N1 transmits data to the local processor A2, the data is transmitted in the reverse order as described above. The data transmitted by the local processor N1 is the copy module 50n, the central control module 40, and the copy. It is transmitted to the local processor A2 side via the module 50a.

Each of the central control module 40 and the subsidiary modules 50a to 50n shown in FIG. 4 has the same structure. The central control module 40 is configured as shown in FIG. 5 and the subsidiary modules 50a to 50n. ) Is configured as shown in FIG. As can be seen in FIG. 5, the central control module 40 is connected to the data input / output controller 60, the CPU 61, and the memory 62. The data input / output control unit 60 stores the data received from the submodules 50a to 50n in a first-in first-out (FIFO) (shown in FIG. 7) provided therein, and the data is stored to some extent in the FIFO. When stored, the interrupt signal INT is output to the CPU 61 side. When the interrupt signal INT is supplied from the data input / output control unit 60, the CPU 61 reads data from the FIFO in the data input / output control unit 60 when it is confirmed that the data is completely stored in the FIFO. At this time, the CPU 61 stores data read from the FIFO using a direct memory access (DMA) at a predetermined address of the memory 62. After that, when the data input / output control unit 60 requests the data output to the CPU 61 side, the CPU 61 reads out the data stored in the predetermined address of the memory 62 and stores it in the FIFO of the data input / output control unit 60. Accordingly, the data input / output control unit 60 outputs the stored data to the subsidiary module 50a-50n when the data is stored to some extent in the FIFO.

As can be seen in FIG. 6, each of the subsidiary modules 50a to 50n is connected to the data input / output control unit 70, the CPU 71, and the memory 72. As shown in FIG. The data input / output control unit 70 stores the data received from the central control module 40 in a first-in first-out (FIFO) provided in its interior and stores the data in the FIFO to some extent. If so, the interrupt signal INT is output to the CPU 71 side. The CPU 71 reads data from the FIFO in the data input / output control unit 70 when the interrupt INT is supplied from the data input / output control unit 70 and confirms that the state of the FIFO is completely stored in the FIFO. At this time, the CPU 71 stores the data read from the FIFO using a direct memory access (DMA) at a predetermined address of the memory 72. After that, when the data input / output control unit 70 requests the data output to the CPU 71 side, the CPU 71 reads out the data stored at the predetermined address of the memory 72 and stores it in the FIFO of the data input / output control unit 70. Accordingly, the data input / output controller 70 outputs the stored data to the central control module 40 when the data is stored in the FIFO to some extent.

As shown in FIG. 7, the data input / output control units 60 and 70 of FIGS. 5 and 6 include a plurality of high level data link controls of the serial interface unit 80 and the plurality of collision control units 81a to 81n; A plurality of FIFOs 83a to 83n and a microcontroller interface unit 84 of 82a to 82n are connected to each other, and the data input / output control units 60 and 70 are made of a single integrated circuit. The serial interface unit 80 converts a plurality of serial data SDRa to SDRn inputted from the outside in parallel, outputs them to the collision control units 81a to 81n, and serially outputs parallel data supplied from the collision control units 81a to 81n. Outputs the converted serial data (SDXa to SDXn) externally. The collision controllers 81a to 81n are configured to separately input data clocks (DCL), frame synchronization signals (FSC), and microcontroller interface unit (84) and data supplied from the serial interface unit (80) and HDLC (82a). The control is performed so that there is no collision between the data supplied from -82n, and the HDLCs 82a-82n control the collision control units 81a-81n and the FIFOs 83a-83n according to control signals supplied from the collision control units 81a-81n. By transmitting and receiving the data input and output between each frame unit to prevent the error of the data transmitted and received. The FIFOs 83a to 83n sequentially store data supplied from the HDLCs 82a to 82n, output the data to the microcontroller interface unit 84, and sequentially store the data supplied from the microcontroller interface 84. Scramble to HDLC 82a-82n side.

The microcontroller interface unit 84 includes an address signal AD, a read control signal RD, a write control signal WR, a chip select signal CS, and an address latch enable signal supplied from the CPUs 61 and 71. Outputs the data DA stored in the FIFOs 83a-83n to the CPY 61, 71 side according to the (ALE) and the reset signal RES, or the CPU 61, 71 reads from the memory 62, 72 and outputs it. One data DA is output to the FIFOs 83a to 83n, and an interrupt signal INT for informing that the data is stored in the FIFOs 83a to 83n is output to the CPUs 61 and 71.

As described above, in the data communication method of the multiprocessor communication system according to the present invention, since the data transmission and reception between the central control module 40 and each of the subsidiary modules 50a-50n is performed through an independent serial communication line, some serial communication lines are used. Even if a failure occurs, the entire system is not caused to interrupt the communication, and the data input / output controllers 60 and 70 of FIG. 7 are manufactured as a single integrated circuit. The central control module 40 and each submodule 50a to Since 50n) can be configured with a simpler circuit than before, the circuit density can be improved, and the HDLC 82a-82n is provided inside the data input / output control unit 60.70 to recover the error in data transfer. The physical structure of data transmission and data reception is equally improved.

Claims (3)

In a data communication method of a multiprocessor communication system having a plurality of submodules connected to a central control module and a plurality of local processors connected to each of the plurality of submodules, the plurality of submodules are independent serial communication lines. The sub-module and the central control module convert the serial data supplied from the serial communication line in parallel, divide the data into frame units and receive the data in the memory means in order. And reading the data stored in the memory means and transmitting the data in the frame unit, and converting the data transmitted in the frame unit to the serial communication line and outputting the data to the serial communication line. In a multiprocessor communication system having a plurality of submodules connected to a central control module and a plurality of local processors connected to each of the plurality of submodules, the central control module includes a CPU 61 for managing data transmitted and received. ) And a data input / output controller 60 for outputting data received from the submodule to the CPU 61 and outputting data supplied from the CPU 61 to the submodule. A memory (62) for storing data read from and applied to the data input / output control unit (60) and outputting the stored data to the data input / output control unit (60) through the CPU (61); Each of the plurality of subsidiary modules outputs the data received from the CPU 71 and the central control module to the CPU 71 and manages the data supplied from the CPU 71. A data input / output control unit 70 which outputs to the module side, and stores data which is read and applied from the data input / output control unit 70 by the CPU 71 and stores stored data through the CPU 71 through the data input / output control unit ( And a central memory module (70) for outputting to the 70) side, wherein the plurality of submodules transmit and receive data through independent serial communication lines. 3. The data input / output control unit (60, 70) converts serial data supplied through a serial communication line in parallel to receive and transmits parallel data to be transmitted in serial to output through the serial communication line. A plurality of collision controllers 81a-81n for controlling a collision between the serial interface unit 80, data supplied from the serial interface unit 80, and data output to the serial interface unit 80 side; A plurality of HDLCs 82a to 82n for receiving data supplied from the controllers 81a to 81n in frame units and for dividing and outputting data transmitted to the collision control units 81a to 81n in frame units; Matching the 61 and 71, the micro controller interface unit 84 for inputting and outputting data to and from the CPU 61 and 71, and the data supplied from the HDLCs 82a to 82n in this order. And store the data supplied to the CPUs 61 and 71 through the microcontroller interface unit 84 and sequentially store the data supplied from the CPUs 61 and 71 through the microcontroller interface unit 84 before the HDLC. A plurality of FIFOs (83a to 83n) output to the (82a to 82n) side, characterized in that the multiprocessor communication system.