KR960011864B1 - Method for manufacturing conductive wiring of semiconductor device - Google Patents

Abstract

None.

Description

Method for manufacturing conductive wiring of semiconductor device

1 is a layout diagram of a DRAM cell.

2A through 2G are cross-sectional views taken along the line I-I of FIG. 1, in which a bit line of a DRAM cell is manufactured according to an embodiment of the present invention.

3A to 3D are sectional views taken along the line II-II of FIG. 1, in which a bit line of a DRAM cell is manufactured according to an embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

1 Substrate 2 Device Separation Oxide

4 word line 5 oxide spacer

6: mask oxide film 7: first insulating layer

8: conductive layer 8A: bit line

9 second insulating layer 10 tungsten film

20, 30: photoresist pattern 40: active region

50: word line 60: bit line

70: bit line contact hole

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a conductive wiring of a highly integrated semiconductor device. In particular, a method of forming a pattern of conductive wiring by selectively depositing a tungsten film on a portion where a conductive wiring is to be formed and using the tungsten film as a mask is used for DRAM, SRAM and ASIC It is a technology that can be used for conductive wiring such as (Application Specified IC.).

Although not shown, a method of manufacturing a conductive wiring by the prior art will be described by applying it to a bit line of a DRAM cell.

One embodiment of the bit line method used in a conventional DRAM cell is to form a device isolation oxide film and a gate oxide film on a silicon substrate, form a plurality of word lines, and then form an interlayer insulating film on the entire surface of the structure. Are stacked to form bit line contact holes.

Then, a conductive layer was deposited on top of the entire structure, and a bit line having a conductive layer pattern was formed by masking.

In this case, there is a problem in that the bit line is difficult to form because a topology difference occurs in the bit line according to the topology of the word line, so that part of the pattern is lost.

Another embodiment of the related art to solve this problem is to form a planarized interlayer insulating film evenly on the entire surface of the word line formed structure, and remove a portion of the insulating layer to form a bit line contact hole, The conductive layer was deposited, and a bit line having a conductive layer pattern was formed by masking.

However, this method has solved the problem due to the topology, but the problem that the contact resistance is increased due to the high aspect ratio of the bit line contact hole is caused.

Accordingly, in order to solve the above problems, the present invention forms a word line and an interlayer insulating film, and then forms a bit line contact hole by a self-aligned contact method without performing a planarization process, and forms a bit on the entire surface of the structure. A line conductive layer is deposited, and an insulating film pattern is formed in the conductive layer to expose a predetermined portion as a bit line, and selective tungsten is deposited on the exposed conductive layer. It is an object of the present invention to provide a method for manufacturing a conductive wiring of a semiconductor device, by removing a lower conductive layer, suppressing an increase in topology, a simple process, and improving reliability of device operation.

A method of manufacturing a conductive wiring of a semiconductor device according to the present invention includes the steps of forming a conductive layer on top of a first insulating layer formed on a semiconductor substrate, and forming a planarizing second insulating layer on the conductive layer. Forming a second insulating layer pattern exposing the conductive layer by removing the planarizing second insulating layer on the portion of the conductive layer, which is intended for conductive wiring, and being exposed by the second insulating layer pattern. Selectively depositing a tungsten film to a predetermined thickness on the conductive layer, removing the second insulating layer pattern, and etching the exposed conductive layer by using the tungsten film as a mask. It includes a step of forming a conductive wiring consisting of.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a layout diagram of a DRAM cell, a series of word lines 50 extending in one direction with a rectangular active region 40 and a series of bit lines 60 and bit lines extending in another direction. The position where the contact 70 is arranged is shown.

2A through 2G and 3A through 3D show the steps of manufacturing a bit line of a DRAM cell according to an embodiment of the present invention, along the lines I-I and II-II in FIG. 1, respectively. As sectional drawing, it demonstrates in association with each other.

2A shows a series of word lines 4 including a device oxide oxide film 2 and a gate oxide film 3 formed over the semiconductor substrate 1, the mask oxide film 6, and an oxide film spacer 5. It is sectional drawing of the state in which MOSFET formed with / drain (not shown) is formed, and the 1st insulating layer 7 was formed in the upper part of the whole structure.

2B is a cross-sectional view of the photosensitive film pattern 20 for the bit line contact hole mask formed on the first insulating layer 7.

2C illustrates a bit line contact hole 70 exposing the semiconductor substrate 1 by etching the exposed first insulating layer 7 by using the photoresist pattern 20 as a mask, and the photoresist pattern 20 Is a cross-sectional view of the state removed.

2d and 3a show a bit line conductive layer 8, for example, made of polycrystalline silicon on the entire surface of the structure, followed by a planarizing second insulating layer 9 thereon. Deposition of Bo Phosphor Silicate Glass (hereinafter referred to as BPSG) or Phosphor Silicate Glass (hereinafter referred to as PSG) and a predetermined bit line region on the second insulating layer 9. It is sectional drawing of the state which formed the photosensitive film pattern 30 for bit line masks exposed.

2E and 3B form a second insulating layer 9 pattern for etching the second insulating layer 9 exposed by the second photoresist pattern 30 to expose the bit line conductive layer 8. Next, the cross-sectional view of the photosensitive film pattern 30 is removed.

2F and 3C are cross-sectional views of a state in which a tungsten film 10 is selectively deposited to a predetermined thickness on the bit line conductive layer 8 exposed by the second insulating layer 9 pattern.

2G and 3D show the remaining planarization of the second insulating layer 9 pattern by using a blanket etch method and exposing the exposed bit line using the deposited tungsten film 10 as a mask. The layer 8 is etched and the bit line 8A which consists of the pattern of the conductive layer 8 in which the tungsten film 10 was laminated | stacked on it is formed, and it is sectional drawing.

According to the present invention, it is possible to reduce the topology when forming a conductive line, for example, a bit line contacted to a substrate, and to easily form a photoresist pattern even when the topology difference is severe.

Claims (4)

A method for manufacturing a conductive wiring of a semiconductor device, the method comprising: forming a conductive layer on an upper portion of a first insulating layer formed on a semiconductor substrate; forming a second insulating layer for planarization on the conductive layer; Forming a second insulating layer pattern exposing the conductive layer by removing the planarizing second insulating layer on the portion of the layer scheduled for conductive wiring; and selectively on the conductive layer exposed by the second insulating layer pattern A conductive wiring comprising a process of depositing a tungsten film to a predetermined thickness, a process of removing the second insulating layer pattern, and a conductive layer pattern having a tungsten film deposited thereon by etching the exposed conductive layer using the tungsten film as a mask. A conductive wiring manufacturing method for a semiconductor device comprising the step of forming a. The method of claim 1, wherein the conductive wiring is a bit line. The method of claim 1, wherein a contact hole connected to the lower conductive layer is formed in a predetermined portion before forming the conductive layer. The method of claim 1, wherein a word line is formed under the first insulating layer.