KR960011558B1 - Bit line selection signal driving method - Google Patents

Abstract

None.

Description

Bit line selection signal driving method

1 is a block diagram showing an example of a bidirectional sense amplifier structure.

2 is a waveform diagram showing an operation example of a conventional bit line selection circuit.

FIG. 3 is a schematic block diagram showing a double shared sense amplifier structure in which four bit line pairs are connected to one sense amplifier. FIG.

4 is a circuit diagram of a bit line selection signal generation circuit.

5 is a circuit diagram of a bit line selection signal generator.

6 is a circuit diagram of a first embodiment of the bit line selection signal generation circuit of the present invention.

7 is a circuit diagram of a second embodiment of the bit line selection signal generation circuit of the present invention.

8 is a waveform diagram showing an example of the proposed bit line selection method.

9 is a waveform diagram of a bit line selection signal showing an example of the bit line selection method of the present invention.

10 is a waveform diagram for explaining the effects of the prior art and the present invention when the same bit line selection signal is continuously selected.

11 and 12 are bit line selection signal waveform diagrams for explaining another embodiment of the present invention.

Tables 1 to 3 are tables for explaining the operation of the bit line selection signal generation circuits.

The present invention relates to a method for driving a bit line selection signal of a DRAM, and more particularly, to a method for driving a bit line selection signal in which power required for driving a bit line selection signal is minimized to be suitable for a low power consumption DRAM.

Recently, in order to increase the degree of integration of a DRAM, a bidirectional shared sense amplifier method, in which two or more bit line pairs are connected to one sense amplifier in both directions, has been used.

The structure of this bidirectional shared sense amplifier is such that n bit pairs are connected to one sense amplifier (n is an integer greater than or equal to 2) so that the bit line and the sense amplifier are connected or separated through a bit line selection switch. .

In this structure, since multiple bit lines share one sense amplifier, the number of sense amplifiers is reduced, thereby reducing chip variation.

1 is a block diagram showing an example of such a bidirectional shared sense amplifier structure.

In the DRAM cell array 10-1, there are bit lines to which a plurality of cells are connected, and the bit lines (for example, BL, and / BL) include a bit line equalizer 11-1 and a bit line select switch 12. It is connected to one side of the sense amplifier unit 13 through -1).

On the other side of the sense amplifier unit 13, bit lines to which a plurality of cells of another DRAM cell array 10-2 are connected are connected through an equalizer 11-2 and a bit line select switch 12-2. .

The sense amplifier unit 13 is connected to a data input / output unit 14 to transfer data read by the sense amplifier to the data bus.

The bit line selection signals BS0 and BS1 generated by the bit line selection signal generator 15 are connected to the bit line selection switch.

The bit line selection signal BS0 generated by the bit line selection signal generation unit 15 is connected to the first bit line selection switch unit 12-1, and the bit line selection is connected to the second bit line selection switch unit 12-2. The bit line selection signal BS1 generated by the signal generator 15 is connected.

A bit line equalization signal is connected to the bit line equalizer. A bit line equalization signal BLEQ0 is connected to the first bit line equalizer 11-1 and a bit line equalization signal to the second bit line equalizer 11-2. BLEQ1 is connected.

The bit line selection signals BS0 and BS1 serve to select each bit line, and the sense amplifier 13 senses the potential difference of the connected bit line to increase the difference. The bit line equalization (equalization) part It serves to equalize and cancel the bit line, and de-equalizes the bit line as BLEQ0 and BLEQ1 signals before the word line is selected.

The data input / output unit 4 serves as a passage when reading or writing data.

The bit line selection signal generation unit 15 is a circuit which controls the bit line selection signal at the time of power-up, bit line selection, and precharge.

2 is a waveform diagram showing an operation example of a conventional bit line selection circuit. For example, the BS0 and BS1 signals are selected once, and are briefly divided into two cases, namely, bit line selection and precharge.

First, at the time of precharging, all signals are held at VCC regardless of the bit line selection signal in the previous state.

For example, when BS0 is selected when the bit line is selected, the selected BS0 goes up to VPP in the VCC state and connects the corresponding bit line with the sense amplifier. The VPP voltage is a voltage higher than Vth of the switching transistor than VCC.

BS1, on the other hand, is not selected and changes from VCC to VSS.

At the next precharge, both BS0 and BS1 become VCC. This is because the potential of the equalized bit line must be transferred to the sense amplifier in order to equalize the bit lines.

In this way, when the bit line is selected, the signal corresponding to the selected bit lines goes up to VPP, the rest is maintained at VSS, and when precharging, all signals are VCC to equalize the sense amplifier.

At the time of selection, the equalizer signal BLEQ is slightly lower than the / RAS signal in the bit line equalizer to be at a low level, so that the equalization of the bit lines BL and / BL is stopped and the bit lines are separated from the precharging voltage VBL.

At this time, the bit line select signal has a high level of VPP higher than Vcc + Vth, thereby allowing the bit line select switch of NMOS TR to connect the bit line to the sense amplifier without voltage loss.

After that, when the word line to be selected receives a low address and becomes a high level, charges stored in a cell connected to one bit line among a pair of BL, / BL pairs of bit lines are charged and have a slight high or low voltage.

At this time, the enable signal of the sense amplifier is applied to widen the voltage difference between Vcc and Vss between the bit lines, and eventually the data stored in the cell is transferred to the bit line and is transferred to the input / output line through the sense amplifier.

3 schematically illustrates a block diagram of a double shared sense amplifier structure in which four bit line pairs are connected to one sense amplifier.

In this example, the number of bit lines connected to one sense amplifier is doubled than the bidirectional shared sense amplifier structure of FIG.

The DRAM cell arrays 20-1 and 20-2 include bit lines to which a plurality of cells are connected, and the bit lines (eg, BL and / BL) are the bit line equalizer 21-1 and the bit line. It is connected to one side of the sense amplifier unit 23 via the selection switch units 22-1 and 22-2.

The bit lines to which the plurality of cells of the DRAM cell arrays 20-3 and 20-4 are connected to the other side of the sense amplifier unit 23 are connected to the bit line equalizer 21-2 and the bit line select switch 22-. 3) (22-4) is connected.

The sense amplifier 23 is connected to a data input / output unit 24 so as to transfer the data read by the sense amplifier to the data bus.

The bit line selection signal generation section 25 is connected to the generated bit line selection signals BSU0, BSU1, BSD0, and BSD1.

In this case, the BSU0, BSU1, BSD0, and BSD1 signals serve to select a bit line, and the BLEQU1, BLEQU0, BLEQD0, and BLEQD1 signals play bitline assimilation and release.

The bit line selection signal BSU0 generated by the bit line selection signal generator 15 is connected to the upper first bit line selection switch unit 22-1, and BSU1 is connected to the upper first bit line selection switch unit 22-2. BSD0 is connected to the upper second bit line select switch section 22-3, and BSD1 is connected to the lower second bit line select switch section 22-4, respectively.

A bit line equalization signal is connected to the bit line equalizer. A bit line equalization signal BLEQU0 for equalizing bit lines connected to the upper first bit line selection switch is connected to the first bit line equalization unit 21-1. The bit line equalization signal BLEQU1 for equalizing the bit lines connected to the lower first bit line select switch is connected, and the bit line connected to the upper second bit line select switch is connected to the second bit line equalizer 21-2. The bit line equalization signal BLEQD0 for equalizing the signals is connected, and the bit line equalization signal BLEQD1 for equalizing the bit lines connected to the lower second bit line selection switch unit is connected.

The bit line selection signal, the sense amplifier unit 23, the bit line selection signal generator 25, and the data input / output unit 24 serve as the example described in FIG. 1.

In this example, as shown in FIG. 2, when the signals BSU0 and BSU1 are selected once each, for example, both signals are maintained at VCC at the time of precharging regardless of the bit line selection signal in the previous state.

For example, when BSU0 is selected at the next bit line selection, the selected BSU0 goes up to VPP in the VCC state and connects the corresponding bit line with the sense amplifier. On the other hand, since BSU1 is not selected, it changes from VCC to VSS.

At the next precharge, both BSU0 and BSU1 become VCC.

As such, when the bit line is selected, signals corresponding to the selected bit lines are raised to VPP, the rest is maintained at VSS, and when precharging, all signals are VCC to equalize the sense amplifier. Other operations are similar to those of FIG.

4 is a conventional circuit diagram of the bit line selection signal generators 15 and 25, and FIG. 5 is a circuit diagram of the bit line selection signal generators 15 and 25 having two bit line selection signal generators.

As shown in FIG. 4, a conventional bit line selection signal generation circuit (called BSG) for generating a BS0 signal includes two NMOS MN2, two in series circuits of two PMOS MP1, MP2 and one NMOS MN1 connected to VCC. MN3 parallel circuit is connected to VSS. The PMOS MP3 connected to VPP is connected to the MN1 and MN2 contacts. Where MNOS and PMOS refer to MOS transistors. Same as below.

To generate the bit line signal BS #, the gates of PMOS MP1 and NMOS MN2 are connected to the BSSUM # signal, the gates of PMOS MP2 and NMOS MN3 are connected to SRSUM #, and the gates of NMOS MN1 and PMOS MP3 are connected to n300. . The output signal BS # is connected to the contacts of MP3 and MN3.

In order for the BSG configured to generate the bit line signal BS0, the gates of the PMOS MP1 and the NMOS MN2 are connected to the BSSUM0 signal, the gates of the PMOS MP2 and the NMOS MN4 are connected to the SRSUM0, and the gates of the NMOS MN1 and the PMOS MP3 are connected to the n300. . The output signal BS0 is connected to the contacts of MP3 and MN3. The connected bit line selection signal generator is named BSG0, and its operation is as shown in the left side of Table 1.

At the time of precharging, BSSUM0, BRSUM0 are 0, n300 is 1, and the output BS0 of this circuit is at the VCC level. 1 indicates high level, 0 indicates low level. At the time of precharging, when BSSUM0 and BRSUM0 become 0 and n300 becomes 1, MP1, MP2 and MN1 are turned on, and MP3, MN2 and MN3 are turned off to bring the output BS0 of this circuit to the VCC level.

When BS0 is selected, BSSUM0 and BRSUM0 become 0 and n300 also become 0, MP3 is on, MN1 is off, and the output BS0 of this circuit is brought back to the VPP level.

In the next precharging again, BSSUM0, BRSUM0 are 0, n300 is 1, and the output BS0 of this circuit is brought back to the VCC level.

Next, when BS1 is selected, BSSUM0 and BRSUM0 become 1 and n300 degrees 1, so that the output BS0 of this circuit becomes the VSS level.

Next, the bit line selection signal generation circuit BSG1 for generating the BS1 signal has the same circuit configuration as the BSG0 circuit, and only the input signal is connected to BSSUM1 instead of BSSUM0 signal, to BRSUM1 instead of SRSUM0, and to n301 instead of n300. . The output signal BS2 is connected to the contacts of MP3 and MN3.

The operation of the connected bit line selection signal generator is as shown in the right side of Table 1 below. That is, at the time of precharging, BSSUM1, BRSUM1 is 0, n300 is 1, and the output BS1 of this circuit is at VSS level.

When BS0 is selected, BSSUM1 and BRSUM1 become 1 and n301 degrees 1, and the output BS1 of this circuit is brought to the VSS level.

In the next precharging again, BSSUM1 and BRSUM1 are 0 and n301 is 1, and the output BS1 of this circuit is at the VCC level.

Next, when BS1 is selected, BSSUM1 and BRSUM1 become 0 and n301 also become 0, and the output BS1 of this circuit is brought to the VPP level.

The circuit of the bit line selection signal generator 25 of FIG. 3 has four bit line selection signal generators as shown in FIG. 4, and different input signals are connected to each other. When the respective output signals BSU0, BSU1, BSD0, and BSD1 are selected, only these signals are raised to the VPP level, and when the precharge is selected, they are at the VCC level, and when other signals are selected, they are at the VSS level.

In the prior art described above, since all the selection signals are maintained at VCC during power-up and precharging, as each bit line is selected, as shown in FIG. 2, the transition of each signal occurs several times from VCC to VSS or VSS to VCC. The consumption of power is increased. Therefore, it is not suitable to configure a low power DRAM.

The present invention is intended to reduce the power consumption by driving the bit line by configuring the bit line structure and the sense amplifier structure of the DRAM cell array as in the prior art, and configuring the bit line selection signal generation circuit differently from the prior art.

The present invention includes a plurality of memory cell arrays, a sense amplifier unit, a bit line, a bit line equalizer, a bit line selector, a data input / output unit, and a bit line select signal generator, each of which includes one bit amplifier. n (n is one or more integers, for example, two pairs or four pairs) are connected on the bit line, the bit line connected to the sense amplifier is through the bit line selection unit, the bit line through the bit line selection unit is a bit line It is connected to the cell array through the equalizer, the bit line equalizer performs the equalization and release, the bit line selector serves as a switch for connecting and disconnecting the bit line with the sense amplifier, and the sense amplifier section is a bit line pair selected at the time of sensing The data input / output unit sends out the voltage of the bit line from the sense amplifier or sends out external data. A bit line selection signal driving method in a DRAM for storing a cell in a cell through a line and sending the bit line selection signal to the bit line selection unit so that the sense amplifier and the bit line are connected to each other. to be.

In this method, when the bit line selection signal voltage is selected, only the bit line selection signal connecting one bit line pair selected from the pair of n pairs of bit lines connected to the sense amplifier to the sense amplifier is selected. The bit line select signals that connect the bit line to the sense amplifier are made at a voltage level that allows the bit line to be connected to the sense amplifier without loss of voltage and connects the remaining unselected pairs of bit lines to the sense amplifier. To a voltage level that makes it impossible; Thereafter, during the precharge period for bit line equalization, only the bit line selection signal that connects the previously selected bit line to the sense amplifier is made to the voltage level that the bit line selector can connect the bit line to the sense amplifier. The bit line selection signals, which have not previously connected the bit line to the sense amplifier, are maintained without change in voltage.

6 is a circuit diagram of the first embodiment of the bit line selection signal generation circuits 15 and 25 of the present invention, and FIG. 7 is a circuit diagram of the second embodiment of the bit line selection signal generation circuits 15 and 25 of the present invention.

Referring to FIG. 6, in the bit line selection signal generation circuit BSGEN # for generating the BS # signal, a series circuit of two NMOS MN10, MN11 and one PMOS MP10 is connected between VCC and VSS. The PMOS MP11 connected to VPP is connected to the MN10 and MN11 contact point (output node OP). Where NMOS and PMOS refer to MOS transistors. Same as below.

The output node OP is connected to the input node IP via inverter IV1 and from the input node IP via inverter IV2 to one input of the NAND gate.

The gates of the PMOS MP10 and NMOS MN11 are connected to the input node IP, connected to the BSSUM # signal via the transmission gate (transfer gate) TG at the input node IP, the SRSUM # signal is connected to the control input of the TG, and the n30 # signal. Is connected to the other input of the NAND gate.

The output of this NAND gate is connected to the level shift circuit 32 which changes the VCC level to the VPP level, and the output of this level shift circuit 32 is connected to the gates of MP11 and MN10.

As shown in FIG. 6, in the bit line selection signal generating circuit BSGEN0 for generating the BS0 signal, a series circuit of two NMOS MN10, MN11 and one PMOS MP10 is connected between VCC and VSS. The PMOS MP11 connected to VPP is connected to the MN10 and MN11 contact point (output node OP). Where NMOS and PMOS refer to MOS transistors. Same as below.

The output node OP is connected to the input node IP via inverter IV1 and from the input node IP via inverter IV2 to one input of the NAND gate.

The gates of the PMOS MP10 and NMOS MN11 are connected to the input node IP, from the input node IP to the BSSUM0 signal via the transmission gate (transfer gate) TG, the SRSUM0 signal is connected to the control input of the TG, and the n300 signal is connected to the NAND gate. Is connected to the other input of the.

The output of this NAND gate is connected to the level shift circuit 32 which changes the VCC level to the VPP level, and the output of this level shift circuit 32 is connected to the gates of MP11 and MN10.

The bit line selection signal generating circuit BSGEN1, which is exactly the same as the bit line selection signal generating circuit BSGEN0, is connected to a different signal, that is, connected to BSSUM1 instead of the BSSUM0 signal, connected to BRSUM1 instead of SSRUM0, and connected to n301 instead of n300. The BSGEN0 is combined with the bit line selection signal generator 30.

The operation of BSGEN0 in the bit line selection signal generator is shown in the left side of Table 2.

The operation of the bit line selection signal generation circuit BSGEN0 for generating the BS0 signal is irrelevant to the state of BSSUM0 at the time of precharging, and BRSUM0 is 0 and n300 is 0 and the output BS0 of BSGEN0 is at VCC or VSS level.

In other words, when BRSUM0 is 0, TG is off, regardless of the state of BSSUM0, and when n300 is 0, the NAND gate output goes high, turning off MP11 and turning on MN10. MP10 is on and MN11 is off and OP is at VCC level.If OP is low, IP is high and MP10 is off and MN11 is on. The VSS state is entered.

When BS0 is selected, BSSUM0 is 0, BRSUM0 is 1, and n300 is 1, so that the output BS0 of this circuit is at the VPP level. In this case, if BRSUM0 is 1, TG is on and IP is determined according to the state of BSSUM0. Therefore, when N300 is 1, the NAND gate output goes low, turning on MP11 and turning off MN10, the state of OP is VPP. It becomes

When precharging again, BRSUM0 is 0 and n300 is 0 regardless of BSSUM0, and the output BS0 of this circuit is at the VCC level. Because IP is low.

Next time BS1 is selected, BSSUM0, BRSUM0, and n300 are all 1, and the output BS0 of this circuit is at VSS level.

When precharging again after BS1 is selected, BRSUM0 is 0 and n300 is 0, regardless of BSSUM0, and the output BS0 of this circuit is at VSS level.

Next, the operation of the bit line selection signal generation circuit BSGEN1 for generating the BS1 signal is also as shown in the right side of Table 2.

When precharging, regardless of the state of BSSUM1, BRSUM1 becomes 0 and n301 becomes 0 so that the BS1 of output BS1 becomes VSS or VSS level.

When BS0 is selected, BSSUM1 and BRSUM1 become 1, n301 degrees 1, and the output BS1 of this circuit is brought to the VSS level.

At the next precharge, BRSUM1 becomes 0 and n301 becomes 0, regardless of BSSUM1, and the output BS1 of this circuit becomes the VSS level.

Next, when BS1 is selected, BSSUM1 is 0, BRSUM1 and n301 are all 1, and the output BS1 of the circuit is at the VPP level.

Next time, when precharging again, BRSUM1 becomes 0 and n301 becomes 0 regardless of BSSUM1, and the output BS1 of this circuit becomes the VCC level.

When BS1 is next selected, BSSUM1 is 0, BRSUM1 and n301 are all 1, and the output BS1 of this circuit is at the VPP level.

Thus, if the previous state of the output BS1 was VPP, even if BRSUM1 and n301 were both 0, regardless of BSSUM1, BS1 would be at VCC level, and BS1 would be at VSS if the previous state of output BS1 was VSS. The VSS level is reached.

This operation is the same with BSGEN0.

7 is a circuit diagram of a second embodiment of the bit line selection signal generation circuits 15 and 25 of the present invention.

As shown in Fig. 7, the bit line selection signal generation circuit NBSGEN0 for generating the BS0 signal uses the flip-flop structure in the existing BSG circuit to use the previously selected bit line selection signal for the next precharge. It is. Here the level shifter is used to level up VCC to VPP.

This connects the NAND3 gate with three inputs, two inputs to BRSUM0 and BRSUM0 via inverters IN3 and IN4, respectively, and n300 to the remaining inputs.

The output of this NAND3 gate is input to the CK terminal as the control signal of the flip-flop FF, and is connected to the gate of MN13 via the inverter IN5.

The input terminal D of the FF is connected to the output of the bit line selection signal generating circuit BSG, and the output Q terminal of the FF is connected to the output terminal through the NMOS MN13 to become a BS0 signal, and at the output of the bit line selection signal generating circuit BSG. It is connected to the output terminal via NMOS MN14, which becomes BS0 signal, and the gate of MN14 is connected to the output of NAND3.

The bit line selection signal generation circuit BSGEN1, which is exactly the same as the bit line selection signal generation circuit NBSGEN0, is connected to a different signal, that is, connected to BSSUM1 instead of the BSSUM0 signal, connected to BRSUM1 instead of SRSUM0, and to n301 instead of n300. The BSGEN0 is combined with the bit line selection signal generator 40.

The operation of NBSGEN0 in the bit line selection signal generator is shown in the left side of Table 3.

The operation of the bit line selection signal generation circuit NBSGEN0 for generating the BS0 signal is BSSUM0, BRSUM0 is 0 and n300 is 1 at the time of precharging, and the output BS0 of the NBSGEN0 is at the VCC or VSS level.

When BS0 is selected, BSSUM0, BRSUM0, and n300 are all zeros, and the output BS0 of this circuit is brought to the VPP level.

At the next precharging again, BSSUM0, BRSUM0 is 0, n300 is 1, and the output BS0 of this circuit is at the VCC level.

Next time BS1 is selected, BSSUM0, BRSUM0, and n300 are all 1, and the output BS0 of this circuit is at VSS level.

When precharging again after BS1 is selected, BSSUM0, BRSUM0 is 0, n300 is 1, and the output BS0 of this circuit is at VSS level.

Next, the operation of the bit line selection signal generation circuit NBSGEN1 for generating the BS1 signal is also as shown in the right side of Table 2.

At the time of precharge, BSSUM0, BRSUM0 is 0, n300 is 1, and the output BS1 of NBSGEN1 is at the VCC or VSS level.

When BS0 is selected, BSSUM0, BRSUM0, and n300 are all 1, so the output BS1 of this circuit is at VSS level.

At the next precharge, BSSUM0, BRSUM0 is 0, n300 is 1, and the output BS1 of this circuit is at VSS level.

When BS1 is next selected, BSSUM0, BRSUM0, and n300 are all zeros, so that the output BS1 of this circuit is at the VPP level.

When precharging again after BS1 is selected, BSSUM0, BRSUM0 is 0, n300 is 1, and the output BS0 of this circuit is at the VCC level.

So, even if the signal state that makes the same precharge signal state, that is, BSSUM1, BRSUM1 is 0 and n301 is 1, BS1 is at VCC level if the previous state of the output BS1 was VPP, and BS1 is VSS if the previous state of the output BS1 was VSS. Level.

The same goes for NBSGEN0.

8 is an example of the proposed bit line selection scheme. This is a proposed method to reduce the power consumption due to the signal transition of the bit line selection signal, which can be thought of as dividing into precharge when selecting the bit line. Keep only one defined signal at VCC.

For example, when BS0 is selected first during bit line selection, BS0 goes up from VCC to VPP to select a bit line, and BS1 remains unchanged because BS1 is not selected.

After precharging, the BS0 signal remains from VPP to VCC and equalizes the bit line. At this time, the BS1 signal is kept at VSS.

Then, if BS1 signal is selected again, BS1 signal goes up from VSS to VCC and then back to VPP. On the other hand, unselected BS0 falls to VSS. Such a method can reduce power consumption due to signal transition when selecting BS0, but has a disadvantage in that power consumption is increased more than in the prior art when selecting BS1. Accordingly, the present invention has devised a bit line selection method of the method shown in FIG.

FIG. 9 is an example of the bit line selection method of the present invention. In this case, as shown in FIG. 8 in that only one bit line selection signal becomes VCC in precharge, the signal becomes VCC in precharge in FIG. In the present example, the signal selected in the previous state at the time of precharging is held at VCC, so that the power consumption is reduced by reducing the number of signal transitions between VCC↔VSS no matter which bit line selection signal is selected.

If we divide this into precharge and bit line selection, the signal selected in the previous state is maintained at VCC and the remaining signals are maintained at VSS.

After the bit line selection, the selected signal goes up to VPP and the remaining signals remain at VSS.

FIG. 10 is a comparison between the prior art and the present invention when the same bit line selection signal is continuously selected. In the prior art, which is indicated by a dotted line, both signals are maintained at VCC during precharging, and thus power consumption due to signal transition. However, according to the present invention, which is indicated by a solid line, a signal that is not selected is kept at VSS, thereby reducing power consumption due to signal transition.

While all bit line selection signals are maintained at VCC during precharging in the prior art, power consumption is increased by generating a signal transition when selecting bit lines, whereas in the present invention, only one bit line selection switch is used during precharging. By maintaining the VCC, the number of signal transitions is reduced, which reduces power consumption and enables low power DRAM.

In particular, since the word lines are sequentially activated during the cell refresh operation requiring low power consumption, the same sense amplifiers are more likely to be selected. In this case, this method is particularly effective.

FIG. 11 illustrates another embodiment of the present invention, in which a double shared sense amplifier structure in which four bit line pairs are connected to one sense amplifier is a bit line driving method in a DRAM. You need four of BSU0, BSU1, BSD0, and BSD1.

This method is basically the same as in the case of FIG. 8, and when divided into the precharge instruction and the bit line selection, only one signal (BSD0 in this case) that is already determined in the precharge instruction is kept at VCC. Go down to VSS. When the bit line is selected, the selected signal goes up to VPP, and the unselected signal goes down to VSS. The circuit in which this method is used is shown in FIG.

This method equalizes the sense amplifier only with one of four signals, and thus can be implemented with less power consumption than the conventional bit line selection method.

The improvement of this structure in the manner according to the present invention is shown in FIG. Also in this case, the bit line selection signal selected in the previous state is maintained at VCC, and the remaining signals are maintained at VSS. In the bit line selection, the selected signal is held at VPP and the remaining signals not selected are held at VSS.

This method of the present invention will be said to have a greater power savings effect than the prior art which maintains all the bit line selection signals at VCC during precharge to generate signal transitions at bit line selection to increase power consumption.

In particular, since the word lines are sequentially activated during the cell refresh operation requiring low power consumption, the same sense amplifiers are more likely to be selected. In this case, this method is particularly effective.

Claims (6)

A plurality of memory cell arrays, a bit line connected to the memory cell, a bit line equalizer for precharging the bit line, a sense amplifier part connected to the bit line pairs to read data of the cell, and a bit line selection signal, 12. A method for selecting and driving a bit line in a DRAM comprising a bit line selection signal generator, a bit line selection unit for connecting a pair of bit lines to a sense amplifier in accordance with the bit line selection signal, and a data input / output unit. When selecting, only the bit line selection signal connecting one bit line pair selected from the pair of n bit lines connected to the sense amplifier to the sense amplifier can connect the bit line to the sense amplifier without losing the voltage of the bit line. A bit that makes the voltage level (Vpp) and connects the remaining bit line pairs that are not selected to the sense amplifier. The select signals are brought to a voltage level (Vss) that prevents the bit line selector from connecting the bit line to the sense amplifier, and then selects to connect the bit line to the sense amplifier just prior to the precharge period for bit line equalization. Only the bit line selection signals that have been used are made at a voltage level Vcc such that the bit line selection unit electrically connects the bit lines to the sense amplifiers, and the bit line selection signals that do not connect the bit lines to the sense amplifiers immediately before A method of driving a bit line selection signal, which is maintained without change. The method of claim 1, wherein the pair of n bit lines connected to the sense amplifier is two pairs of bit lines. The method of claim 1, wherein the n bit line pairs are four pairs of bit lines. In a circuit for generating a bit line select signal for connecting a pair of bit lines to a sense amplifier in a DRAM, a series circuit of two NMOSFETs MN10 and MN11 and one PMOSFET MP10 is connected between VCC and VSS, and is connected to a power supply VPP. The connected PMOS MP11 is connected to the output node OP which is the MN10 and MN11 contact point, connected to the input node IP through the inverter IV1 at the output node OP, and to the input of the NAND gate via the inverter IV2 at the input node IP, The gates of the PMOS MP10 and NMOS MN11 are connected to the input node IP, from the input node IP to the BSSUM0 signal via the transmission gate TG, the SRSUM0 signal to the control pressure of the TG, and the n300 signal to the other input of the NAND gate. The output of the NAND gate is connected to the level shift circuit 32 which changes the VCC level to the VPP level, and the output of the level shift circuit 32 is connected to the gates of MP11 and MN10. A generated bit line select signal generating circuit. A circuit for generating a bit line selection signal for connecting a pair of bit lines to a sense amplifier in a DRAM, the bit line selection signal generating circuit having three input signals BRSUM0, BSSUM0, and n300 for generating the bit line selection signal. And a flip-flop connected to an output of the bit line selection signal generation circuit (BSG) to use a previously selected bit line selection signal for the next precharge, and the bit line selection signal generation circuit (BSG). Two transistors connected to the three input signals BRSUM0, BSSUM0, and n300, and connected to the bit line select signal output terminal, a NAND gate for giving a control signal to the flip-flop, and a bit line selection according to the control signal of the NAND gate. A bit line selection signal generation circuit having two transistors for connecting a signal to an output node OP. The NAND circuit of claim 5, wherein the NAND has three inputs, the two inputs are connected to BRSUM0 and BSSUM0 through inverters IN3 and IN4, and n300 is connected to the remaining inputs, and the output of the NAND gate is a flip-flop. It is input to the CK terminal as a control signal and is connected to the gate of MN13 via inverter IN5, the input terminal D of FF is connected to the output of BSG, and the output Q terminal of FF is connected to the output terminal OP through NMOS MN13. And a bit line selection signal generation circuit configured to be connected to an output terminal via an NMOS MN14 to a BS0 signal at an output of a BSG that maintains all signals as a VCC during precharging, and connected to an output of a gate NAND3 of the MN14.