KR960011472B1 - Semiconductor Memory Manufacturing Method - Google Patents
Semiconductor Memory Manufacturing Method Download PDFInfo
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- KR960011472B1 KR960011472B1 KR1019930012365A KR930012365A KR960011472B1 KR 960011472 B1 KR960011472 B1 KR 960011472B1 KR 1019930012365 A KR1019930012365 A KR 1019930012365A KR 930012365 A KR930012365 A KR 930012365A KR 960011472 B1 KR960011472 B1 KR 960011472B1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0413—Manufacture or treatment of FETs having insulated gates [IGFET] of FETs having charge-trapping gate insulators, e.g. MNOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
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- H—ELECTRICITY
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
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Abstract
Description
제1도는 본 발명에 따라 반도체 기억장치를 제조하기 위한 레이아웃도.1 is a layout for manufacturing a semiconductor memory device according to the present invention.
제2a 내지 2d도는 본 발명의 한 실시예에 따라 반도체 기억장치를 제조하는 공정을 나타내는 단면도.2A through 2D are cross-sectional views illustrating a process of manufacturing a semiconductor memory device according to one embodiment of the present invention.
제3도는 본 발명의 또다른 실시예에 따라 제조된 기억장치의 단면도.3 is a cross-sectional view of a memory device manufactured in accordance with another embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 반도체 기판 2 : 소자분리 절연막1 semiconductor substrate 2 device isolation insulating film
3 : 비트라인 4 : 제1 절연막3: bit line 4: first insulating film
5 : 활성화영역 5A : 소오스/ 드레인 영역5: active area 5A: source / drain area
6 : 게이트 절연막 7 : 워드라인(게이트 전극)6 gate insulating film 7 word line (gate electrode)
8 : 제2 절연막 9 : 스페이서 절연막8 second insulating film 9 spacer insulating film
10 : 제3 절연막 11 : 전하저장전극10: third insulating film 11: charge storage electrode
12 : 캐패시터 절연막 13 : 플레이트 전극12 capacitor insulating film 13 plate electrode
14 : 제4 절연막 15 : 비트라인 콘택14: fourth insulating film 15: bit line contact
16 : 전하저장 전극 콘택 17 : 콘택홀16: charge storage electrode contact 17: contact hole
본 발명은 SOI(실리콘 온 인술레이터) 소자를 이용한 반도체 기억장치 제조방법에 관한 것으로, 특히 비트라인 콘택과 캐패시터 콘택의 공정여유도를 증가시키고 소자들간의 누설전류가 극소화되도록 한 반도체 기억장치 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor memory device using a silicon on insulator (SOI) device, and more particularly, to a method of manufacturing a semiconductor memory device which increases the process margin of bit line contacts and capacitor contacts and minimizes leakage current between devices. It is about.
종래 DRAM 구조에서는 고집적화 될수록 비트라인 콘택과 워드라인 사이의 간격 그리고 캐패시터 콘택과 비트라인/워드라인 사이의 간격이 급격히 감소하여 이들간의 단락 문제가 심각해지며 콘택 형성시 엄격한 정합도 조절이 요구되므로 공정여유도가 거의 없는 상태로 되고 있다. 그리고 단결정 실리콘 위에 전하저장 콘택을 형성할 경우 확산 접속면에서의 누설 전류와 전하저장 확산층간의 누설전류 등의 문제가 발생할 수 있으며 이러한 문제는 DRAM이 고집적화될수록 더욱 더 심각해진다.In the conventional DRAM structure, as the integration becomes higher, the gap between the bit line contact and the word line and the gap between the capacitor contact and the bit line / word line are drastically reduced, causing short-circuit problem between them. There is almost no state. In addition, when the charge storage contact is formed on the single crystal silicon, problems such as leakage current at the diffusion interface and leakage current between the charge storage diffusion layer may occur. This problem becomes more serious as the DRAM becomes more integrated.
따라서, 본 발명은 상술한 문제점을 해결하기 위해 SOI(실리콘 온 인술레이터) 소자를 이용하여 비트라인 콘택과 캐피시터 콘택의 공정여유도를 증가시키고 소자들간의 누설전류문제를 해결할 수 있는 반도체 기억장치 제조방법을 제공하는데 그 목적이 있다.Therefore, in order to solve the above problems, the present invention uses a silicon on insulator (SOI) device to increase the process margin of the bit line contact and the capacitor contact and to solve the leakage current problem between the devices. The purpose is to provide a method.
상기한 목적을 달성하기 위한 본 발명의 반도체 기억장치 제조방법은 반도체 기판(1) 위에 소자분리 절연막(2)과 전도체를 차례로 중착한 후 패턴화 공정으로 전도체 소정부위를 식각하여 기억소자의 비트라인(3)을 형성하는 단계와, 상기 전체 구조 위에 제1절연막(4)을 증착하고 패턴화 공정으로 소정의 제1절연막(4)을 식각하여 비트라인(3) 접속용 콘택홀(17)을 형성하는 단계와, 상기 단계로부터 폴리실리콘을 증착하고 패턴화 공정으로 소정의 폴리실리콘을 식각하여 박막 트랜지스터 활성화 영역(5)을 형성하는 단계와, 상기 활성화 영역(5) 상부에 열적산화 또는 화학 증착법으로 게이트 옥사이드를 증착하여 게이트 절연막(6)을 형성하는 단계와, 상기 게이트 절연막(6) 위에 전도체 및 제2절연막(7 및 8)을 차례로 증착하고 패턴화 공정으로 전도체 및 제2절연막(7 및 8)의 소정부위를 식각하여 게이트 전극(7)을 형성하는 단계와, 상기 전체구조 위에 절연막을 증착하고 비둥방성 식각하여 게이트 전극(7) 측벽에 스페이서 절연막(9)을 형성하고 다시 전체 구조위에 제3절연막(10)을 증착하는 단계와, 상기 단계로부터 패턴화 공정에 의해 소정부위의 상기 제3절연막(10)을 식각하여 전하저장용 콘택을 자기정립방법으로 형성하는 단계와, 상기 구조위에 전하저장용 전도체를 증착하고 패턴화 공정으로 소정 부분의 전하저장용 전도체를 식각하여 전하저장전극(11)을 형성한 다음 상기 전하저장전극(11) 위에 캐패시터 절연막(12)과 플레이트 전극(13)을 차례로 형성하는 단계로 이루어지는 것을 특징으로 한다.The semiconductor memory device manufacturing method of the present invention for achieving the above object is a bit line of the memory device by etching a predetermined portion of the conductor in the patterning process after the device isolation insulating film 2 and the conductor is sequentially stacked on the semiconductor substrate (1) (3) and depositing a first insulating film 4 on the entire structure and etching a predetermined first insulating film 4 by a patterning process to form a contact hole 17 for connecting the bit line 3. Forming a thin film transistor active region 5 by depositing polysilicon from the step and etching a predetermined polysilicon through a patterning process, and thermally oxidizing or chemical vapor deposition on the active region 5. Depositing a gate oxide to form a gate insulating film 6, depositing a conductor and a second insulating film 7 and 8 on the gate insulating film 6 in turn, and forming a conductor and a second film by a patterning process. Forming a gate electrode 7 by etching predetermined portions of the insulating films 7 and 8; depositing an insulating film over the entire structure and performing anisotropic etching to form a spacer insulating film 9 on the sidewalls of the gate electrode 7. And depositing a third insulating film 10 over the entire structure, and etching the third insulating film 10 at a predetermined portion by a patterning process from the step to form a charge storage contact by a self-establishment method. And a charge storage electrode 11 is formed by depositing a charge storage conductor on the structure and etching a predetermined portion of the charge storage conductor by a patterning process, and then forming a capacitor insulating film 12 on the charge storage electrode 11. It characterized in that the step consisting of sequentially forming the plate electrode (13).
이하, 첨부된 도면을 참조하여 본 발명을 더욱 상세하게 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in more detail the present invention.
제1도는 본 발명에 따라 반도체 기억 장치를 제조하기 위한 레이아웃도로서, 워드라인(7), 비트라인(3) 및 전하저장전극(11)이 위치할 영역이 도시되는데, 비트라인 콘텍(15)은 소오스/드레인 영역과 접속되는 부분을 나타내고, 전자저장전극 콘택(16)은 전하저장전극(11)과 소오스/드레인 영역(5A)이 접속되는 부분을 나타내며, 박막 트랜지스터의 활성화 영역(5)은 박막 트랜지스터로 동작되는 영역을 나타낸다.FIG. 1 is a layout diagram for manufacturing a semiconductor memory device according to the present invention, in which a region in which a word line 7, a bit line 3, and a charge storage electrode 11 are to be located is shown. Represents a portion connected to the source / drain region, the electron storage electrode contact 16 represents a portion to which the charge storage electrode 11 and the source / drain region 5A are connected, and the active region 5 of the thin film transistor A region operated by a thin film transistor is shown.
제2a 내지 2d도는 본 발명의 한 실시예에 따라 반도체 기억장치의 제조공정을 나타내는 단면도로서, 제2a도는 반도체 기판(1)위에 소자분리 절연막(2)과 전도체막(3)을 차례로 증식한 후 전도체막(3)을 패턴화 공정에 의해 식각하여 제1도에 도시된 비트라인(3)을 형성한 상태에서 제1절연막(4)을 증착하고, 상기 비트라인(3) 상부의 제1절연막(4)을 소정의 폭으로 패턴화하여 콘택홀(17)을 형성한 상태의 단면도인데, 패턴화 공정시 사용되는 감광막 마스크는 상기 비트라인(3)의 폭보다 크게해야 한다.2A through 2D are cross-sectional views illustrating a manufacturing process of a semiconductor memory device according to an exemplary embodiment of the present invention. The conductor film 3 is etched by a patterning process to deposit the first insulating film 4 in the state where the bit line 3 shown in FIG. 1 is formed, and the first insulating film over the bit line 3. It is sectional drawing of the state which formed the contact hole 17 by patterning (4) to predetermined width, The photoresist mask used at the time of the patterning process should be larger than the width | variety of the said bit line (3).
제2b도는 상기 공정을 마친 후 전체 구조위에 폴리실리콘을 증착하고 패턴화 공정에 의해 박막 트랜지스터의 활성화 영역(5)을 형성한 다음 게이트 옥사이드를 열산화법 혹은 화학증착법으로 증착하여 게이트 절연막(6)을 형성한 상태의 단면도인데 상기 활성화 영역(5) 형성된 후 문턱전압 조절용 이온주입 공정이 실시된다.FIG. 2B shows that after the process, polysilicon is deposited on the entire structure, the active region 5 of the thin film transistor is formed by a patterning process, and then gate oxide is deposited by thermal oxidation or chemical vapor deposition to form the gate insulating film 6. After the activation region 5 is formed, the ion implantation process for adjusting the threshold voltage is performed.
한편, 상기 활성화 영역(5)은 열처리로 폴리실리콘을 단결정화 하거나 결정입자를 크게 할 수 있다.On the other hand, the activation region 5 may be a single crystal polysilicon or a large crystal grain by the heat treatment.
제2c도는 상기 구조에 전도체(7)와 제2절연막(8)을 차례로 증착하고 패턴화 공정에 의해 상기 제2절연막(8)과 전도체(7)를 식각하여 박막 트랜지스터의 게이트 전극(7)을 형성한 다음 일정 두께의 절연막을 전체적으로 증착하고 비등방성 식각하여 상기 게이트 전극(7) 측벽에 스페이서 절연막(9)을 형성한 후 상기 게이트 전극증착하고 비동방성 식각하여 상기 게이트 전극(7) 측벽에 스페이서 절연막(9)을 형성한 후 상기 게이트 전극(7)을 자기 정렬 마스크로 하고, BF2, AS, B, P 등을 이온주입 소스로 하여 트랜지스터의 소오스/드레인 영역(5A)을 형성한 상태의 단면도인데, 도면부호(5B)로 표시되는 영역이 박막 트랜지스터의 채널영역이다.In FIG. 2C, the conductor 7 and the second insulating film 8 are sequentially deposited on the structure, and the second insulating film 8 and the conductor 7 are etched by a patterning process to etch the gate electrode 7 of the thin film transistor. And then depositing an insulating film having a predetermined thickness as a whole and anisotropically etching to form a spacer insulating film 9 on the sidewall of the gate electrode 7, and then depositing the gate electrode and anisotropically etching the spacer on the sidewall of the gate electrode 7. After forming the insulating film 9, the gate electrode 7 is used as a self-alignment mask, and the source / drain regions 5A of the transistor are formed using BF2, AS, B, P, etc. as ion implantation sources. The region indicated by 5B is a channel region of the thin film transistor.
제2d도는 상기 구조에서 제3절연막(10)을 증착한 후 마스크 공정과 식각 공정으로 제3절연막(10)을 식각하여 자기정합 콘택을 형성하고 전도체를 상기 구조 전체에 정착한 후 패턴화 공정에 의해 전하저장전극(11)을 형성한 상태에서 캐패시터 절연막(12)과 플레으트 전극(13)을 형성한 상태의 단면도인데, 캐패시터 절연막(12)으로 실리콘 옥사이드, 실리콘 질화막, 탄탈륨 옥사이드 또는 PZT와 같은 고유전율 박막이 사용된다.FIG. 2D illustrates the deposition of the third insulating layer 10 in the above structure, followed by etching the third insulating layer 10 by a mask process and an etching process to form a self-aligned contact, and fixing the conductor to the entire structure. The capacitor insulating film 12 and the plate electrode 13 are formed in the state where the charge storage electrode 11 is formed by the capacitor insulating film 12. High dielectric constant thin films are used.
제3도는 상기 제조 공정중 게이트 전극(워드라인;7)을 형성한 후 전체구조 상부에 제4절연막(15)을 증착하고 자기정립 콘택 형성방법이 아닌 직접 콘택형성 방법인 패턴화 공정으로 전하저장용 콘택을 형성한 상태에서 상기 제조 공정과 같은 공정으로 캐패시터를 형성한 상태의 단면도이다.FIG. 3 illustrates the formation of a gate electrode (word line) 7 during the manufacturing process, followed by depositing a fourth insulating layer 15 over the entire structure, and charge storage in a patterning process, which is a direct contact forming method, not a self-established contact forming method. It is sectional drawing of a state in which a capacitor was formed in the same process as the said manufacturing process in the state which formed the dragon contact.
이상에서 살펴본 바와같이, 기억소자 제조시 실리콘 온 인술레이터 구조를 도입함으로써 비트라과 워드라인 단락문제, 전하저장전극 콘택과 비트라인 도는 워드라인과의 단락문제를 해결할 수 있을 뿐 아니라 확산접속면에서의 누설전류가 없으므로 공정여유도가 증가되므로 고집적 기억소자 제조와 수율향상에 효과가 있다.As described above, the introduction of a silicon on insulator structure in the manufacture of a memory device can solve the problem of short-circuit and word line short-circuit, charge storage electrode contact and bit line or word line short-circuit. Since there is no leakage current, the process margin is increased, which is effective in fabricating highly integrated memory devices and improving yield.
Claims (4)
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019930012365A KR960011472B1 (en) | 1993-07-02 | 1993-07-02 | Semiconductor Memory Manufacturing Method |
| JP6151017A JP2796249B2 (en) | 1993-07-02 | 1994-07-01 | Method for manufacturing semiconductor memory device |
| US08/266,357 US5447879A (en) | 1993-07-02 | 1994-07-01 | Method of manufacturing a compactor in a semiconductor memory device having a TFT transistor |
| US08/265,269 US5585284A (en) | 1993-07-02 | 1994-07-01 | Method of manufacturing a SOI DRAM |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019930012365A KR960011472B1 (en) | 1993-07-02 | 1993-07-02 | Semiconductor Memory Manufacturing Method |
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| KR950004563A KR950004563A (en) | 1995-02-18 |
| KR960011472B1 true KR960011472B1 (en) | 1996-08-22 |
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