KR960010339B1 - Manufacturing method of semiconductor device - Google Patents

Abstract

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Description

Semiconductor device manufacturing method

1 is a graph showing the relationship between shrinkage and temperature of glass substrates.

2 is a graph showing the relationship between the shrinkage rate of a glass substrate and the heating time.

3 is a graph showing the relative intensity in laser Raman spectroscopy for semiconductor layers.

4A to 4E are schematic cross-sectional views showing a method for manufacturing a thin film transistor according to the present invention.

5 is a graph showing drain current versus gate voltage of a thin film transistor.

6 is a graph showing a relationship between field effect mobility and gate voltage of a thin film transistor.

7 is a graph showing field effect mobility of a thin film transistor.

8 is another graph showing the relationship between shrinkage and temperature of glass substrates.

9 is another graph showing the relationship between the shrinkage rate of a glass substrate and the heating time.

10 is another graph showing the relative intensity in laser Raman spectroscopy for semiconductor layers.

FIG. 11 is another graph showing the relative intensity in laser Raman spectroscopy for semiconductor layers. FIG.

12A to 12E are schematic cross-sectional views showing a method for manufacturing a thin film transistor according to the present invention.

13 is another graph illustrating drain current vs. gate voltage characteristics in a thin film transistor.

14 is a graph showing the relationship between field effect mobility and gate voltage in a thin film transistor.

15 is another graph showing drain current vs. gate voltage characteristics in a thin film transistor.

16A to 16E are schematic cross-sectional views showing a method for manufacturing a thin film transistor according to the present invention.

17 is another graph showing drain current versus gate voltage characteristics in a thin film transistor.

18 is a graph showing a relationship between field effect mobility and gate voltage in a thin film transistor.

19 is another graph showing field effect mobility in a thin film transistor.

20 is a graph illustrating drain current vs. gate voltage characteristics in a thin film transistor.

The present invention relates to a method of manufacturing a semiconductor device.

Techniques for forming a non-single crystal semiconductor layer on a glass substrate by plasma CVD or reduced pressure CVD and heating the substrate at about 600 ° C. to crystallize the layer into a polycrystalline semiconductor layer are well known in the semiconductor device manufacturing art. Explaining this thermocrystallization process, the temperature initially rises from room temperature (ie the initial stage). The temperature is then maintained at about 600 ° C. for several hours to several tens of hours (ie, intermediate stage) and finally the temperature is lower than room temperature (ie, final stage). If inexpensive glass, such as a large-sized liquid crystal display device, undergoes a thermal crystallization process at about 600 ° C., the glass substrate shrinks due to the strain point of about 600 ° C. Volume becomes smaller than that at the initial stage), whereby an internal strain is created in the semiconductor layer made on the substrate. In addition, the photographic plate type for later use becomes deformed due to shrinkage of the glass substrate. So the mask alignment in the next process becomes difficult to execute. According to one embodiment, the interface state in the semiconductor layer formed from the substrate is increased due to the internal pressure, so that the electrical properties of the semiconductor layer are poor. For this reason, a technique for obtaining a semiconductor layer having excellent electrical properties from a glass substrate has been required in the field of manufacturing semiconductor devices.

An object of the present invention is to provide a method of manufacturing a high performance semiconductor device. Another object of the present invention is to provide a semiconductor device comprising a channel region of high performance field effect mobility.

To achieve these and other purposes, the glass substrate is first heated in an inert gas or non-oxidizing atmosphere at a temperature not higher than the strain point of the glass substrate.

A non-single crystalline semiconductor layer is then formed on the substrate, and the non-single crystalline semiconductor layer is crystallized by heat in an inert gas or non-oxidizing atmosphere. The volume of the glass substrate at room temperature after the glass substrate heating process is smaller than the volume at room temperature before the glass substrate heating process, for example. In other words, the glass substrate shrinks after heating. By this glass substrate heating process, when the non-single crystal semiconductor layer formed in the glass substrate is crystallized by heat, the volume of the glass substrate is not so reduced. That is, the shrinkage of the glass substrate is very small. Therefore, a crystallized semiconductor free of internal pressure can be obtained by the crystallization process.

Non-monocrystalline semiconductors include amorphous semiconductors, semi-amorphous semiconductors, microcrystalline semiconductors, and incomplete polycrystalline semiconductors. A microcrystalline semiconductor is defined as an amorphous semiconductor in which crystals are dispersed. On the other hand, an incomplete polycrystalline semiconductor is defined as a semiconductor in a polycrystalline state in which crystal growth is incomplete, that is, a crystal can grow. The strain point of the glass is defined as the temperature when the viscosity V of the glass is 4 × 10 ¹⁴ poises (log (V) = 1.45).

The formation of a semiconductor layer on a substrate according to the first embodiment of the present invention will be mentioned below. The substrate used in the first embodiment is AN-2 non-alkali glass having a strain point of 616 ° C. produced by Asahi Glass Company. AN-2 non-alkali glass consists of SiO ₂ (53%), Al ₂ O ₃ (11%), B ₂ O ₃ (12%), RO (24%) and R ₂ O (0.1%). The glass substrate is heated to 610 ° C. for 12 hours in an electric furnace. Glass-based heating is carried out under atmospheric pressure in an inert gas, for example N ₂ atmosphere.

After heating, the silicon compound layer, for example, SiO ₂ layer, is formed to a thickness of 20 nm by sputtering to prevent the protective alkali ions present in the glass substrate from entering the device formed on the substrate. An amorphous silicon layer is then formed thereon to a thickness of 100 nm. The amorphous silicon layer is heated to 600 ° C. for 96 hours in an electric furnace to crystallize. Crystallization is performed under atmospheric pressure in an inert gas atmosphere, for example N ₂ , to prevent the amorphous silicon layer from reacting with a gas such as oxygen.

The relationship between shrinkage and temperature is explained below.

In the same manner as in the first embodiment, the glass substrate A (AN-2 non-alkali glass) heated in advance is prepared. Moreover, the glass base material B (AN-2 non-alkali glass) which has never been heated is prepared. First, the volume of each substrate is measured at room temperature (the measured volume is called V ₁ ). These glass substrates are then heated at various temperatures for 12 hours. After heating, the volume of each substrate is re-measured at room temperature (the measured volume is referred to as V ₂ ). The shrinkage of each substrate is then calculated by the respective volumes V ₁ and V ₂ . In FIG. 1, the relationship between the shrinkage ratio and the temperature of the heated glass substrate A is shown by line A, and the case of glass substrate B is shown by line B. In FIG. As shown in FIG. 1, the shrinkage ratio of the preheated glass substrate A is 1/5 or less of the shrinkage ratio of the glass substrate B. FIG. It can also be seen that the shrinkage tends to increase exponentially with the increase in temperature. In the manufacture of thin film transistors, the mask alignment error in the subsequent photolithography process has already been reduced since the shrinkage rate of the already heated glass substrate after the crystallization process is 1/5 or less than that of the unheated glass substrate after the crystallization process. The glass substrate that was heated is 1/5 or less than that of the unheated glass substrate. Therefore, it is possible to manufacture a large sized thin film transistor in one step.

Next, the relationship between the shrinkage rate and the heating cycle is explained. In the same manner as in the first embodiment, the preheated glass substrate A '(AN-2 non-alkali glass) and the preheated glass substrate B' (AN-2 non-alkali glass) are prepared. First, the volume of each substrate is measured at room temperature (the measured volume is called V ₁ ). These glass substrates are then heated at 600 ° C. for each time period. After the heating process, the volume of each substrate is remeasured at room temperature (the volume obtained is called V ₂ ). Thus, the shrinkage of each substrate is calculated by the volume V ₁ and volume V ₂ , respectively.

The relationship between the shrinkage rate of the glass substrate A 'heated in FIG. 2 and the heating time is shown by the curve A', and the case of the glass substrate B 'is shown by the curve B'.

As shown in FIG. 2, the glass substrate shrinks during the first few hours of the heating process, and curves A 'and B' tend to saturate over time. When heated for 96 hours, the shrinkage of the glass substrate A 'is only about 500 ppm, while the shrinkage of the glass substrate B' is about 2000 ppm. It is evident in FIGS. 1 and 2 that the thin film transistor can be reduced in advance by heating the glass substrate after the crystallization process.

3 shows the relative intensity in Raman spectroscopy for the semiconductor layer. In the figure, curve a is shown for the silicon semiconductor layer a crystallized according to the first embodiment. Curve (b) shows the semiconductor layer (b) formed in the same manner as in the first embodiment except that the glass substrate (AN-2 non-alkali glass), which has never been heated, is used instead of the preheated glass substrate. . The curve (c) also shows the semiconductor layer (c) formed in the same manner as in the first embodiment except that the quartz substrate was used instead of the preheated AN-2 non-alkali glass substrate. The ordinate in FIG. 3 represents the relative intensity of the crystallinity of the semiconductor layers.

As shown in FIG. 3, the crystallinity of the silicon semiconductor layer (a) obtained according to the first embodiment is much higher than the values of the semiconductor layers (b) and (c). The semiconductor layers (a) and (c) each exhibit sharp peaks at the same number of waves and the location of these sharp peaks is inherent to the polycrystalline silicon.

Therefore, similarly to the semiconductor layer (a) formed in accordance with the first embodiment, the semiconductor layer (c) formed on the quartz substrate is a high crystallinity polycrystalline body. The internal pressure generated by the crystallization process in the silicon semiconductor layer (a) is very small due to preheating of the glass substrate. As mentioned above, it is advantageous to preheat the glass substrate at a temperature not higher than the strain point of the glass substrate. After the crystallization process, the shrinkage of the glass substrate is very small and the internal pressure generated in the crystallized semiconductor layer is very small, which improves crystallinity and electrical properties.

As shown in FIG. 3 with respect to the semiconductor layer (b), the peak appears at a position slightly different from the intrinsic position of the polycrystalline silicon. This is because the property of the semiconductor layer b is affected by the internal pressure generated therein. The activation energy for the AN-2 non-alkali glass is about 0.08 eV. This corresponds to the transition point of the glass. The activation energy is calculated by the equation representing the straight line of FIG.

R = Aexp (-Ea / kT)

A: proportionality constant, Ea: activation energy, k: Boltzmann constant

Glass base heating may be performed under reduced pressure instead of atmospheric pressure.

The manufacture of a polycrystalline silicon thin film transistor with reference to FIGS. 4A to 4E will be mentioned according to the second embodiment of the present invention. Glass substrate 1 (AN-2 non-alkali glass) is heated to 610 ° C. for 12 hours in an electric furnace. This heating is carried out under atmospheric pressure in an inert gas atmosphere, for example N ₂ . Instead, it may be performed in an inert gas atmosphere containing hydrogen adduct under atmospheric pressure or reduced pressure.

In the glass substrate 1, for example, a silicon compound layer ₂ such as an SiO ₂ layer is formed to a thickness of 200 nm by an RF sputtering method. This formation is carried out under pressure 0.5 Pa, temperature 100 ° C., RF frequency 13.56 MHz and RF output 400 W.

Subsequently, the amorphous silicon active layer 3 is formed to a thickness of 100 nm by RF sputtering on the silicon compound layer. In this case the formation is carried out under pressure 0.5 Pa, temperature 150 ° C., RF frequency 13.56 MHz, RF output 400 W. The amorphous silicon layer 3 is heated at atmospheric pressure in an inert gas atmosphere such as N ₂ for 96 hours between 400 ° C. and 800 ° C., generally between 500 ° C. and 700 ° C., for example 600 ° C. Crystallize. This crystallization process is carried out under high vacuum.

The crystallized silicon layer 3 is partially removed to obtain the form shown in FIG. 4A. Subsequently, the n-type amorphous silicon layer 4 had a pressure of 6.65 Pa, a temperature of 350 ° C., an RF frequency of 13.56 MHz, an RF output of 400 W, PH ₃ (5%): SiH ₄ : H ₂ = 0.2 SCCM; 0.3SCCM; 50 nm thick by PCVD at a rate of 50 SCCM. The silicon layer 4 is then partially removed so that the gate region is formed as shown in FIG. 4B.

The gate oxide film (SiO ₂ ) 5 is formed to a thickness of 100 nm by sluttering as shown in FIG. 4C at a pressure of 0.5 Pa, a temperature of 100 ° C., an RF frequency of 13.56 MHz, and an RF output of 400 W. As shown in FIG. The gate oxide film 5 is then partially removed to form contact holes as shown in FIG. 4D.

Finally, 300 nm thick aluminum is formed by vacuum deposition and patterned into the electrode 6. This completes the polycrystalline silicon thin film transistor a as shown in FIG. 4E.

In FIG. 4E, S denotes a source electrode, G denotes a gate electrode, and D denotes a drain electrode.

For comparison, the polycrystalline silicon thin film transistor (b) was manufactured in the same manner as in the second embodiment except that the unheated AI-2 non-alkali glass substrate was used instead of the pre-heated AN-2 non-alkali glass substrate. do. In addition, the polycrystalline silicon thin film transistor (c) is made in the same manner as in the second embodiment except that the quartz substrate is used instead of the preheated AN-2 non-alkali glass substrate. The I _D (drain current) -V _G (gate voltage) characteristics of the thin film transistors (a), (b) and (c) are represented by curves (a) (b) and (c) in FIG. As shown in FIG. 5, compared with the thin film transistor b, the I _D -V _G characteristics of the thin film transistor a are improved considerably. In addition, the electrical property of the transistor (a) is close to the electrical property of the thin film transistor (c).

The relationship between the gate voltage and the field effect mobility of the thin film transistors (a) (b) (c) is shown in FIG. 7 shows the field effect mobility. The letter a represents a thin film transistor manufactured according to the second embodiment, the letter b represents a thin film transistor manufactured in the same manner as that of the thin film transistor b, and the letter c represents that of the thin film transistor c. The thin film transistor manufactured by the same method is shown. 6 and 7 show that the field effect mobility of the thin film transistor a is greater than that of the thin film transistor b and is substantially the same as that of the thin film transistor c.

It will be described below that the semiconductor layer is formed on the substrate according to the third embodiment of the present invention.

AN-2 non-alkali glass having a strain point of 616 ° C. is used as the substrate. This glass substrate is heated to 610 ° C. for 12 hours in a steam chamber. This heating process is carried out under atmospheric pressure in an inert gas atmosphere such as N ₂ containing 50% hydrogen. Subsequently, using a target made of silicon, a silicon compound layer such as, for example, a SiO ₂ layer is formed to a thickness of 200 nm by an RF magnetron sputtering device, and then the amorphous silicon layer is formed with a hydrogen partial pressure of 0.75 mTorr and an argon partial pressure of 3.00 mTorr. And 100 nm thick by means of RF magnetron sputtering in an atmosphere with an RF output of 400W. The amorphous silicon layer is then crystallized by heating at 600 ° C. for 96 hours.

In the same manner as in the third embodiment, the shrinkage ratio of the pre-heated glass base material D is measured. In addition, the value of the glass base material E which has never been heated is also measured. The relationship between the shrinkage ratio and the temperature of the glass substrates (D) and (E) is shown as lines (D) and (E) in FIG. 8, respectively. The shrinkage of each substrate in FIG. 8 is calculated in the same way as in FIG. As is apparent, the shrinkage of the heated glass substrate (D) is much lower than that of the unheated glass substrate (E).

Next, the relationship between the contracted meat and the heating cycle is examined. In the same manner as in the third embodiment, the heated glass substrate D '(AN-2 non-alkali glass) and the unheated glass substrate E' (AN-2 non-alkali glass) are heated at 600 占 폚. The relationship between the shrinkage of the substrates D 'and E' and the heating period is shown by curves D 'and E' in FIG. The shrinkage of each substrate in FIG. 9 is calculated in the same way as in FIG. As a result, when the glass substrate is heated for 96 hours, the shrinkage of the glass substrate E 'is about 2000 PPm, while the value of the glass substrate D' is only about 500 PPm.

FIG. 10 shows the relative intensity in Raman spectroscopy on the semiconductor layer. In this figure, the curve d is shown for the silicon semiconductor layer d made of crystal according to the third embodiment. Also, curve (e) is the third except that the unheated AN-2 non-alkali glass substrate is used in place of the pre-heated AN-2 non-alkali glass substrate and the amorphous silicon layer is formed by plasma CVD instead of the sputtering method. The silicon semiconductor layer e formed in the same manner as in the embodiment is shown. Further, the curve f is formed by the same method as in the third embodiment except that the quartz substrate is used instead of the pre-heated AN-2 non-alkali glass substrate and the amorphous silicon layer is formed by plasma CVD instead of the sputtering method. The silicon semiconductor layer f is shown, and the semiconductor layer f is a polycrystal.

In FIG. 10, the ordinate indicates the relative strength of the crystallinity of the semiconductor layers. It can be seen from FIG. 10 that the crystallinity of the silicon semiconductor layer d is very high in comparison with the values of the semiconductor layers e (f) according to the third embodiment. Like the semiconductor layer f, the semiconductor layer d shows the highest point with the same number of waves. This means that like the semiconductor layer f, the silicon semiconductor layer d is a high crystallinity polycrystal.

As shown in FIG. 10, the semiconductor layer e exhibits a sharp peak at a slightly different position than polycrystalline silicon.

11 shows the relative intensities for the semiconductor layers in Raman spectroscopy. In the figure, the curve D is shown for the semiconductor layer d formed according to the third embodiment.

Curve F also shows the same as in the third embodiment except that hydrogen is not introduced into the RF magnetron sputtering device during the formation of the amorphous silicon layer and that the argon partial pressure is maintained at 3.75 mTorr in the device during the formation of the amorphous silicon layer. The semiconductor layer f formed by the same method is shown. The Gdara curve G shows a semiconductor layer formed by the same method as in the third embodiment except that the hydrogen partial pressure and argon partial pressure in the RF magnetron sputtering apparatus maintain 0.15 mTorr and 3.50 mTorr, respectively, during the formation of the amorphous silicon layer. Indicate for G). In the case of F without hydrogen injection and in the case of G where the hydrogen partial pressure is maintained at 0.15 mTorr, they do not show a sharp peak at a wave number of 520 cm ⁻¹ . On the other hand, in the case of the semiconductor layer (d) formed in accordance with the third embodiment, a sharp peak is shown at a wave number of 520 cm ^-1 . This means that the semiconductor layer (d) is polycrystalline. As a result, it can be seen that hydrogen injection into the RF magnetron sputtering device during sputtering is preferable. This is because the microstructure is prevented from being formed in the semiconductor layer by hydrogen injection during sputtering, whereby crystallization is performed with lower activation energy. When hydrogen is injected during sputtering, the semiconductor layer may crystallize at a temperature of 800 ° C. or lower. Glass base heating may be performed under reduced pressure instead of atmospheric pressure.

The manufacture of a polycrystalline silicon thin film transistor with reference to FIGS. 12A-12E will be mentioned according to the fourth embodiment of the present invention. The glass substrate 11 (AN-2 non-alkali glass) is washed by ultrasonic means. The glass substrate 11 is heated at 610 ° C. for 12 hours. Glass-based heating is carried out in an inert gas atmosphere, such as N ₂ , containing 50% hydrogen at atmospheric pressure. Then, for example, a silicon compound layer 12, such as a SiO ₂ layer, is formed 200 nm thick on the glass substrate 11 by the RF magnetron sputtering method. This formation is carried out in an argon atmosphere under a pressure of RF frequency 13.56 MHz, RF output 400 W, temperature 100 ° C., and 0.5 Pa. On the silicon compound layer, the amorphous silicon activation layer 13 is formed to a thickness of 100 nm by the RF magnetron sputtering method. This formation is carried out in an atmosphere of RF frequency 13.56 MHz, RF output 400 W, temperature 100 ° C., argon partial pressure 3.00 Torr and hydrogen partial pressure 0.75 Torr. The amorphous silicon layer 13 is then subjected to heating in an inert gas atmosphere such as N ₂ in an electric furnace for 96 hours at 400 ° C.-800 ° C., generally 500 ° C.-700 ° C., for example 600 ° C. Crystallized by This crystallization process may be carried out in an inert gas atmosphere containing hydrogen or carbon monoxide or in a carbon monoxide atmosphere or in a hydrogen atmosphere to prevent the amorphous silicon layer from reacting with a gas such as oxygen. The crystallized silicon layer 13 is partially removed to obtain the form of FIG. 12A.

Subsequently, the n ⁺ type amorphous silicon layer 14 is formed on the silicon layer 13 with a thickness of 50 nm by an RF magnetron sputtering method. This formation is performed in an atmosphere where the RF frequency is 13.56 MHz, the RF output is 400 W, the temperature is 150 ° C., the hydrogen partial pressure is 0.75 Torr, the argon partial pressure is 3.00 Torr, and the PH ₃ partial pressure is 0.05 Torr. Silicon layer 14 is then partially removed to obtain the gate region as shown in FIG. 12B. The gate oxide film (SiO ₂ ) 15 is then formed at 100 nm by RF magnetron sputtering under a pressure of RF output 400 W, RF frequency 13.56 MHz, temperature 100 ° C., 0.5 Pa, as shown in FIG. 12C. The gate oxide film 15 is then partially removed to form contact holes as in FIG. 12d.

Finally, a 300 nm thick aluminum layer is formed by vacuum deposition and patterned into the electrode 16. The polycrystalline silicon thin film transistor shown in FIG. 12E is completed. In FIG. 12E, S denotes a source electrode, G denotes a gate electrode, and D denotes a drain electrode.

For comparison, the polycrystalline silicon thin film transistor h is manufactured by the same method as in the fourth embodiment except that the amorphous silicon activation layer 13 is formed by plasma CVD instead of the RF magnetron sputtering method. In FIG. 13, the I _D -V _G characteristics of the thin film transistor h are shown by the curve h. In addition, the characteristic of the thin film transistor g which concerns on 4th Embodiment is shown by the curve g. As shown in FIG. 13, the I _D -I _G characteristics of the two thin film transistors are very similar. Further, the relationship between the gate voltage V _G and the field effect mobility μ for the thin film transistor g and the thin film transistor h is shown by the curve g (h) in FIG. As is apparent from this figure, the field effect mobility of the two thin film transistors g and h is very similar. These results show that the characteristics of the thin film transistor h in which the amorphous silicon layer 13 is formed by plasma CVD are almost the same as those of the thin film transistor g according to the fourth embodiment.

For further comparison, the polycrystalline silicon thin film transistor (i) is manufactured in the same manner as in the fourth embodiment except that the glass substrate is heated in a nitrogen atmosphere containing no hydrogen. The I _D -V _G characteristic of the thin film transistor i is shown by the curve i in FIG. The characteristics of the transistor g according to the fourth embodiment are shown by the curve g. It is shown in FIG. 15 that the characteristics of the thin film transistor g are superior to those of the thin film transistor i. This is because hydrogen etches oxygen present in the glass substrate in the thin film transistor g, so that the electrical properties of the thin film transistor g do not deteriorate. In the fourth embodiment, heating and washing of the glass substrate are performed in one step. In order to reduce the number of manufacturing steps, it is preferable to heat the glass substrate in an inert gas atmosphere containing hydrogen as described above. Since carbon monoxide also plays a role in removing oxygen from the glass substrate, the glass substrate heating is preferably performed in an inert gas atmosphere containing taso monoxide.

Referring to FIGS. 16A to 16E, the manufacture of a coplanar polycrystalline silicon thin film transistor according to the fifth embodiment of the present invention will be mentioned.

The glass base material 21 (AN-2 non-alkali glass) is heated in an electric furnace to 610 degreeC for 12 hours. This heating is carried out under atmospheric pressure in an inert atmosphere, for example N ₂ . Glass base heating can be performed in hydrogen or carbon monoxide atmosphere or in an inert gas atmosphere containing hydrogen or carbon monoxide. A silicon compound layer, for example, SiO ₂ layer 22, is formed to a thickness of 200 nm by RF sputtering at a RF output of 400 W, an RF frequency of 13.56 MHz, a temperature of 100 ° C., and a pressure of 0.5 Pa.

The amorphous silicon active layer 23 having a thickness of 100 nm on the silicon compound layer 22 is formed by RF sputtering at an RF output of 400 W, an RF frequency of 13.56 MHz, a temperature of 150 ° C., and a pressure of 0.5 Pa.

The amorphous silicon layer 23 is crystallized by heating to a temperature of 400 ° C to 800 ° C, typically 500 ° C to 700 ° C, for example 600 ° C, for 96 hours in a nitrogen atmosphere containing carbon monoxide. This crystallization is carried out in an electric furnace under atmospheric pressure or reduced pressure. Since carbon monoxide oxidizes oxygen present in the glass substrate, the amorphous silicon layer 23 is not affected by oxygen. The crystallization process is performed by partially irradiating the silicon layer 23 with a laser so that the temperature of the silicon layer 23 is 400 ° C to 800 ° C.

In this case, at least part of the carbon dioxide layer 23 irradiated with laser is crystallized to be used as the channel region. The silicon layer 23 is then partially removed to form the shape of FIG. 16A. Reference numeral 23 in FIG. 16 denotes a channel region formed of a crystallized silicon layer.

n ⁺ type amorphous silicon layer 24 has a temperature of 35 ° C., RF frequency 13.56 MHz, RF output 400 W, PH ₃ (5%): SiH ₄ : H ₂ = 0.2SCCM: 0.3SCCM: 50SCCM, pressure 6.65Pa Under 50rpm thickness for PCVD method.

A 100 nm thick gate oxide film 25 is then formed by sputtering under an RF output of 400 W, an RF frequency of 13.56 MHz, a temperature of 100 DEG C, and a pressure of 0.5 Pa, as shown in FIG. The gate oxide film 25 is partially removed to form contact holes as shown in FIG. 16D.

Finally, a 300 nm thick aluminum layer is formed by vacuum deposition and patterned with electrodes 26. Then, as shown in FIG. 16E, the polycrystalline silicon thin film transistor j is completed. In FIG. 16E, S denotes a source electrode, G denotes a gate electrode, and D denotes a drain electrode.

For comparison, the polycrystalline silicon thin film transistor (k) is similar to the embodiment of FIG. 5 except that an unheated glass substrate (AN-2 non-alkali glass) is used instead of a pre-heated AN-2 non-alkali glass substrate. Prepared in the same way.

The polycrystalline silicon thin film transistor m is manufactured in the same manner as in the fifth embodiment except that the quartz substrate is used in place of the previously heated AN-2 non-alkali glass.

The I _D -V _G characteristics of the thin film transistors j, k, and m are shown by curves j, k, and m in FIG. 17, respectively. From this figure, it can be seen that the I _D -V _G characteristics of the thin film transistor j according to the fifth embodiment are considerably formed as compared with the thin film transistor k using the glass substrate which is not heated.

The electrical properties of the thin film transistor j are similar to those of the thin film transistor m formed from a quartz substrate.

FIG. 18 shows the relationship between the gate voltage V _G of the thin film transistors j (k) (m) and the field effect mobility μ.

19 shows field effect mobility. Here, the letter j denotes a thin film transistor manufactured in the same manner as that of the thin film transistor j, the letter m denotes a thin film transistor made in the same manner as the thin film transistor k, and the letter m denotes the thin film transistor m A thin film transistor made in the same way as the one is displayed. As shown in FIG. 18 and FIG. 19, the field effect mobility [mu] of the thin film transistor j according to the fifth embodiment is higher than the field effect mobility of the thin film transistor made from the unheated AI-2 non-alkali substrate. It is almost the same as the field effect mobility of the thin film transistor m made from the substrate.

For further comparison, the thin film transistor n is manufactured in the same manner as in the fifth embodiment except that the amorphous silicon layer 23 is crystallized in 100% nitrogen atmosphere instead of nitrogen atmosphere containing 50% carbon monoxide. .

In these thin film transistors n, field effect mobility exceeding 100 cm 2 / Vs could not be obtained. In contrast, for thin film transistors manufactured according to the FIG. 5 embodiment, 10% or more of all products have field effect mobility in excess of 100 cm 2 / Vs. In FIG. 20, the I _D -V _G characteristics of the thin film transistors j and n are shown by the curve j and n. As shown in FIG. 20, the thin film transistor j manufactured according to the fifth embodiment is superior to the thin film transistor n.

The description of some embodiments described above is merely for the purpose of explanation.

They cannot define the invention and many modifications or variations will be possible in light of the above teaching. Embodiments are selected to explain the principles and applications of the present invention, and those skilled in the art will be able to utilize the present invention more effectively using various embodiments and modifications.

For example, the non-single crystal semiconductor layer is formed by a chemical vacuum deposition method (CVD), a vacuum deposition method, an ion diagnostic beam method, an MBE method, a laser polishing method, or the like on a glass substrate. A high crystallinity polycrystalline semiconductor layer can be obtained from the non-single crystal semiconductor layer by the method of the present invention. In addition, the staggered, reverse staggered, reverse coplanar thin film transistors can be manufactured by the method of the present invention. The glass substrate may be heated in a CVD apparatus equipped with a heat engine instead of an electric furnace. In this case hydrogen is activated in the photo-CVD apparatus while being injected and heated to increase the cleanliness of the substrate surface.

In addition, a silicon nitride layer, a silicon carbide layer, a silicon oxide layer, a silicon nitride layer, or a multilayer containing some of the above-mentioned collisions may be supplied from the glass substrate as a blocking layer instead of the blocking layer used in the embodiment of the present invention. The preparation of such a blocking layer avoids the injection of alkali ions present in the glass substrate into the apparatus formed on the substrate.

In the above-described embodiment, the blocking layer is formed from the heated substrate. However, the semiconductor device of the present invention is manufactured by forming a blocking layer from a glass substrate following a glass substrate heating with a blocking layer.

In addition, EL-30 manufactured by HOYA, which contains SiO ₂ (60%), Al ₂ O ₃ (15%), B ₂ O ₃ (6%) and R ₂ O (2%), T-C-5 (TRC-5) manufactured by Ohara, which contains LE-30), SiO ₂ , Al ₂ O _3, and ZnO, and AN-NO manufactured by Nippon Electric Glass Co., Ltd. -2 may be used instead of non-alkali glass.

Claims (11)

Preparing a glass substrate, heating and shrinking the glass substrate, directly forming an insulating layer having silicon oxide on the shrunk glass substrate, forming an amorphous semiconductor layer on the insulating layer, and the semiconductor A method for manufacturing a semiconductor device, comprising the step of crystallizing a layer. Preparing a glass substrate, directly forming an insulating layer having silicon oxide on the glass substrate, heating and shrinking the glass substrate having the insulating layer formed thereon, the insulation formed on the shrunken glass substrate A method of manufacturing a semiconductor device, comprising forming an amorphous semiconductor layer on a layer, and crystallizing the semiconductor layer. Preparing a glass substrate, directly forming an insulating layer having silicon oxide on the glass substrate, and heating and shrinking the glass substrate having the insulating layer formed thereon in an inert atmosphere, on the contracted glass substrate Forming an amorphous semiconductor layer on the formed insulating layer, and crystallizing the semiconductor layer. The method of manufacturing a semiconductor device according to claim 3, wherein said inert atmosphere has nitrogen. The method of claim 3, wherein the inert atmosphere has carbon monoxide. The method of claim 3, wherein the inert atmosphere contains hydrogen. 4. A method according to claim 3, wherein the inert atmosphere has a mixture of nitrogen, carbon monoxide and hydrogen. The method of manufacturing a semiconductor device according to any one of claims 1 to 3, wherein the semiconductor device comprises an insulated gate field effect transistor having at least a channel semiconductor layer formed on the insulating layer. The method of manufacturing a semiconductor device according to claim 1, wherein the crystallization step is crystallized by heating. The method of claim 1, wherein the amorphous semiconductor layer has silicon. 4. The method of claim 3, wherein the semiconductor layer has silicon.