KR960008544A

KR960008544A - Method and apparatus for selecting multiple memory banks

Info

Publication number: KR960008544A
Application number: KR1019950024789A
Authority: KR
Inventors: 에드워드 부치 로버트; 필립 토미 안드레
Original assignee: 윌리엄 티. 엘리스; 인터내셔널 비지네스 머신즈 코포레이션
Priority date: 1994-08-12
Filing date: 1995-08-11
Publication date: 1996-03-22
Anticipated expiration: 2015-08-11
Also published as: US5530836A; KR0174631B1; TW256894B

Abstract

메모의 뱅크 선택 시스템은 두 개의 비동기 RAS 핀, 하나의 CAS핀 각 메모리 뱅크에 대한 스위칭 회로, 및 출력이 각 스위칭 회로로 향하는 뱅크 어드레스 디코더를 포함한다. RAS 핀은 모든 스위칭 회로에 사용가능하다. 주어진 스위칭 회로는 액티브인 RAS 핀은 모든 스위칭 회로에 사용가능하다. 주어진 스위칭 회로는 액티브인 RAS 신호가 존재하고 뱅크 어드레스 디코더 출력이 스위칭 회로로 전송되어진 경우에 자신에 연결된 뱅크를 선택한다. 동시에 액티브로 될 수 있는 메모리 뱅크의 수는 RAS 입력의 수에 직접적인 관계를 가진다. 다르게는, CAS 핀의 수는 비동기 RAS 핀의 수와 동일하다.The memo bank selection system includes two asynchronous RAS pins, one CAS pin switching circuit for each memory bank, and a bank address decoder whose output is directed to each switching circuit. The RAS pin is available for all switching circuits. Given a switching circuit, the active RAS pin can be used for any switching circuit. A given switching circuit selects the bank connected to it when there is an active RAS signal and the bank address decoder output is sent to the switching circuit. The number of memory banks that can be active at the same time is directly related to the number of RAS inputs. Alternatively, the number of CAS pins is equal to the number of asynchronous RAS pins.

Description

Method and apparatus for selecting multiple memory banks

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명에 의한 뱅크 선택 시스템의 간략화된 블록도.3 is a simplified block diagram of a bank selection system according to the present invention.

제4도는 제3도의 예시적인 뱅크 선택 시스템의 세부 사항을 도시하는 도면.4 shows details of the example bank selection system of FIG.

제5도는 제3도 및 제4도의 뱅크 선택 시스뎀에 대한 판독 동작의 타이밍 도.5 is a timing diagram of a read operation for the bank select system of FIGS. 3 and 4. FIG.

Claims

A plurality of memory banks; A plurality of asynchronous enable inputs to the plurality of memory banks; A decoder for decoding the bank address; And a plurality of switches responsive to the output of the decoder and the plurality of asynchronous enable inputs for selecting among the plurality of memory banks so that multiple memory banks are simultaneously selected, wherein the number of the plurality of memory banks is selected from the plurality of memory banks. Memory bank selection system, characterized by more than the number of asynchronous enable inputs.

2. The memory bank selection system of claim 1, wherein the plurality of memory banks comprises partitions of a memory module.

3. The memory bank selection system of claim 2, wherein the memory module comprises a DRAM memory module.

2. The method of claim 1, wherein the plurality of switches comprises a switch associated with each of the plurality of memory banks, the connection of each of the plurality of asynchronous enable inputs from each given memory bank of the connected switches. Memory bank selection system, characterized in that possible.

5. The memory bank selection system of claim 4, wherein the connected switch comprises a plurality of latches equal to the plurality of asynchronous enable inputs.

2. The memory bank selection system of claim 1 wherein the decoder comprises a binary decoder having a plurality of outputs of the same number as the plurality of memory banks.

A plurality of memory banks; A plurality of asynchronous bank enable inputs for the plurality of memory banks; One or more bank output enable inputs for the plurality of memory banks; A plurality of bank address inputs for addressing the plurality of memory banks; A decoder for decoding an addressing signal applied to the plurality of bank address inputs; And a plurality of switches responsive to an output signal from the decoder and a bank enable signal from the plurality of asynchronous bank enable inputs for selecting among the plurality of memory banks, wherein the number of the plurality of memory banks is selected from the plurality of memory banks. And wherein more than one memory bank can be selected simultaneously.

8. The memory bank selection system of claim 7, wherein the plurality of asynchronous bank enable inputs comprise a plurality of row address select inputs and the one or more bank output enable inputs comprise column address select inputs.

8. The memory bank selection system of claim 7, wherein the at least one bank output enable input is a single bank output enable input.

8. The memory bank selection system of claim 7, wherein the number of one or more bank output enable inputs is equal to the number of the plurality of asynchronous bank enable inputs.

A method of selecting from a greater number of memory banks than said plurality of asynchronous enable inputs in a system comprising a plurality of asynchronous enable inputs and a plurality of bank address inputs, the input of said plurality of asynchronous enable inputs. Applying an enable signal to the; Applying a bank address signal to the input; Applying a bank address signal to the plurality of bank address inputs; Decoding the applied bank address signal; And automatically selecting a first memory bank based on the applied enable signal and the decoded bank address signal.

12. The method of claim 11, wherein applying the bank address signal is performed in response to the applied enable signal.

12. The system of claim 11, wherein the system further comprises a plurality of switches coupled between the plurality of memory banks and the plurality of asynchronous enable signals, wherein the automatically selecting is one of the plurality of asynchronous enable inputs. And automatically making a connection between the first memory bank and the first memory bank.

12. The method of claim 11, further comprising: applying an enable signal to another input of the plurality of asynchronous enable inputs; Applying another bank address signal to the plurality of bank address inputs; Decoding the applied another bank address signal; And automatically selecting a second memory bank based on the enable signal and the decoded another bank address signal applied to another input of the plurality of asynchronous enable inputs, the first memory bank. And the second memory bank are simultaneously selected.

A plurality of asynchronous enable inputs for inputting a first type of memory bank select signal, one or more other enable inputs for inputting a second type of memory bank select signal, and a plurality of bank addresses for inputting a bank addressing signal A method of selecting from a plurality of a plurality of memory banks than the plurality of asynchronous enable inputs in a system comprising an input, the method comprising: (a) selecting the first type of memory bank to one input of the plurality of asynchronous enable inputs; Applying a signal; (b) applying a bank addressing signal to the plurality of bank address inputs; (c) applying the second type of memory bank select signal to the one or more other enable inputs; (d) decoding the applied bank addressing signal; (e) automatically selecting a memory bank based on the decoded bank addressing signal and the applied memory location addressing signal of the first type and the second type; And (f) repeating steps (a) to (e), wherein at least two memory banks are simultaneously selected from among the plurality of memory banks.

16. The method of claim 15, wherein said memory bank selection signal of said first type is a row access selection signal and said memory bank selection signal of said second type is a column access selection signal.

※ Note: The disclosure is based on the initial application.