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KR960008504B1 - Metal wire forming method of semiconductor device - Google Patents

Metal wire forming method of semiconductor device Download PDF

Info

Publication number
KR960008504B1
KR960008504B1 KR96008503A KR19960008503A KR960008504B1 KR 960008504 B1 KR960008504 B1 KR 960008504B1 KR 96008503 A KR96008503 A KR 96008503A KR 19960008503 A KR19960008503 A KR 19960008503A KR 960008504 B1 KR960008504 B1 KR 960008504B1
Authority
KR
South Korea
Prior art keywords
insulating layer
contact hole
photoresist
semiconductor device
forming method
Prior art date
Application number
KR96008503A
Other languages
Korean (ko)
Inventor
Ik-Soo Do
Original Assignee
Lg Semicon Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lg Semicon Co Ltd filed Critical Lg Semicon Co Ltd
Priority to KR96008503A priority Critical patent/KR960008504B1/en
Application granted granted Critical
Publication of KR960008504B1 publication Critical patent/KR960008504B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

forming a first photoresist which defines a contact hole connected to the electrical components on the semiconductor substrate (40); etching a first insulating layer (42) around the contact hole and removing the first photoresist layer; forming a second photoresist which defines a region where the contact hole and wiring are formed over the first insulating layer (42); removing the rest of the first insulating layer near the contact hole by using the second photoresist layer as mask, second etching of the first insulating layer around the region of wiring to the semiconductor substrate and removing of the second photoresist; depositing metal (49) and second insulating layer (51) on the top of the first insulating layer which includes the region of the contact hole and wiring; etchback of the second insulating layer (51) to reveal the metal (49) on the first insulating layer (42); etchback of the metal (49) to reveal the first insulating layer (42) by using the second insulating layer (51) in the contact hole as mask.
KR96008503A 1992-12-22 1996-03-27 Metal wire forming method of semiconductor device KR960008504B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR96008503A KR960008504B1 (en) 1992-12-22 1996-03-27 Metal wire forming method of semiconductor device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR920026012 1992-12-22
KR96008503A KR960008504B1 (en) 1992-12-22 1996-03-27 Metal wire forming method of semiconductor device

Publications (1)

Publication Number Publication Date
KR960008504B1 true KR960008504B1 (en) 1996-06-26

Family

ID=26629453

Family Applications (1)

Application Number Title Priority Date Filing Date
KR96008503A KR960008504B1 (en) 1992-12-22 1996-03-27 Metal wire forming method of semiconductor device

Country Status (1)

Country Link
KR (1) KR960008504B1 (en)

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Legal Events

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G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
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Payment date: 20120524

Year of fee payment: 17

EXPY Expiration of term