KR960008053B1 - Apparatus for synchronization of image signal and sound signal - Google Patents

Abstract

The apparatus is for synchronizing MPEG-Picture and MPEG-Voice while complying with the standard under the MPEG recommendation. The synchronization apparatus includes a data processing unit(1), a RAM(2), buffers(3,4), a STC counter(5), registers(6,7,8,9), comparators(10,11,12,13), a picture decoder(14), a voice decoder(15) and a decoder controller(20). The apparatus improves a system application capability by solving the synchronization problem such as a lack of lip sync.

Description

Synchronization device between video signal and audio signal

1 is a general block diagram showing an MPEG video and audio signal processing system, respectively.

2A is a timing diagram for decoding and displaying a video signal.

2B is a timing diagram of decoding and playing processing of a voice signal.

3 is a block diagram of a synchronization device according to an embodiment of the present invention.

4 is a block diagram of a synchronization device according to another embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

1: data processing unit 2: RAM

3,4, buffer 5: STC counter

6,7,8,9: registers 10,11,12,13: comparison unit

14: video decoder 15: voice decoder

20: decoder control unit

The present invention relates to a synchronization device between a video signal and an audio signal for synchronizing between a video signal processing system and an audio signal processing system in a device for decoding and processing compressed video and audio information signals.

Unlike general data, a vast amount of data signals are generated in digital representation of still and moving images having multidimensional characteristics.

Application fields for processing, storing, transmitting and displaying such digital video signals require relatively expensive equipment. However, thanks to the recent development of signal processing technologies such as image input devices, storage devices, and display devices, high-definition television, Application fields of digital video, such as multimedia computers, are widely spreading.

In addition, unlike the general data, the digitized video signal contains a considerable amount of redundancy information. Therefore, a video compression technology is being developed at various angles. Compression technology has been largely developed into the compression method for video telephony and storage media. MPEG (Moving Picture Experts Group) was established in May 1988. Standardization work is underway.

MPEG deals with not only the above-mentioned image compression but also related audio signal compression, synchronization of audio and video signals. In other words, MPEG is composed of MPEG video, MPEG audio, and MPEG system. MPEG-Video deals with the compression of video signals of approximately 1.2 Mbits / s, and MPEG-Audio deals with the compression of digital audio signals with transmission rates of 64, 128 and 192 Kbits / s per channel. The MPEG-system also addresses the problem of multiplexing and synchronizing multiple compressed audio and video signals.

The MPEG video and audio processing system generally processes compressed video and audio signals using respective decoders 22 and 25 and buffers 21 and 24 as schematically shown in FIG. In order to extend the video signal, the decoder operates in accordance with an externally generated synchronization signal Vsync to comply with the timing relationship as shown in FIG.

That is, in the processing of the video signal, the MPEG-video signal input as shown in FIG. 2 (a) is decoded and displayed in accordance with the synchronization signal having a predetermined time interval, and in the processing of the audio signal in FIG. Decode and play at a separate timing as shown in the timing chart. In MPEG video, the transmission order (decoding order) is different from the display order because of the bidirectional predictive frame (B picture). Namely, IO B1 B2 P3 B4 B5... When a display sequence such as is transmitted (when decoded) IO P3 B1 B2 P6 B4 B5... Will be in order.

This is as shown in Fig. 2 (a). After decoding, the frames need to be rearranged in the display order. Thus, the buffer rearrangement buffer 23 is shown in FIG. As shown in FIG. 2 (a), due to the frame rearrangement, the first frame is decoded and displayed after the time delay of two image frames, except for the delay shown in the initial drawing.

On the other hand, as shown in Fig. 2 (b), in the MPEG audio, in addition to the delay at the initial startup, the first frame is played after the delay of one audio frame after decoding.

In this way, if the video system and the audio system are completely operated separately, the lip sync is not matched. Therefore, special consideration is needed to synchronize the two systems. To this end, MPEG introduces a time stamp concept to achieve a synchronization problem. However, MPEG does not adopt a specific circuit configuration, but is a standard that stipulates that it is relatively effective among many methods, and only for synchronization, STC (System Time Clock) or DTS (Decoding Time Stapm) is used for synchronization. And PTS (hereinafter referred to as PTS).

An object of the present invention is to provide a synchronization device that conforms to the standard within the scope of the MPEG recommendation described above, and specifically synchronizes MPEG video and MPEG audio.

According to an aspect of the present invention for achieving the above object, by inputting the data signal of the multiplexed bitstream and demultiplexed through the signal processing means and then delivered to the video decoder and the audio decoder through the respective buffer, And a video signal and an audio signal for synchronizing and displaying an audio signal, wherein the signal processing means comprises: a system time clock reference included in the data signal by demultiplexing a data signal of the multiplexed bitstream; And extracting a plurality of time stamps, video signals, and audio signals, and storing and restoring the system tie clock reference and the plurality of time stamps extracted therefrom, and outputting the extracted video and audio signals. Number of data detection and storage for outputting to the video decoder 14 and the audio decoder 15 through And; Decoding time for controlling the start of decoding and displaying (or playing) operations on the buffered video and audio signals based on an interrupt signal generated by a comparison between a system time clock reference of the data detection and storage means and a plurality of time stamps. Provided is a synchronization device between a video signal and an audio signal, characterized by having a control means.

In addition, the data detection and storage means employed in the synchronization device between the video signal and the audio signal of the above configuration according to the present invention, the system time clock reference included in the data signal by demultiplexing the data signal of the multiplexed bitstream And a data processor 1 for extracting a plurality of time stamps, video signals, and audio signals, and a RAM for temporarily storing and restoring the extracted system time clock criteria and a plurality of time stamps by the data processor 1 ( 2), and the RAM 2 includes an area for storing four values of DTS-V, DTS-A, PTS-V, and PTS-A as a plurality of time stamps extracted by the data processing unit 1. .

Furthermore, the decoding time control means included in the synchronization device of the present invention having the above-described configuration includes an STC counter 5 for providing a reference time by inputting a system clock from the data processing unit 1, and a data processing unit 1; Registers 6, 7, 8, and 9 for temporarily storing and outputting a plurality of time stamps from < RTI ID = 0.0 >) and < / RTI > A comparison unit (10, 11, 12, 13) for generating and outputting an interrupt signal corresponding to the plurality of time stamps provided from (8, 9), respectively, at a matching time point, and the comparison unit (10, 11) And a decoding start signal for starting the video and audio signals of the video decoder 14 and the audio decoder 15 and a display (or play) operation in response to the interrupt signals 12 and 13; Display (or play) A decoder control unit 20 to provide a signal.

According to another aspect of the present invention for achieving the above object, by inputting the data signal of the multiplexed bitstream and demultiplexed through the signal processing means and then delivered to the video decoder and the audio decoder through the respective buffer, And a video signal and an audio signal for synchronizing and displaying an audio signal, wherein the signal processing means comprises: a system time clock reference included in the data signal by demultiplexing a data signal of the multiplexed bitstream; A plurality of time stamps, video signals, and audio signals are extracted, and the system time clock reference and the plurality of time stamps extracted therefrom are temporarily stored, restored, and output. 4) data detection and storage for output to the video decoder 14 and the audio decoder 15 through However, decoding and displaying (or playing) the buffered video and audio signals are simultaneously performed based on a strobe signal generated based on a comparison between a system time clock reference of the data detection and storage means and a plurality of time stamps. And a decoder control means for outputting a decoding start signal and a display (or play) start signal to the video decoder 14 and the audio decoder 15 so that the video signal and the audio signal can be synchronized. do.

In addition, the data detection and storage means employed in the synchronization device between the video signal and the audio signal according to the present invention is a system tie clock reference included in the data signal by demultiplexing the multiplexed bisstream data signal. And a data processing unit 1 for extracting a plurality of time stamps, and a RAM 2 for temporarily storing and storing the system time clock reference extracted by the data processing unit 1 and a plurality of time stamps. The RAM 2 in the data detection and storage means includes an area for storing four values of DTS-V, DTS-A, PTS-V, and PTS-A as a plurality of time stamps extracted by the data processing unit 1. do.

Further, the decoder control means included in the synchronization device of the present invention having the above-described configuration includes an STC counter 5 which provides a reference time by inputting a system clock from the data processor 1, and a data processor 1; Registers 6, 7, 8, and 9 for temporarily storing and outputting a plurality of timestamps from the registers; and the registers 6, 7, and 8 with reference to the reference time according to the system time clock reference of the STC counter 5. And compare the plurality of time stamps provided from (9) with each other and perform decoder and display (or play) operations of the video decoder 14 and the audio decoder 15 on the basis of the corresponding strobe signal. Comparator 10, 11, 12, 13 to perform.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

3 is a synchronization device diagram according to an embodiment of the present invention, Figure 4 is a synchronization device diagram according to another embodiment of the present invention.

Referring to FIG. 3, a synchronization device according to an embodiment of the present invention includes a data processor 1, a RAM 2, a buffer 3, 4, an STC counter 5, and a register 6, 7, 8. And 9), a comparator 10, 11, 12, 13, an image decoder 14, an audio decoder 15, and a decoder controller 20.

The data processor 1 demultiplexes the data signal of the multiplexed bitstream to extract a system time clock criterion and a plurality of time stamps included in the data signal, and the extracted system time clock criterion is an STC counter 5. And the extracted plurality of timestamps are provided to the RAM 2 and the registers 6, 7, 8, and 9 described later. The video signal extracted by demultiplexing the data signal of the multiplexed bitstream is provided to a buffer 3 to be described later, and the audio signal extracted by the demultiplexed is provided to a buffer 4 to be described later. do.

The buffers 3 and 4 buffer the video and audio signals extracted and input from the data processing unit 1, and then output the video signals to the video decoder 14, which will be described later. Output to! 5).

The STC counter 5 is configured to temporarily store PTS-V data among a plurality of time stamps provided from the data processing unit 1 and to provide one side terminal of the comparators 10, 11, 12, and 13 described later. The STC counter 5 consists of a 33-bit counter.

The register 6 is configured to temporarily store PTS-V data among a plurality of time stamps provided from the data processing unit 1 and to provide it to the other terminal of the comparison unit 10 described later. The register 7 is a data processing unit ( The PTS-A data is temporarily stored in the plurality of time stamps provided from 1) and then provided to the other terminal of the comparison section 11 described later.

The register 8 is configured to temporarily store DTS-V data among a plurality of time stamps provided from the data processing unit 1, and to provide it to the other terminal of the comparison unit 12 described later. The register 9 is a data processing unit ( The DTS-A data is temporarily stored in the plurality of time stamps provided from 1) and provided to the other terminal of the comparison section 13 described later.

The comparator 10 generates an interrupt signal IRQ1 at a time point that matches the reference time provided from the STC counter 5 and the PTS-V data provided from the register 6 and generates a decoder control unit 20 to be described later. Is configured to provide

The comparator 11 generates an interrupt signal IRQ2 at a point of time when the comparison time between the reference time provided from the STC counter 5 and the PTS-A data provided from the register 7 matches, and thus the decoder controller 20 described later. Is configured to provide

The comparator 12 generates an interrupt signal IRQ3 at a time point that matches the reference time provided from the STC counter 5 with the DTS-V data provided from the register 8, and the decoder controller 20 described later. Is configured to provide

The comparator 13 generates an interrupt signal IRQ4 at a point of time when a comparison result between the reference time provided from the STC counter 5 and the DTS-A data provided from the register 9 matches and the decoder controller 20 described later. Is configured to provide

The decoder controller 20 provides a display start signal to the video decoder 14 at the time when the interrupt signal IRQ1 is applied from the comparator 10 to output the video signal decoded from the following description to the TV system. And providing a play start signal to the audio decoder 15 at the time when the interrupt signal IRQ2 is applied from the comparator 11, thereby outputting the audio signal decoded from the following description to the amplifier.

In addition, the decoder controller 20 decodes a video signal provided from the buffer 3 by providing a display start signal to the video decoder 14 at the time when the interrupt signal IRQ3 is applied from the comparator 12. When the interrupt signal IRQ4 is applied from the comparator 13, the decoding start signal is provided to the voice decoder 15 to decode the voice signal provided from the buffer 4.

Referring to FIG. 4, a synchronization device according to another embodiment of the present invention will be described as being included in the repeated components of FIG. 3. That is, the data processor 1, the RAM 2, the STC counter 5, the registers 6, 7, 8, 9, the comparators 10, 11, 12, 13, the video decoder 14, and the audio. And a decoder 15.

The data processor 1 demultiplexes the data signal of the multiplexed bitstream to extract a system time clock criterion and a plurality of time stamps included in the data signal, and the extracted system time clock criterion is an STC counter 5. And the extracted plurality of timestamps are provided to the RAM 2 and the registers 6, 7, 8, and 9 described later. The video signal extracted by demultiplexing the data signal of the multiplexed bitstream is provided to a video decoder 14 to be described later through the buffer 3, and the audio signal extracted by the demultiplexing is also buffered ( 4) to be provided to the voice decoder 15 to be described later.

The STC counter 5 is configured to be provided as one side terminal of the comparators 10, 11, 12, and 13 which describe the reference time obtained by countering the system clock input from the data processor 1, and the STC counter 5 ) Consists of a 33-bit counter.

The register 6 is configured to temporarily store PTS-V data among a plurality of time stamps provided from the data processing unit 1 and to provide it to the other terminal of the comparison unit 11 described later. The register 7 is a data processing unit ( The PTS-A data is temporarily stored in the plurality of time stamps provided from 1) and then provided to the other terminal of the comparison section 13 described later.

The register 8 is configured to temporarily store DTS-V data of a video signal among a plurality of time stamps provided from the data processing unit 1, and to provide it to the other terminal of the comparison unit 10 described later. The DTS-A data is temporarily stored in the plurality of time stamps provided from the data processing unit 1 and then provided to the other terminal of the comparison unit 12 described later.

The comparator 10 generates a strobe signal at a point in time at which the reference time provided from the STC counter 5 and the DTS-V data provided from the register 8 coincide, and provides the image signal to the image decoder 14 described later. Is configured to.

The comparator 11 generates a strobe signal at a point in time at which the reference time provided from the STC counter 5 matches with the PTS-A data provided from the register 6, and provides the strobe signal to the image decoder 14 described later. Is configured to.

The comparator 12 generates a strobe signal at a point of time when the reference time provided from the STC counter 5 matches with the DTS-A data provided from the register 9, and provides the strobe signal to the voice decoder 15 described later. Is configured to.

The comparator 13 generates a strobe signal at the point of time when the comparison time between the reference time provided from the STC counter 5 and the PTS-A data provided from the register 7 matches and provides the voice decoder 15 to be described later. Is configured to.

Hereinafter, with reference to the illustrated drawings will be described a preferred embodiment according to the present invention.

First embodiment

The basic principle of MPEG-system synchronization in accordance with MPEG-systems is that the decoder uses a single 90KHz system clock and uses a timestamp that defines the time to receive encoded and multiplexed data and the decoding glyph display of video and audio. The apparatus of the present invention, shown in Figures 3 and 4, also receives the aforementioned multiplexed bitstream input signal.

The video decoder of the present invention shown in FIGS. 3 and 4 includes a frame rearrangement buffer (RAM), and the audio decoder also includes a voice frame buffer (RAM) for play delay.

Since the multiplexed input signal is a video signal and an audio signal mixed, the multiplexed input signal is demultiplexed by the data processor 1 to be processed into a separate signal.

In addition, while performing demultiplexing, the SCR, DTS, and PTS included in the input signal are detected to be used in subsequent signal processing. The demultiplexing and timing signal included in the input signal can be detected by the design of the demultiplexing means and the timing signal detecting means. In this embodiment, however, the apparatus is controlled by a program as shown in FIG. do.

The data processor 1 includes a RAM 2 which is a storage device for temporarily storing data to be processed, and the fraudulent data processor 1 that receives the input data by the internal input / output means includes a timing signal included in the input data. And extract the extracted video and audio signals into respective buffers 3 and 4.

The data processor 1 temporarily stores the timing signal in RAM 2, which is a storage device connected thereto, and temporarily stores the timing signal in the plurality of registers 6, 7, 8, 9 or STC counter 5 under suitable conditions. send.

Of the extracted timing signals, the SCR is transmitted to the STC counter 5 connected to the data processor 1. The STC is a system time clock of 90 KHz according to the MPEG standard and provides the system's reference timing.

The data processor 1 reads the first DTS and PTS for the video and audio signals, and writes them to the PTS-V, PTS-A, DTS-V, and DTS-A registers 6, 7, 8, and 9, respectively. Save it.

The RAM 2 always retains four storage spaces to have current PTS and DTS values by the data processing section 1, and these values are transferred to the respective registers 6, 7, 8, 9.

At this time, the transmission time is processed by the interrupt signal generated when the contents of the STC counter 5 and the contents of each register 6, 7, 8, 9 coincide with each other, and then the PTS and DTS are required. Increment by to transfer to the register (6, 7, 8, 9).

Comparators 10, 11, 12, 13 for comparing the contents of the SCR counter 5 with the values of the respective registers 6, 7, 8, and 9 as shown in FIG. ), And each of the comparators 10, 11, 12, and 13 generates an interrupt signal IRQ1 to IRQ4 corresponding to the timing point at which the two timing signals coincide with each other, and provides it to the decoder controller 20.

That is, the moment the DTS matches the STC, that is, at the start of decoding, the decoder controller 20 receives the interrupt signal IRQ1 from the comparator 10 and operates the interrupt service program accordingly. Accordingly, the image decoder 14 performs a decoding operation on the image signal provided from the buffer 3 based on the decoding start signal provided from the decoder controller 20. In addition, the decoder controller 20 receives the interrupt signal IRQ2 from the comparator 11 and operates the interrupt service program accordingly, and the voice decoder 15 receives the decoding start signal provided from the decoder controller 20. On the basis of this, the decoding operation is performed on the audio signal provided from the buffer 4.

Subsequently, when the contents of the PTS and the STC coincide with each other, the decoder controller 20 receives the interrupt signal IRQ3 from the comparator 12 and operates the interrupt service program accordingly. The video decoder 14 performs a display operation on the decoded video signal based on the display start signal provided from the decoder controller 20.

In addition, the decoder controller 20 receives the interrupt signal IRQ4 from the comparator 13 and operates the interrupt service program accordingly. The voice decoder 15 performs a play operation on the decoded voice signal based on the play start signal provided from the decoder controller 20.

Accordingly, the video and audio decoders 14 and 15 output the decoded video and audio signals to the TV system and the amplifier.

(A) and (b) in FIG. 2 show the timing relationship to be decoded and displayed in accordance with an externally generated synchronization signal in the conventional case, but the timing relationship is similar in this embodiment as well.

According to the GOP (Group Of Picture) structure shown in MPEG, the transmission frame is IBBPBBPBBIB... Has a pattern. Intra-picture removes only spatial direction redundancy by applying discrete cosine transform and quantization process for each block partitioning the frame image, and P-picture (predictive-picture) uses forward inter-picture prediction coding and discrete cosine. Data is compressed using the transform method, and B-picture (Bidirectional-picture) is data compressed using the bidirectional inter-prediction encoding and discrete cosine transform methods.

In the timing diagram, the timing of synchronizing is generated according to the frame interval in the case of FIG. 2 (a). At this time, for example, I0, P3, B1, B2, P6... In this timing relationship, the timing of generating the synchronization signal corresponds to the generation of the interrupt signal IRQ3, and the timing of the display corresponds to the interrupt signal IRQ1. As described above, the point of occurrence of the interrupt signal is caused by the output of the comparator, and it is controlled by the STC counter 5.

This is to control the synchronization signal interval. For this purpose, the data processor 1 reads the information on the frame rate from the input bitstream, calculates the increment of the timestamp, and has this value. Used to control the spacing.

Also in the case of an audio signal, the timing relationship in FIG. 2 (b) corresponds to the interrupt signals IRQ4 and IRQ2, respectively.

Although the operation is controlled at the time of the occurrence of the interrupt and the interrupt processing cannot be performed at the same time, the data processing unit 1 simply applies the control signal to the corresponding signal processing block at the time of the interruption, thereby enabling synchronization matching.

The second embodiment of FIG. 4 is configured such that the outputs of the plurality of comparators 10-13 are directly applied to the video decoder 14 and the audio decoder 15. FIG.

According to this embodiment, when the outputs of the plurality of comparators 10-13 appear simultaneously, that is, for the simultaneous processing (decoding processing) of the video signal and the audio signal, the outputs of the comparator! 0 and the comparator 12 As a result, the video decoder 14 and the audio decoder 15 perform decoding operations on the buffered video and audio signals. In other words, the outputs of the comparators 10, 11, 12, 13 act as a sprobe signal to the decoder, thereby achieving simultaneous operation, that is, synchronous matching.

Similarly, the outputs of the comparators 11 and 13 can be synchronized as control signals for video display and audio play.

As described above, since the conventional digital video signal processing system and the audio signal processing system were separately studied, there was a problem in utilizing the system because there was no consideration of synchronization between the two systems, that is, lip sync. As in the present invention, the system adaptability is improved by solving the synchronization problem with a simple configuration.

Claims (8)

The data signals of the multiplexed bitstreams are input, demultiplexed through signal processing means, and then transmitted to the video decoder and the audio decoder through respective buffers, so that the video signal and the audio signal are synchronized and displayed. In the synchronization device, the signal processing means demultiplexes the data signal of the multiplexed bitstream to extract a system time clock reference included in the data signal, a plurality of time stamps, video signals, and audio signals. The system tie clock reference and the plurality of time stamps extracted therefrom are temporarily stored and restored, and the extracted video and audio signals are outputted through the buffers 3 and 4 through the buffers 3 and 4. Data detection and storage means for outputting to the decoder 15; Decoding time for controlling the start of decoding and displaying (or playing) operations on the buffered video and audio signals based on an interrupt signal generated by a comparison between a system time clock reference of the data detection and storage means and a plurality of time stamps. Synchronization device between the video signal and the audio signal characterized in that it comprises a control means. The data detection and storage unit of claim 1, wherein the data detection and storage unit is configured to demultiplex the data signal of the multiplexed bitstream to obtain a system time clock reference included in the data signal, a plurality of time stamps, a video signal, and an audio signal. A data processor 1 for extracting; And a RAM (2) for temporarily storing and restoring the system time clock reference and a plurality of time stamps extracted by the data processor (1). 3. The RAM 2 according to claim 2, wherein the RAM 2 stores a region for storing four values of DTS-V, DTS-A, PTS-V, and PTS-A as a plurality of time stamps extracted by the data processing unit 1. Synchronizing device between the video signal and the audio signal comprising a. 4. The apparatus according to any one of claims 1 to 3, further comprising: an STC counter (5) for providing a reference time by inputting said decoding time control means and a system clock from said data processor (1); Registers (6,7,8,9) for temporarily storing and outputting a plurality of time stamps from the data processing section (1); Interrupt signals corresponding to the time points provided from the registers 6, 7, 8, and 9 with reference to the reference time according to the system time clock reference of the STC counter 5, respectively, A comparator (10, 11, 12, 13) for outputting in response to the response; In response to the interrupt signals of the comparators 10, 11, 12, and 13, the decoding operation and the display (or play) operation of the video and audio signals of the video decoder 14 and the audio decoder 15 are started. And a decoder controller (20) for providing a decoding start signal and a display (or play) start signal for performing the video signal and the audio signal. The data signals of the multiplexed bitstreams are input, demultiplexed through signal processing means, and then transmitted to the video decoder and the audio decoder through respective buffers, so that the video signal and the audio signal are synchronized and displayed. In the synchronization device, the signal processing means demultiplexes the data signal of the multiplexed bitstream to extract a system time clock reference included in the data signal, a plurality of time stamps, video signals, and audio signals, The system time clock reference and the plurality of time stamps extracted therefrom are temporarily stored, restored, and output, and the extracted video and audio signals are output through the video decoder 14 and the audio decoder through the buffers 3 and 4. Data detecting and storing means for outputting to the 15); The decoding and display (or play) operation of the buffered video and audio signals may be simultaneously performed based on a strobe signal generated based on a comparison between a system time clock reference of the data detection and storage means and a plurality of time stamps. And decoder control means for outputting a decoding start signal and a display (or play) start signal to the video decoder (14) and the audio decoder (15), respectively. 6. The data processor (1) according to claim 5, wherein said data detection and storage means and said data processing unit (1) demultiplex the data signal of said multiplexed bitstream to extract a system tie clock reference and a plurality of time stamps included in the data signal. Wow ; And a RAM (2) for temporarily storing and restoring the system time clock reference and a plurality of time stamps extracted by the data processor (1). 7. The RAM 2 according to claim 6, wherein the RAM 2 stores a region for storing four values of DTS-V, DTS-A, PTS-V, and PTS-A as a plurality of time stamps extracted by the data processing unit 1. Synchronizing device between the video signal and the audio signal comprising a. 8. The decoder according to any one of claims 5 to 7, wherein the decoder control means comprises: an STC counter (5) which provides a reference time by inputting a system clock from the data processing section (1); Registers (6,7,8,9) for temporarily storing and outputting a plurality of time stamps from the data processing section (1); By comparing the time stamps provided from the registers 6, 7, 8, and 9 with reference to the reference time according to the system time clock reference of the STC counter 5, the corresponding strobe signals are matched at the corresponding time points. And a comparator (10, 11, 12, 13) for applying to the video decoder 14 and the audio decoder 15 to perform the decoding and display (or play) operation for the video and audio signals Synchronizing device between the video signal and the audio signal characterized in that.