KR960006998Y1 - Nonvolatile semiconductor memory - Google Patents

Abstract

none.

Description

Nonvolatile Semiconductor Memory

1 is a block diagram showing a schematic circuit configuration of a nonvolatile semiconductor memory according to the present invention.

2 is a circuit diagram showing the circuit of the above embodiment in detail.

FIG. 3 is a circuit diagram showing in detail some circuits of the circuit shown in FIG.

4 is a characteristic diagram for explaining the circuit of FIG.

5 is a timing chart for explaining the operation of the circuit according to the above embodiment.

6 is a circuit diagram showing a schematic configuration of a conventional nonvolatile semiconductor memory.

7 is a timing chart for explaining the conventional circuit.

* Explanation of symbols for main parts of the drawings

10: first memory array 11, 14: memory cell array

12, 15: dummy cell array 13: second memory array

16, 18: row decoder 17: column decoder

19: sense amplifier 20: intermediate potential generating circuit

21: memory cell 22: bit line

23: word line 24: dummy cell

25: discharge transistor 26: column select transistor

27 transistor for level down 28 transistor for precharge

31, 32: NOR gate 33: flip-flop

34, 35, 36: NAND gate

[Industrial use]

The present invention relates to a nonvolatile semiconductor memory using a nonvolatile element such as a floating gate transistor as a memory cell.

[Traditional Technology and Problems]

6 is a circuit diagram showing a schematic configuration of a conventional nonvolatile semiconductor memory using a floating gate transistor as a memory cell. Here, for the sake of simplicity, a recording circuit or the like for recording data is omitted.

In the figure, reference numeral 51 denotes a memory cell consisting of a floating gate transistor.

The drain of this memory cell 51 is connected to the bit line 52, and the control gate is connected to the word line 54 to which the decode signal from the row decoder 53 to which the row address is input is supplied.

In addition, a discharge transistor 55 in which conduction is controlled by a nematode control signal Pr is inserted between the source of the memory cell 51 and the ground potential Vss.

A column select transistor 56 is inserted between the bit line 52 and the node A. The decode signal from the column decoder 57 into which the open dress is input is inserted into the gate of the transistor 56. Supplied. The level-down transistor 58 is inserted between the node A and the node B. As shown in FIG. The gate of this transistor 58 is supplied with an intermediate potential V _DD between the power supply potential Vcc and the ground potential Vss output from the intermediate potential generating circuit 59.

In addition, a precharge transistor 60 is inserted between the node B and the power supply potential Vcc in which conduction is controlled by the precharge control signal Pr. The potential of the node B is connected to one input terminal of the sense amplifier 63 that forms a flip-flop by cross-connecting the input / output terminals of the two NOR gates 61 and 62. The sense amplifier 63 detects the stored data of the memory cell 51 by comparing the potential of the node B supplied to one input terminal with the comparison potential V _ref supplied to the other input terminal, thereby reading the read data ( Dout).

The comparison potential V _ref used when detecting data by the sense amplifier 63 is formed by the comparison potential generating circuit 70 configured like the main memory cell axis. In this comparative potential generation circuit 70, between the power supply potential Vcc and the ground potential Vss, the transistor 71 which is equivalent to the transistor 60 and the transistor 72 which is equivalent to the transistor 58 are provided. The transistor 73 equivalent to the transistor 56, the floating gate transistor 74, and the transistor 75 equivalent to the transistor 55 are connected in series. In this case, the floating gate transistor 74 is used as a dummy cell, and the size of the channel length and the channel width is set to about 1/2 of the memory cell 51.

The comparison potential V _ref is obtained at the node C to which the transistors 71 and 72 are connected. In addition, the precharge control signal Pr is output to the gates of the transistors 71 and 75, and the gate of the transistor 72 is output from the intermediate potential generating circuit 59 to make the same condition as the main body memory cell side. The intermediate potential V _DD is supplied with the power source potential Vcc to the gate of the transistor 73, respectively.

In addition, writing is not performed on the transistor 74 used as the dummy cell, and electrons are not injected into the floating gate.

Next, the operation of the memory constituting the above configuration will be described using the timing chart of FIG. first. When the nematode control signal Pr becomes L level prior to reading from the memory cell 51, the precharge transistor 60 is turned on at the main memory cell side, and the node B is precharged to H level, that is, Vcc level. do.

At this time, since the intermediate potential V _DD lower than the power potential Vcc output from the intermediate potential generating circuit 59 is supplied to the gate of the level-down transistor 58, the power supply potential Vcc is supplied to the node A. Lower potential is given. Next, the precharge control signal Pr becomes H level, and the discharge transistor 55 is turned on. Further, one memory cell 51 is selected in correspondence with the row address and the open address. At this time, when data is written to the selected memory cell 51 and electrons are injected into the floating gate, the memory cell 51 remains non-conducting and the potential of the bit line 52 and the node A are lost. The potential of does not change with the state of precharge.

Therefore, the potential of the node B also does not change while being in the precharge state as indicated by the dotted line in FIG. On the other hand, when data is not written to the selected memory cell 51 and no electrons are injected into the floating gate, the memory cell 51 is turned on so that the potential of the bit line 52 and the potential of the node A are turned on. Are respectively discharged to ground potential (Vss). Therefore, the potential V _ref of the node B is also discharged to the ground potential Vss as shown by the solid line in FIG.

On the other hand, in the comparison potential generating circuit 70, when the precharge control signal Pr is at the L level, the transistor 71 is turned on, and the node C is precharged to the H level. After that, when the nematode control signal Pr becomes H level, the transistor 75 is turned on. At this time, the transistor 74 is also turned on in response to the row address, and the potential of the node C is discharged to the ground potential Vss.

At this time, since the ratio of the channel length and the channel width of the transistor 74 is set to about 1/2 of the memory cell 51, the time until the potential of the node C decreases to Vss When the memory cell 51 in which no writing is performed is selected, the potential of the node B becomes longer than the time until the potential Vss is lowered. Here, the sense amplifier 63 detects data by comparing the potentials of both nodes B and C to determine the level of the output Dout.

In the conventional memory, however, the parasitic capacitance present in the bit line to which the drain of the memory cell is connected is very large compared to the parasitic capacitance present in the corresponding node in the comparison potential generating circuit.

As the memory capacity increases, the capacity difference gradually increases, and even when precharging and discharging are performed at the same timing on the memory cell side and the dummy cell side, the potential number of the node B tends to be delayed compared to the potential change of Vref. .

When the potential change of the node B is about the same as the potential change of Vref, for example, as indicated by the dashed-dotted line in FIG. 7, the sense amplifier may not be flip-floped correctly and wrong data may be detected.

[Purpose of designation]

The present invention has been made in view of the above, and in a nonvolatile semiconductor memory which performs data charging from a nonvolatile memory cell by performing precharge and discharge, the data detection means always detects data correctly regardless of the memory cell capacity. It is an object of the present invention to provide a nonvolatile semiconductor memory.

[Composition of design]

A nonvolatile semiconductor memory according to the present invention for achieving the above object has a plurality of first bit lines, a plurality of first nonvolatile memory cells and at least one nonvolatile dummy cell connected to the plurality of first bit lines. A first precharge-discharge type memory circuit, a plurality of second bit lines, a plurality of second nonvolatile memory cells, and at least one nonvolatile dummy cell connected to the plurality of second bit lines of the first memory circuit Second precharge-discharge type memory circuit

One of the plurality of first nonvolatile memory cells of the first memory circuit along one of the at least one dummy cell of the second memory circuit, or one of the at least one dummy cell of the first memory circuit Cell selection means for selecting one of the plurality of second memory cells;

The potentials output from the first or second memory circuits including the memory cells selected according to the potentials output from the first or second memory circuits including the dummy cells selected by the cell selecting means are compared to the selected memory cells. Data detecting means for detecting stored data.

A plurality of bit line selection transistors included in the cell selecting means, each of which is connected to the bit lines of each memory circuit at a first stage so as to form a node of a memory cell, and interconnected at a second stage of each memory circuit; And a column decoder for selecting and driving one of the bit line selection transistors according to a signal.

A plurality of level shifting transistors connected to a node of a second stage of the plurality of bit line selection transistors for each memory circuit in a first stage, and a second stage of each of the plurality of level shifting transistors in a first stage respectively; It is characterized by comprising a plurality of precharged transistors connected.

In addition, in the nonvolatile semiconductor memory of the present invention, the data detection means is initially set in the precharge period of the first and second memory arrays, and the memory cell and the dummy cell are selected by the selection means in the discharge period. And a CMOS flip-flop circuit for comparing the read potential from

In addition, the nonvolatile semiconductor memory of the present invention is characterized in that the geometric size of the dummy cells in the first and second memory arrays is set differently from that of the memory cells.

(Action)

In the present invention configured as described above, the memory cells are divided into two of the first and second memory arrays, dummy cells are provided for each memory array, and connected to the same bit lines as the memory cells. When one of the memory cells of the first and second memory arrays is selected, the other dummy cell is selected to enable data detection in the data detection means.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram showing a schematic circuit configuration of a nonvolatile semiconductor memory according to the present invention. In the circuit of this embodiment, a recording circuit for recording data and the like is omitted for simplicity of explanation.

In the figure, reference numeral 10 denotes a memory cell array 11 in which a plurality of nonvolatile memory cells (not shown) are arranged in a matrix form, and one memory cell array 11 corresponding to each memory cell row of the memory cell array 11. A first memory array including dummy cell rows 12 in which dummy cells are arranged. 13 denotes a memory cell array 14 in which a plurality of nonvolatile memory cells are arranged in a matrix like the first memory array 10 and one memory cell row corresponding to each memory cell row of the memory cell array 14. A second memory array including dummy cell arrays 15 in which dummy cells are arranged.

The memory cells in the memory cell array 11 of the first memory array 10 are m-bit complementary row addresses [(ADR) 0. (ADR) 0 to (ADR) m-1. (ADR) m-1] and the row address 16 of the most significant bit [(ADR) m] and the row address [(ADC) 0. (ADC) 0 to (ADC) n. (ADC) n] is selected corresponding to each of the record outputs of the column decoder 17 to be supplied.

In addition, the memory cells in the memory cell array 14 of the second memory array 13 are m-bit complementary row addresses [(ADR) 0. (ADR) 0 to (ADR) m-1. (ADR) m-1] and the row address [(ADR) m] of the most significant bit are selected corresponding to the decode outputs of the row decoder 18 and the column decoder 17, respectively.

The row decoders 16 and 18 operate only when the most significant bit [(ADR) m or (ADR) m] of the row address is activated, and memory cells arranged in the same column in the corresponding memory cell arrays 11 and 14. The selection of the columns is performed via word lines not shown. The most significant bits [(ADR) and (ADR) m] of the row address are also supplied to the dummy cell array 12 in the first memory array 10 and the dummy cell array 15 in the second memory array 13. It is.

When both addresses are activated, all the dummy cells in the corresponding dummy cell columns 12 and 15 are simultaneously selected.

Selected corresponding to each decoded output of the memory cell, row decoder 18 and column decoder 17 of the memory cell array 11 selected corresponding to the decoded output of the row decoder 16 and column decoder 17. The potential according to the stored data of the memory cell of the memory cell array 14 and the potential according to the stored data of the dummy cell in the dummy cell array 12 or 15 are supplied to the sense amplifier 19. The sense amplifiers 19 are also supplied with the most significant bits [(ADR) m and (ADR) m] of the row address, and the sense amplifiers 19 correspond to the addresses so that the first memory array 1 and the second memory array are provided. The read potential from one memory cell and the read potential from the other dummy cell are selected in (13), and data is detected and output as Dout by comparing the selected potentials.

2 is a circuit diagram showing the circuit of the above embodiment in detail.

In this detailed circuit diagram, in addition to the first memory array 10, the second memory array 13, the row decoders 16 and 18, the column decoder 17 and the sense amplifier 19, a power supply potential Vcc and a ground potential ( The intermediate potential generating circuit 20 which generates the intermediate potential V _DD between Vss) and the peripheral circuit of the memory cell array are shown.

In the memory cell array 11 of the first memory array 10, a plurality of memory cells 21 each consisting of N-channel floating gate transistors are provided.

The drains of these memory cells 21 are commonly connected to the plurality of bit lines 22 on a row basis, and the source is commonly connected on a row basis. The control gates of the plurality of memory cells 21 are commonly connected to the plurality of word lines 23 in units of columns.

The decode signals output from the row decoder 16 are supplied to the plurality of word lines 23. In the dummy cell array 12 of the first memory array 10, similarly to the memory cell 21, each of the N-channel floating gate transistors is formed, and the size ratio of the channel length and the channel width is different. Is set to be about 1/2 of the memory cells 21, and the number of dummy cells 24 corresponding to the memory rows of the memory cell array 11 is provided. Each dummy cell 24 is connected in parallel with each memory cell 21 in a corresponding row, and the control gates of all the dummy cells 24 in the dummy cell column 12 have the most significant bit [ (ADR) m] is supplied.

In addition, an N-channel transistor 25 for discharge is connected between the common source of the memory cells 21 and the dummy cells 24 and the ground potential Vss in each row, and each gate of these transistors 25 is connected to each gate. The precharge control signal Pr is supplied in parallel.

On the other hand, between each of the plurality of bit lines 22 and the node A1, transistors 26 of N channels for column selection are inserted.

Decoded signals output from the column decoder 17 are supplied to the gates of these transistors 26.

In addition, an N-channel transistor 27 for leveling down is inserted between the node A1 and the node B1. The intermediate potential V _DD generated in the intermediate potential generating circuit 20 is supplied to the gate of the transistor 27. A P-channel transistor 28 for precharging, in which conduction is controlled by the precharge control signal Pr, is inserted between the node B1 and the power supply potential Vcc.

The second memory array 13 side is basically configured similarly to the first memory array 10 side, but the row address [(ADR) is applied to the control gate of each dummy cell 24 in the dummy cell array 15. The line address [(ADR) m] is supplied instead of m], and the point at which the decode signal of the row decoder 18 is supplied to the word line 23 is different from that of the first memory array 10. The nodes corresponding to the nodes A1 and B1 on the second memory array 13 side are A2 and B2.

In addition, data is not written into each of the dummy cells 24 and electrons are not injected into each floating gate, and the threshold voltage remains low.

The sense amplifier 19 is constituted by cross-connecting the input / output terminals of two NOR gates 31 and 32, and the node B1 on the side of the first memory array 10 has a potential of one pressure and the other. The flop 33 to which the potential of the node B2 on the second memory array 13 side is supplied as the input of the input, the output of the flip flop 33 and the row address [(ADR) m] are inputted. A NAND gate 34, a NAND gate 35 to which the output of the flip-flop 33 and the row address [(ADR) m] are input, and a NAND gate to which the outputs of the NAND gates 34 and 35 are input ( 36. The read data Dout is outputted from the NAND gate. The NOR gates 31 and 32 and the NAND gates 34, 35, and 36 each have a CMOS configuration.

The intermediate potential generating circuit 20 is configured as shown in FIG. 3, for example. That is, the P-channel transistor 41 between the power supply potential Vcc and the ground potential Vss. A depletion type N channel transistor 42 and an N channel transistor 43 having an intrinsic (threshold voltage almost OV) are inserted in series. The read control signal Rd is supplied to the gate of the transistor 41, and the gates of the transistors 42 and 43 are commonly connected to the connection node C of both transistors 42 and 43.

The intermediate potential V _DD is output from the node C. In the intermediate potential generating circuit 20, when the read control signal Rd becomes L level and the transistor 41 is turned on, the node C is intermediate between the power supply potential Vcc and the ground potential Vss. The potential V _DD is obtained. Since the gates of the transistors 42 and 43 are commonly connected to the node C, the intermediate potential V _DD is always constant even if the power supply potential Vcc fluctuates to some extent as shown in FIG. It is controlled to be a value.

Note that the transistors are all enhancement types unless otherwise specified.

Next, the operation of the memory having the above configuration will be described using the timing chart of FIG.

First, when the read control signal Rd reaches the L level, the intermediate potential generating circuit 20 is operated as described above, thereby enabling the readout. Thereafter, the precharge control signal Pr becomes L level so that the precharge transistor 27 on the first memory array 10 side and the second memory array 13 side is turned on, and the nodes B1 and B2 are respectively connected. It is precharged to the potential of Vcc. [Precharge period (Tp) in Fig. 5].

At this time, the discharging transistor 25 on the first memory array 10 side and the second memory array 13 side is in a non-conductive state, and a DC current is applied between the power supply potential Vcc and the ground potential Vss. Does not flow In this case, since the nodes B1 and B2 together become the potential of Vcc, that is, the H level, both outputs of the flip-flop 33 in the sense amplifier 19 become L level.

Next, the row address and the open address are supplied to the row decoders 16 and 18 and the column decoder 17. At this time, when the most significant bit [(ADR) m] of the row address is H level and (ADR) m is L level, the row decoder 16 is operated so that the word line 23 on the side of the first memory array 10 is operated. One of which is selectively driven. In this case, therefore, any one memory cell 21 in the memory cell array 11 on the first memory array 10 side is selected based on the decode output of the row decoder 16 and the column decoder 17. . At this time, the other row decoder 18 is not operated. Accordingly, nothing is selected in the memory cell 21 in the memory cell array 14 on the second memory array 13 side. However, since (ADR) m is H level, all the dummy cells 24 in the dummy cell column 15 on the second memory array 13 side are selected.

Thereafter, as the nematode control signal Pr changes from the L level to the H level, the bidirectional charging transistor 27 becomes non-conductive, and is now on the first memory array 10 side and the second memory array 13 side. The discharge transistor 25 is turned on. [Discharge Period Td in Fig. 5].

In this case, the threshold voltage is kept low unless the memory cell 21 selected on the first memory array 10 side has been pre-recorded and electrons are not injected into the floating gate. By selectively driving 23, the memory cell 21 is turned on, and the node B1, which has been precharged at a high potential in advance, is discharged to the ground potential Vss. As described in the related art, the potentials of the nodes B1 and B2 change according to the electrical characteristics of the selected memory cell 21 and the dummy cell 24, so that the change of the potentials is compared in the sense amplifier 19. The level of data Dout is determined. At this time, in the sense amplifier 19, the NAND gate 34 is opened by the address [(ADR) m] so that the output of the NOR gate 31 on the side of the first memory array 10 including the selected memory cell is selectively output. do. In addition, the output of the NAND gate 35 to which the output of the NOR gate 32 on the non-selective second memory array 13 side is supplied is fixed to the H level by the address [(ADR) m].

On the other hand, when the most significant bit [(ADR) m] of the row address is L level and (ADR) m is H level, the row decoder 18 is operated so that among the word lines 23 on the second memory array 13 side. One is selectively driven so that any one memory cell 21 in the memory cell array 11 on the second memory array 13 side is selected. Further, (ADR) m selects all the dummy cells 24 in the dummy cell column 15 on the first memory array 10 side, and changes the potentials of the nodes B1 and B2 in the same manner as described above. 19, the level of data Dout is determined.

Here, the same number of memory cells 21 and one dummy cell 24 are connected to each bit line 22 on the first memory array 10 side and the second memory array 13 side, respectively. The parasitic existing in the bit line 22 is the same regardless of the memory capacity. For this reason, the parasitic capacitance attached to each of the bit lines to which the selected memory cell is connected and the bit lines to which the selected dummy cell is connected are equal, so that the sense amplifier 19 is based only on the difference in electrical characteristics of each cell. The potential change is compared. As a result, the sense amplifier 19 can always detect correct data.

In the memory of the above embodiment, the bit line 22 is precharged before data is read out, and is discharged and readout at the time of reading, and the dynamics are reduced. Can be.

In addition, although the current is consumed during the readout period in the intermediate potential generating circuit 20, the current consumption can be reduced by increasing the impedance of the entire circuit.

In addition, this invention is not limited only to the said Example, Of course, various deformation | transformation is possible. For example, in the above embodiment, the case where the discharging transistors 24 are provided for each memory cell row has been described, but this is because only one is installed in the first memory array 10 and one in the second memory array 13 is provided. You may provide only one in all. In addition, although the case where a normal enhancement type was used as the level-down transistor 27 provided between the nodes A1 and B1 or the nodes A2 and B2 has been described, an intrinsic transistor may be used. By using the intrinsic transistor, even if an error occurs in the process, the potential supplied to the bit line can be made almost constant, thereby preventing a decrease in yield.

[Effect of design]

As described above, according to the present invention, in a nonvolatile semiconductor memory which detects data from a nonvolatile memory cell by performing precharge and discharge, a nonvolatile data can be detected correctly by the data detection means regardless of the memory capacity. A semiconductor memory can be provided.

Claims (4)

A first precharge-discharge type memory circuit having a plurality of first bit lines, a plurality of first nonvolatile memory cells and at least one nonvolatile dummy cell connected to the plurality of first bit lines; A second precharge-discharge type memory circuit having a plurality of second bit lines, a plurality of second nonvolatile memory cells, and at least one nonvolatile dummy cell connected to the plurality of second bit lines of the second memory circuit; One of the plurality of first nonvolatile memory cells of the first memory circuit along one of the at least one dummy cell of the second memory circuit, or one of the at least one dummy cell of the first memory circuit Cell selection means for selecting one of the plurality of second memory cells; The potentials output from the first or second memory circuits including the memory cells selected according to the potentials output from the first or second memory circuits including the dummy cells selected by the cell selecting means are compared to the selected memory cells. Data detecting means for detecting stored data. A plurality of bit line selection transistors included in the cell selecting means, each of which is connected to the bit line of each memory circuit at a first stage to form a node of each memory cell, and interconnected at a second end of each memory circuit; And a column decoder for selecting and driving one of the bit line selection transistors according to a signal. A plurality of level shifting transistors connected to a node of a second stage of said plurality of bit line selection transistors for each memory circuit in a first stage, and A nonvolatile semiconductor memory comprising a plurality of nematode transistors each connected at a first stage to a second stage of each of the plurality of level shifting transistors 2. The data detection means according to claim 1, wherein the output state is initially set in the precharge period of the first and second memory arrays, and the readout from the memory cell and the dummy cell selected by the selection means in the discharge period. A nonvolatile semiconductor memory comprising a CMOS flip-flop circuit for performing the above comparison 2. The nonvolatile semiconductor memory according to claim 1, wherein the geometric size of the dummy cells in the first and second memory arrays is set differently from that of the memory cells. At least one first nonvolatile dummy cell connected to the plurality of first bit lines, the plurality of first nonvolatile memory cells, and the plurality of first bit lines having different electrical characteristics from the plurality of first nonvolatile memory cells, A first line charge having a plurality of first word lines for selecting a first nonvolatile memory cell and a dummy word line for simultaneously selecting at least one first nonvolatile dummy cell connected to the plurality of first bit lines Discharge memory circuits, At least one second nonvolatile dummy cell connected to the plurality of second bit lines, the plurality of second nonvolatile memory cells, and the plurality of second bit lines having different electrical characteristics from the plurality of second nonvolatile memory cells, A second line charge having a plurality of second word lines for selecting a second nonvolatile memory cell and a dummy word line for simultaneously selecting at least one second nonvolatile dummy cell connected to the plurality of second bit lines Discharge type memory circuit One of a plurality of first nonvolatile memory cells of the first memory circuit along at least one second nonvolatile dummy cell of the second memory circuit, or at least one first nonvolatile dummy cell of the first memory circuit Cell selection means for selecting one of the plurality of second memory cells of the two memory circuits to read data from the selected nonvolatile memory cell; A nonvolatile selected by comparing the potential output from the first or second memory circuit including the memory cell selected according to the potential output from the first or second memory circuit including the nonvolatile dummy cell each selected by the cell selection means Data detecting means for detecting data stored in the memory cell, A plurality of bit line selection transistors included in the cell selecting means, each of which is connected to the bit line of each memory circuit at a first stage to form a node of each memory cell, and interconnected at a second end of each memory circuit; First and second bit line selection circuits including a column decoder for selecting and driving one of the bit line selection transistors according to a signal A plurality of level shifting transistors connected to a node of a second stage of said plurality of bit line selection transistors for each memory circuit in a first stage, and A nonvolatile semiconductor memory comprising a plurality of precharge transistors each connected at a first stage to a second stage of each of the plurality of level shifting transistors