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KR960006599A - 2-D Discrete Cosine Converter - Google Patents

2-D Discrete Cosine Converter Download PDF

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KR960006599A
KR960006599A KR1019940016608A KR19940016608A KR960006599A KR 960006599 A KR960006599 A KR 960006599A KR 1019940016608 A KR1019940016608 A KR 1019940016608A KR 19940016608 A KR19940016608 A KR 19940016608A KR 960006599 A KR960006599 A KR 960006599A
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discrete cosine
data
control signal
unit
cosine transform
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KR1019940016608A
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KR0124169B1 (en
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김성정
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배순훈
대우전자 주식회사
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/60—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding
    • H04N19/625—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding using discrete cosine transform [DCT]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • H04N19/423—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements
    • H04N19/426—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements using memory downsizing methods
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/50—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding
    • H04N19/593—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding involving spatial prediction techniques

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  • Discrete Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Complex Calculations (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Compression Or Coding Systems Of Tv Signals (AREA)

Abstract

본 발명은 보다 간단한 하드웨어로 보다 간단하면서도 빠르게 2차원 역이산 코사인 변환을 행할 수 있다는 개선된 2차원 역이산 코사인 변환기에 관한 것이다. N×N의 영상 데이타(X)를 기설정된 순서로 입력받아 1차원 이산 코사인 변환하여 출력하는 1차원 이산 코사인 변환1부와, 상기 1차원 이산 코사인 변환1부로부터 제공되는 N×N의 1차원 이산 코사인 변환된 데이타(Y1)를 전치시켜 상기 기설정된 순서로 출력하는 전치부와, 상기 전치부로부터 제공되는 데이타(X1)를 1차원 이산 코사인 변환하고, 그 결과로 얻어진 2차원 이산 코사인 변환된 데이타를 출력하는 1차원 이산 코사인 변환2부를 갖는 본 발명의 2차원 이산 코사인 변환기는, 상기 변환기가 외부로부터의 제1클럭신호(CLK)를 입력받아, 래치 제어신호(C), 제1선택부 제어신호(SO), 롬 제어신호(A), 및 제2선택부 제어신호(P)를 출력하는 로직제어부를 포함한다.The present invention relates to an improved two-dimensional inverse discrete cosine transformer that can perform simpler and faster two-dimensional inverse discrete cosine transform with simpler hardware. A one-dimensional discrete cosine transform unit for receiving N × N image data X in a predetermined order and outputting one-dimensional discrete cosine transform and a one-dimensional N × N one unit provided from the one-dimensional discrete cosine transform unit 1 and anterior that was pre-discrete cosine transformed data (Y 1) output in the predetermined order, the transformed data (X 1) a discrete cosine first dimension provided by the anterior, and the two-dimensional and the resulting DCT In the two-dimensional discrete cosine transformer of the present invention having two one-dimensional discrete cosine transform outputting data, the converter receives the first clock signal CLK from the outside, and the latch control signal C and the first selector. And a logic controller for outputting a control signal SO, a ROM control signal A, and a second selector control signal P. FIG.

Description

2차원 이산 코사인 변환기2-D Discrete Cosine Converter

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 본 발명에 따른 2차원 이산 코사인 변환기를 도시한 블럭도.1 is a block diagram illustrating a two-dimensional discrete cosine transformer in accordance with the present invention.

제2도는 본 발명에 따른 2차원 이산 코사인 변환기를 구성하는 1차원 이산 코사인 변환부를 도시한 블럭도.2 is a block diagram illustrating a one-dimensional discrete cosine transform unit constituting a two-dimensional discrete cosine transformer according to the present invention.

Claims (12)

N×N의 영상 데이타(X)를 기설정된 순서로 입력받아 1차원 이산 코사인 변환하여 출력하는 1차원 이산 코사인 변환1부(100)와, 상기 1차원 이산 코사인 변환1부(100)로부터 제공되는 N×N의 1차원 이산 코사인 변환된 데이타(Y1)를 전치시켜 상기 기설정된 순서로 출력하는 전치부(120)와, 상기 전치부(120)로부터 제공되는 데이타(X1)를 1차원 이산 코사인 변환하고, 그 결과로 얻어진 2차원 이산 코사인 변환된 데이타를 출력하는 1차원 이산 코사인 변환2부(140)를 갖는 2차원 이산 코사인 변환기에 있어서, 상기 변환기가 외부로 부터의제1클럭신호(CLK)를 입력받아, 래치 제어신호(C), 제1선택부 제어신호(SO), 롬 제어신호(A), 및 제2선택부 제어신호(P)를 출력하는 로직제어부(160)를 포함하며, 상기 1차원 이산 코사인 변환1부(100)가, 상기 제1클럭신호(CLK)에 응답하여 상기 N×N 영상 데이타(X)의 한 행 데이타(x0, x1, x2, x3,…,xn)를 순차적으로 입력받아 소정 시간 저장하며, 상기 로직제어부(160)로부터 제공되는 상기 래치제어신호(C)에 응답하여 저장하고 있던 한 행 데이타를 순차적으로 출력하는 버퍼부(200)와; 상기 로직제어부(160)로부터 제공되는 상기 제1선택부 제어신호(SO)에 응답하여, 상기 버퍼부(200)로부터 순차적으로 제공되는 데이타를 선택적으로 출력하는 제1선택부(220)와; N×N의 이산 코사인 변환계수가 저장되어 있는 롬(ROM)을 가지며, 상기 로직제어부(160)로 부터 제공되는 상기 롬 제어신호(A)에 응답하여 상기 제1선택부(220)로부터 제공되는 상기 데이타와 상기 이산 코사인 변환 계수를 승산하고 행단위로 누산하여 출력하는 행연산부(240)와; 상기 로직제어부(160)로부터 제공되는 상기 제2선택부 제어신호(P)에 응답하여, 상기 행연산부(240)로부터 제공되는 데이타를 선택적으로 출력하는 제2선택부(260)를 포함하며, 상기 N은 양의 정수인 것을 특징으로 하는 2차원 이산 코사인 변환기.1D discrete cosine transform 1 unit 100 for receiving N × N image data X in a predetermined order and outputting the 1D discrete cosine transform and the 1D discrete cosine transform 1 unit 100 One-dimensional discrete cosine transforming the preposition unit 120 for transposing the N × N one-dimensional discrete cosine transformed data Y 1 and outputting the data in the predetermined order, and the data X 1 provided from the preposition unit 120. In the two-dimensional discrete cosine transformer having a one-dimensional discrete cosine transform 2 section 140 for outputting the resulting two-dimensional discrete cosine transformed data, the converter is a first clock signal (CLK) from the outside And a logic control unit 160 for receiving a latch control signal C, a first selector control signal SO, a ROM control signal A, and a second selector control signal P. The one-dimensional discrete cosine transform unit 1 may generate an image in response to the first clock signal CLK. One row data (x 0 , x 1 , x 2 , x 3 ,..., X n ) of the N × N image data X are sequentially input and stored for a predetermined time, and are provided from the logic controller 160. A buffer unit 200 for sequentially outputting one row data stored in response to the latch control signal C; A first selector (220) for selectively outputting data sequentially provided from the buffer unit (200) in response to the first selector control signal (SO) provided from the logic controller (160); A ROM having a discrete cosine transform coefficient of N × N is stored and provided from the first selector 220 in response to the ROM control signal A provided from the logic controller 160. A row operation unit 240 multiplying the data and the discrete cosine transform coefficients and accumulating the data in units of rows; And a second selector 260 for selectively outputting data provided from the row operator 240 in response to the second selector control signal P provided from the logic controller 160. A two-dimensional discrete cosine converter, wherein N is a positive integer. 제1항에 있어서, 상기 전치부(120)에서의 기설정된 순서는 상기 영상 데이타(X)의 N×N 매트릭스내에서의 배열순서임을 특징으로 하는 2차원 이산 코사인 변환기.The two-dimensional discrete cosine converter according to claim 1, wherein the predetermined order in the preposition unit (120) is an arrangement order in the N × N matrix of the image data (X). 제2항에 있어서, 상기 N이 8인 것을 특징으로 하는 2차원 이산 코사인 변환기.3. The two-dimensional discrete cosine transducer of claim 2, wherein N is eight. 제3항에 있어서, 상기 버퍼부(200)가, 8개의 레지스터로 구성된 레지스터부(204)와; 8개의 래치로 구선된 래치부(208)를 포함하며, 상기 레지스터부(204)의 각 레지스터는 상기 제1클럭신호(CLK)에 응답하여 한 행 데이타(x0, x1, x2, x3, x4, x3, x6, x7)를 순차적으로 입력받아 소정 시간 저장하며, 저장하고 있던 데이타를 이웃하는 다음 레지스터 및 그에 대응하는 위치의 래치로 각각 전달하는 것을 특징으로 하는 2차원 이산 코사인 변환기.4. The apparatus of claim 3, wherein the buffer unit (200) comprises: a register unit (204) consisting of eight registers; And a latch portion 208 formed by eight latches, and each register of the register portion 204 has one row of data x 0 , x 1 , x 2 , x in response to the first clock signal CLK. 3 , x 4 , x 3 , x 6 , and x 7 ) are sequentially received and stored for a predetermined time, and two-dimensionally characterized by transferring the stored data to a neighboring next register and a latch of a corresponding position, respectively. Discrete cosine converter. 제4항에 있어서, 상기 로직제어부(160)가 상기 제1클럭신호(CLK)의 8클럭을 주기로 상기 래치 제어신호(C)를 출력하는 것을 특징으로 하는 2차원 이산 코사인 변환기.5. The two-dimensional discrete cosine converter of claim 4, wherein the logic controller 160 outputs the latch control signal C at intervals of eight clocks of the first clock signal CLK. 제5항에 있어서, 상기 래치부(208)가 상기 래치 제어신호(C)에 응답하여, 저장하며 상기 8개 데이타(x0, x1, x2, x3, x4, x3, x6, x7)를 통시에 출력하는 것을 특징으로 하는 2차원 이산 코사인 변환기.The method of claim 5, wherein the latch unit 208 stores and stores the eight data (x 0 , x 1 , x 2 , x 3 , x 4 , x 3 , x in response to the latch control signal C). 6 , x 7 ) through a two-dimensional discrete cosine converter characterized in that output at the same time. 제6항에 있어서, 상기 제1선택부(220)가, 상기 래치부(208)로부터 출력되는 8개 데이타 중 상위 4개 데이타(x0, x1, x2, x3)를 입력하여 상기 제1선택부 제어신호(SO)에 의해 선택적으로 출력하는 제1멀티플렉서(224)와; 상기 래치부(208)로부터 출력되는 8개 데이타 중 하위 4개 데이타(x4, x5, x6, x7)를 입력하여 상기 제1선택부 제어신호(SO)에 의해 선택적으로 출력하는 제2멀티플렉서(228)를 포함하는 것을 특징으로 하는 2차원 이산 코사인 변환기.The method of claim 6, wherein the first selector 220 inputs the top four data (x 0 , x 1 , x 2 , x 3 ) of the eight data output from the latch unit 208 to receive the data. A first multiplexer 224 selectively outputting the first selector control signal SO; A fourth output unit (x 4 , x 5 , x 6 , x 7 ) among the eight data outputted from the latch unit 208 and selectively output by the first selector control signal SO; Two-dimensional discrete cosine transducer, characterized in that it comprises a two-multiplexer (228). 제7항에 있어서, 상기 제1선택부 제어신호(SO)는 제1선택부 제어신호 1 내지 4로 구성되며, 상기 제1 및 2멀티플렉서(224 및 228)가 상기 제1선택부 제어신호1에 응답하여 각각 x0및 x7을 출력하며, 상기 제1선택부 제어신호2에 응답하여 각각 x1및 x6을 출력하고, 상기 제1선택부 제어신호3에 응답하여 각각 x2및 x5을 출력하며, 그리고 상기 제1선택부 제어신호4에 응답하여 각각 x3및 x4를 출력하는 것을 특징으로 하는 2차원 이산 코사인 변환기.8. The control unit according to claim 7, wherein the first selector control signal (SO) is composed of first selector control signals 1 to 4, and the first and second multiplexers 224 and 228 are configured to control the first selector control signal 1. Outputs x 0 and x 7 in response to the control signal, outputs x 1 and x 6 in response to the first selector control signal 2, respectively, and outputs x 2 and x in response to the first selector control signal 3, respectively. Outputting 5 and outputting x 3 and x 4 in response to the first selector control signal 4, respectively. 제8항에 있어서, 상기 행연산부(240)가, 상기 제1멀티플렉서(224)로부터 제공되는 소정의 데이타와 상기 제2멀티플렉서(228)로부터 제공되는 소정의 데이타를 가산하는 가산부(241)와; 상기 제1멀티플렉서(224)로부터 제공되는 소정의 데이타에서 상기 제2멀티플렉서(228)로부터 제공되는 소정의 데이타를 감산하는 감산부(242)와; 상기 가산부(241)로부터 제공되는 데이타를 기설정된 이산 코사인 변환 계수와 승산하고, 행단위로 출력하는 제1계산부(243)와; 상기 감산부(242)로부터 제공되는 데이타를 기설정한 이산 코사인 변환 계수와 승산하고, 행단위로 누산하여 출력하는 제2계산부(246)를 포함하는 것을 특징으로 하는 2차원 이산 코사인 변환기.10. The apparatus of claim 8, wherein the row operator 240 adds predetermined data provided from the first multiplexer 224 and predetermined data provided from the second multiplexer 228; ; A subtraction unit 242 which subtracts predetermined data provided from the second multiplexer 228 from predetermined data provided from the first multiplexer 224; A first calculator 243 for multiplying the data provided by the adder 241 with a predetermined discrete cosine transform coefficient and outputting the data in units of rows; And a second calculation unit (246) for multiplying the data provided by the subtraction unit (242) with a predetermined discrete cosine transform coefficient and accumulating the output in units of rows. 제9항에 있어서, 상기 제1계산부(243)가, 4×4의 기설정된 이산 코사인 변환 계수를 저장하고, 상기 롬 제어신호(A)에 응답하여 상기 이산 코사인 변환 계수를 출력하는 제1롬(244)과; 상기 가산부(241)로부터 제공되는 데이타를 상기 제1롬(244)으로부터 제공되는 이산 코사인 변환 계수와 승산하고, 행단위로 누산하여 출력하는 제1맥(245)을 포함하며, 상기 제2계산부(246)가, 4×4의 기설정된 이산 코사인 변환 계수를 저정하고, 상기 롬 제어신호(A)에 응답하여 이산 코사인 변환 계수를 출력하는 제2롬(248)과; 상기 감산부(242)로부터 제공되는 데이타를 상기 제2롬(244)로부터 제공되는 이산 코사인 변환 계수와 승산하고, 행단위로 누산하여 출력하는 제2맥(246)을 포함하는 것을 특징으로 하는 2차원 이산 코사인 변환기.10. The apparatus of claim 9, wherein the first calculator 243 stores a predetermined discrete cosine transform coefficient of 4x4 and outputs the discrete cosine transform coefficient in response to the ROM control signal A. Romans 244; And a first vein 245 that multiplies the data provided by the adder 241 with the discrete cosine transform coefficients provided by the first ROM 244 and accumulates the output in rows. A second ROM (248) for storing a 4x4 predetermined discrete cosine transform coefficient and outputting discrete cosine transform coefficients in response to the ROM control signal (A); And a second vein 246 that multiplies the data provided by the subtractor 242 with the discrete cosine transform coefficients provided by the second ROM 244 and accumulates the data in rows. Discrete cosine converter. 제10항에 있어서, 상기 제2선택부(260)가 상기 제2선택부 제어신호(P)에 응답하여 상기 제1맥(245) 및 제2맥(248)로부터 제공되는 데이타를 교번적으로 출력하는 것을 특징으로 하는 2차원 이산 코사인 변환기.The method of claim 10, wherein the second selector 260 alternately supplies data provided from the first vein 245 and the second vein 248 in response to the second selector control signal P. 12. Two-dimensional discrete cosine converter characterized in that the output. 제11항에 있어서, 상기 1차원 이산 코사인 변환2부(140)가 상기 1차원 이산 코사인 변환1부(100)와 동일한 구성을 갖는 것을 특징으로 하는 2차원 이산 코사인 변환기.12. The two-dimensional discrete cosine converter of claim 11, wherein the one-dimensional discrete cosine transform unit 2 (140) has the same configuration as the one-dimensional discrete cosine transform unit 1 (100). ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940016608A 1994-07-11 1994-07-11 2-D Discrete Cosine Converter KR0124169B1 (en)

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