KR960001331B1 - Semiconductor memory device and manufacturing method thereof - Google Patents

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Description

Semiconductor memory device and manufacturing method thereof

1 through 4 are cross-sectional views illustrating a method of manufacturing a semiconductor memory device by a conventional method.

5 is a sectional view showing a semiconductor memory device manufactured by the method of the present invention.

6 to 12 are sectional views shown for explaining the first embodiment of the method of manufacturing a semiconductor memory device according to the present invention.

13 to 18 are sectional views shown for explaining the second embodiment of the method of manufacturing a semiconductor memory device according to the present invention.

19 and 20 are sectional views shown for explaining the third embodiment of the method of manufacturing a semiconductor memory device according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly to a semiconductor memory device having an improved storage electrode structure of a capacitor in order to increase its capacitance in a memory cell having a stacked capacitor structure and a method of manufacturing the same. .

The reduction of cell capacitance due to the reduction of memory cell area is a serious obstacle to increasing the density of dynamic random access memory (DRAM), which not only reduces the readability of the memory cell and increases the soft error rate, but also the device at low voltage. It is a problem that must be solved for high integration of a semiconductor memory device because the operation is made difficult and the power consumption is excessive during operation.

In general, in a 64Mb DRAM having a memory cell area of about 1.5 μm ² , if a typical two-dimensional stack type memory cell is used, it is difficult to obtain sufficient capacitance even if a material having a high dielectric constant such as Ta ₂ O ₅ is used. The stacked capacitor of the dimensional structure is proposed to improve the capacitance. The double stack structure, fin structure, cylindrical electrode structure, spread stack structure, and box structure are proposed three-dimensional structures for increasing cell capacitance of memory cells. Storage electrodes.

In the three-dimensional stack type cell capacitor structure, especially the cylindrical structure can be used as an effective capacitor area not only on the outer surface of the cylinder but also on the inner surface, so it is adopted as a structure suitable for 64 Mb-class memory cells or higher density memory cells. A capacitor structure has been proposed to improve cell capacitance by adding a cylinder or another cylinder inside a cylinder.

1 through 4 are cross-sectional views illustrating a method of manufacturing a semiconductor memory device by a conventional method, and explain a method of forming a storage electrode having a structure in which another cylinder is added inside the cylinder. This is referred to a paper published in IEEE in 1991, "Crown-Shaped Stacked-Capacitor Cell for 1.5-V Operation 64-Mb DRAM's".

1 shows one bit line 20 and one drain region 16 in the active region of the semiconductor substrate, which are divided into an active region and an inactive region by the field oxide film 12, each of which has one source region 14. And forming a transistor having a gate electrode 18, and forming an insulating layer 19 on the entire surface of the resultant to insulate the transistor from other conductive layers (a conductive layer to be produced by a subsequent process). Forming a planarization layer 22 on the entire surface of the resultant; forming a contact flow by partially removing the insulating layer and the planarization layer stacked on the source region 14; Forming a starting electrode 30 by filling with polysilicon, laminating a first silicon dioxide layer 24, a silicon nitride layer 26 and a second silicon dioxide layer 32 on the entire surface of the resultant, Each cell unit Forming a well in the stacked material layer to expose the surface of the pillar electrode 30, and depositing a second polysilicon on the entire surface of the resultant to form a first polycrystalline silicon layer 34; And a process of forming a spacer 36 of a third silicon dioxide layer on the inner sidewall of the well by anisotropic etching after forming the third silicon dioxide layer.

FIG. 2 illustrates a process of forming a second polysilicon layer 38 by depositing a third polysilicon layer on the entire surface of the semiconductor substrate on which the spacers 36 are formed, and to prevent the surface of the second polysilicon layer from being exposed. The semiconductor device formed by the process of forming the 4th silicon dioxide layer 40 in the front surface is shown.

3 is a step of etching back the fourth silicon dioxide layer to the height of the top surface of the spacer 36, and removing the second polysilicon layer exposed to the surface by anisotropic etching, followed by the anisotropic etching. A semiconductor device formed by a process of forming the storage electrode 100 by anisotropically etching the first polysilicon layer exposed to the surface is shown.

4 is a step of removing the fourth silicon dioxide layer, the spacer and the second silicon dioxide layer, forming the dielectric film 110 on the entire surface of the storage electrode 100 and the fourth polysilicon on the entire surface of the resultant. The semiconductor device formed by the process of depositing and forming the plate electrode 120 is shown.

According to the method of manufacturing a semiconductor memory device according to the conventional method described above, a storage electrode to which another cylinder is added can be formed inside the cylinder, thereby improving cell capacitance. First, the pillar electrode (described in FIG. 1) When the first polysilicon is filled after forming the contact hole for formation, the shape of the cylinder formed thereon depends on the state in which the first polysilicon is filled, so that the first It is important to accurately fill polycrystalline silicon, which process is very difficult.

Second, in the process of anisotropically etching the second silicon dioxide layer to form a well (described in FIG. 1), the well is easily formed so that its sidewalls are inclined, which is a hole between cells in forming a plate electrode. (Void) is formed to reduce the electrical characteristics of the memory device.

Third, when etching back the fourth silicon dioxide (described in FIG. 3), it is difficult to control the degree, so that it is difficult to secure uniform cell capacitance.

Fourth, when the first polycrystalline silicon layer is formed and then the second polycrystalline silicon layer is formed (described in FIG. 2), a thin natural oxide film is formed on the surface of the first polysilicon layer, thereby providing electrical characteristics of the memory device. Lowers.

Fifth, since the end of the cylindrical electrode is sharply formed, there are many problems such as the possibility of leakage current.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device capable of improving reliability and cell capacitance.

Another object of the present invention is to provide a method of manufacturing the semiconductor memory device suitable for manufacturing the semiconductor memory device.

The object of the present invention is formed of a pillar electrode formed in a columnar shape, a cylindrical electrode connected to the upper portion of the pillar electrode and formed in a double overlapping cylindrical shape, and a disk electrode formed in a disk shape spread in all directions from the middle of the pillar electrode. A semiconductor memory device including a capacitor including a storage electrode is achieved.

The other object of the invention is a step of forming a first conductive layer on the entire surface of the semiconductor substrate, a step of forming a predetermined pattern in a shape that is isolated in each cell unit on the first conductive layer, each of the first conductive layer Forming a first storage electrode pattern by etching to be limited to a cell unit; forming a first sidewall spacer on a predetermined pattern and sidewalls of the first storage electrode pattern; removing a predetermined pattern; Forming a second storage electrode pattern by etching the first conductive layer to a predetermined depth by using the sidewall spacers of the substrate as a etch mask, removing the first sidewall spacer, and forming a sidewall spacer on the sidewall of the second storage electrode pattern. Forming a second sidewall spacer; forming a storage electrode by anisotropically etching the first conductive layer using the second sidewall spacer as an etch mask; and the second sidewall spacer; It is achieved by a method for manufacturing a semiconductor memory device including the step of removing the side wall spacers.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

5 is a perspective view showing a semiconductor memory device manufactured by the method of the present invention, in which a transistor consisting of a source region 14, a drain region 16 and a gate electrode 18, a bit connected to the drain region of the transistor A line 20, a pillar electrode 100a connected to the source region of the transistor and formed in a pillar shape, a cylindrical electrode 100b connected to an upper portion of the pillar electrode and overlapping in two layers, and a middle portion of the pillar electrode. In the storage electrode 100 consisting of a disk electrode (100c) formed in the shape of a disk unfolded in all directions, the dielectric film 110 directed to cover the entire surface of the storage electrode and the plate electrode formed to cover the entire surface of the dielectric film A semiconductor memory device including 120 is shown.

According to the semiconductor memory device shown in FIG. 5, the cell capacitance can be easily increased by forming the cylindrical electrode in two layers and forming the disc electrode at the bottom thereof, and since the end of the cylindrical electrode is not sharply formed. There is no possibility of exposure to leakage current, enabling a highly reliable memory device.

6 through 12 are cross-sectional views illustrating a first embodiment of a method of manufacturing a semiconductor memory device according to the present invention.

First, FIG. 6 illustrates a process of forming a predetermined pattern 52 on the first conductive layer, and the process of forming the planarization layer 22 by the method described in FIG. Since the present invention is not the subject matter of the present invention, the method described in the related art is used as it is), and the first and second insulating layers are alternately stacked on the entire surface of the resultant, and the source region 14 of the transistor is Forming a contact hole on the source region by partially removing the first insulating layer and the second insulating layers, the planarization layer 22, and the insulating layer 19 which are stacked on the planarization layer which is exposed; Depositing a conductive material such as polycrystalline silicon doped with impurities to a thickness of about 3,000 kPa to 6,000 kPa on the entire surface of the resultant to form the first conductive layer 50, optionally on the entire first conductive layer. Etching process For example, an insulating material having an etch rate different from that of the material constituting the first conductive layer, for example, an oxide such as HTO (High Temperature Oxide), is applied to a thickness of about 1,000 kPa, for example, to form the first first material layer. Forming a photoresist, a photoresist such as photoresist on the entire surface of the resultant, patterning the photosensitive material so as to be limited to each cell unit, and forming a photoresist pattern 54, and using the photoresist pattern as an etching mask. The process of forming a predetermined pattern 52 by isotropically etching the first first material layer is performed. When the isotropic etching process is performed based on the edge portion of the photosensitive film pattern, the isotropic etching process is preferably performed to be etched in a length of about 1,000 mW to 1,500 mW in the lateral direction.

At this time, the material constituting the first material layer and the second material layer, the etching rate is different from the material constituting the first conductive layer for any etching process (A material for any etching process When the etch rate of is 1, the etch rate of B material is 4 ~ 5). Insulation material is used. Such materials include nitrides such as silicon nitride (Si ₃ N ₄ ) and oxides such as high temperature oxide film (HTO) when polycrystalline silicon doped with impurities is used as a material constituting the first conductive layer. have. In this specification, the words 'first' or 'second' and the like are referred to as the first material layer, the nitride as the second material layer, and described before the first material layer or the second material layer. It means an arbitrary name to distinguish each layer.

The first material layer and the second material layer alternately stacked on the planarization layer 22 may include a second first material layer 44, a first second material layer 46, and a third first material layer. The material layer 48 may be formed of three material layers, such as the material layer 48 (first embodiment), and a second material layer is added below the second first material layer to form a second second material. It may be formed of four material layers such as the layer 42, the second first material layer 44, the first second material layer 46, and the third first material layer 48 ( Second embodiment). At this time, each layer is formed to a thickness of about 500 kPa. Detailed description thereof will be described later.

FIG. 7 illustrates a process of forming the first storage electrode pattern 50a, wherein the photoresist pattern 54 is an etch mask and the third material layer 48 is an etch end point. It is formed by the process. It will be apparent to those skilled in the art that the first storage electrode pattern is formed in a shape defined for each cell unit like the photoresist pattern.

8 shows a process of forming the first sidewall spacers 56. A process of removing the photoresist pattern, and anisotropic after forming a second material layer having a thickness of about 500 kPa to 1,000 kPa on the entire surface of the resultant. Etching is performed to form a first sidewall spacer 56 on sidewalls of the predetermined pattern 52 and the first storage electrode pattern 50a.

FIG. 9 illustrates a process for forming the second storage electrode pattern 50b, which is an oxide etchant, such as a buffered oxide etchant (BOE; a solution in which NH ₄ F and HF are mixed at an appropriate ratio). Removing the predetermined pattern using the third first material layer, wherein the first sidewall spacer 56 is etched to define the first storage electrode pattern. The second storage electrode pattern 50b is formed by anisotropic etching to a depth of, for example, about 500 GPa.

FIG. 10 illustrates a process of forming the second sidewall spacers 58, wherein the process of removing the first sidewall spacers (in which case the first second material layer is also removed), A second sidewall spacer 58 is formed on the sidewalls of the second storage electrode pattern 50b by forming the second material layer to a thickness of about 500 to about 1,000 micrometers, and then anisotropically etching (first first layer). Example).

In the second embodiment, oxide is used as a material for forming the second sidewall tracer.

FIG. 11 illustrates a process of forming a storage electrode 100 including a pillar electrode 100a and a cylindrical electrode 100b formed in two overlapping cylindrical shapes, wherein the second sidewall spacer 58 is used as an etch mask. The second storage electrode pattern is formed by a process of anisotropic etching to a depth of about 2,000 kPa to 5,000 kPa (when the thickness of the first conductive layer 50 is 3,000 kPa to 6,000 kPa).

FIG. 12 illustrates a process of forming the dielectric film 110 and the plate electrode 120. The process of removing the second sidewall spacer (when the second sidewall spacer is formed of nitride (first first). Example 1 When the second first material layer (44 in FIG. 11) is not removed, but when the second sidewall spacer is formed of an oxide (second example), the second The first material layer is removed together with the second sidewall spacer), and a dielectric material such as an oxide / nitride / oxide (ONO) film or Ta ₂ O ₅ is coated on the entire surface of the storage electrode 100 to form the dielectric film ( And forming a plate electrode 120 by depositing a conductive material such as polysilicon doped with impurities, for example, on the entire surface of the resultant.

According to the first embodiment, since the storage electrode having two cylindrical electrodes can be formed, the cell capacitance can be easily increased, and since the end of the cylindrical electrode is not sharply formed, there is no possibility of leakage current. Can increase the reliability.

In the first embodiment, when a second material layer is used as a material forming a predetermined pattern (see FIG. 6), a material layer laminated on the first and second sidewall spacers and the planarization layer. Of course, it is necessary to change the material constituting the. For example, the material layer formed of the first material layer is changed into the second material layer, and the material layer formed of the second material layer is changed into the first material layer. In the present specification, a buffer oxide film as described in FIG. 9 is used to remove the first material layer, and phosphoric acid is used to remove the second material layer. However, the etchant is not limited to the above examples, and the etchant may also change as the material used is changed.

13 to 18 are cross-sectional views shown for explaining the second embodiment of the manufacturing method of the semiconductor memory device according to the present invention.

First, FIG. 13 illustrates a process of forming a predetermined pattern 72 and a third sidewall spacer 76 on the first conductive layer 50. The method of FIG. 13A is the same as the method described with reference to FIG. A step of forming up to the first conductive layer 50, and the third second material layer 72 and the fourth first material layer 74 are sequentially laminated on the first conductive layer with a thickness of about 1,500 GPa. And a predetermined pattern 72 of the third second material layer by anisotropically etching the third second material layer and the fourth first material layer so as to be limited to each cell unit. Using the same reference numerals as the second material layer of < RTI ID = 0.0 > (wherein < / RTI > the fourth first material layer is also patterned in the same shape as the predetermined pattern), on the entire surface of the resultant, for any anisotropic etching The material constituting the first conductive layer is different from the etch rate thereof, and for any isotropic etching, the fourth first material And the same etch rate (when the etch rate of the A material is 1 to 5 for any etching process, the etching rate of the B material is 4 to 5 or less), for example, an oxide such as a high temperature oxide film. After the coating is applied in a thickness of, anisotropic etching is performed to form the third sidewall spacer 76.

In this case, the material layer applied on the planarization layer 22 may include a fourth second material layer 60, a sixth first material layer 66, a fifth second material layer 68, and a seventh material. It may be formed of four material layers, such as the first material layer 70 of (first second embodiment), the second material layer 60 of the fourth layer, and the eighth first material layer ( 62), the sixth second material layer 64, the sixth first material layer 66, the fifth second material layer 68, and the seventh first material layer 70 It may also be formed of a material layer (second second embodiment). In addition, the fourth second material layer 60 may be formed to a thickness of about 100 GPa, and the other layers 62, 64, 66, 68, and 70 may be formed to a thickness of about 500 GPa.

FIG. 14 illustrates a process of forming the first storage electrode pattern 50a and the first sidewall spacer 56. The third sidewall spacer and the fourth first material layer are etch masks. Anisotropically etching the first conductive layer using the first material layer of FIG. 7 as an etching end point to form the first storage electrode pattern 50a having a shape defined in each cell unit, the third sidewall spacer and the third Removing the first material layer of 4 (at this time, the seventh first material layer is also removed), and forming the first material layer to a thickness of about 500 kPa on the entire surface of the resultant, and then anisotropically etching it. The process of forming the first sidewall spacers 56 is performed.

FIG. 15 illustrates a process of forming the second storage electrode pattern 50b, wherein the process of removing a predetermined pattern (in which case, the fifth second material layer is also removed) and the first sidewall spacer The second storage electrode pattern 50b is formed by anisotropically etching the first storage electrode pattern to a depth of about 1,000 mm by using 56 as an etching mask.

FIG. 16 shows the process of forming the second sidewall spacer 58, wherein the process of removing the first sidewall spacer (in which case the sixth first material layer is also removed), After forming one material layer to a thickness of, for example, about 500 kPa, the process proceeds to anisotropic etching.

FIG. 17 illustrates a process of forming the storage electrode 100 including the starting electrode 100a and a cylindrical electrode 100b formed in two overlapping cylindrical shapes, wherein the second sidewall spacer 58 is etched. And anisotropic etching using the second storage electrode pattern as an etching target and the sixth second material layer (in the case of the first embodiment, the fourth second material layer) as the end point. The storage electrode is completed by the front surface. In this case, in the first second embodiment, the sixth second material layer is an etching process (anisotropic or isotropic process) using the second sidewall spacer as an etching mask before or after the anisotropic etching process for forming the storage electrode. Etched by

FIG. 18 illustrates a process of forming the dielectric film 110 and the plate electrode 120. The process of removing all material layers (except storage electrodes) formed on the fourth second material layer 60 is illustrated in FIG. And forming a dielectric film 110 on the storage electrode (the same method as described in FIG. 12), and depositing a conductive material such as polycrystalline silicon doped with impurities, for example, on the entire surface of the resultant plate electrode 120. ) To the process of forming.

In the second embodiment, when the material constituting the predetermined pattern is changed from oxide to nitride, it is necessary to change the first material layer to the second material layer and the second material layer to the first material layer. It will be apparent to those skilled in the art to which the invention pertains.

According to the second embodiment, not only a storage electrode having the same shape as the storage electrode formed by the method of the first embodiment can be formed, but also a larger cell capacitance can be obtained than in the first embodiment. This is because the first storage electrode pattern can be formed larger than the first embodiment, and the distance between the lower surface of the cylindrical electrode and the planarization layer can be made larger.

19 and 20 are cross-sectional views illustrating a third embodiment of a method of fabricating a semiconductor memory device according to the present invention, wherein the material used as the sixth second material layer in the second embodiment is described above. After the conductive material layer 82 is formed of the same conductive material as the material constituting the first conductive layer, the conductive material layer is also etched together during the anisotropic etching process of forming a storage electrode (see FIG. 17). do.

According to the third embodiment, since the disc electrode 100c can be formed between the lower surface of the storage electrode and the planarization layer, a larger cell capacitance can be obtained than in the first and second embodiments.

Therefore, according to the semiconductor memory device and the manufacturing method thereof according to the present invention, since there is no pointed portion, the possibility of occurrence of leakage current is eliminated, and the storage electrode is formed as a lower conductive layer (first and second). Second Embodiment Since a cell capacitor can be formed which eliminates the possibility of generating a natural oxide film that may be formed between conductive layers, it is possible to produce a highly reliable memory device. In addition, since the lower surface of the round electrode, the outer surface of the column electrode, and the upper and lower surfaces of the disk electrode can be used as an effective area for cell capacitance, it is advantageous for high integration.

It is apparent that the present invention is not limited to the above embodiments, and many modifications are possible by those skilled in the art within the technical idea of the present invention.

Claims (15)

A capacitor comprising a pillar electrode formed in a pillar shape, a cylindrical electrode connected to an upper portion of the pillar electrode and overlapping in two layers, and a storage electrode formed of a disk electrode formed in a disk shape extending in all directions from the middle of the pillar electrode. A semiconductor memory device comprising. Forming a first conductive layer on the entire surface of the semiconductor substrate, forming a predetermined pattern on the first conductive layer in a cell-separated manner, and etching the first conductive layer to be limited to each cell unit. Forming a first storage electrode pattern, forming a first sidewall spacer on a predetermined pattern and sidewalls of the first storage electrode pattern, removing a predetermined pattern, and forming a first sidewall spacer as an etch mask Etching the first conductive layer to a predetermined depth to form a second storage electrode pattern, removing a first sidewall spacer, and forming a second sidewall spacer on the sidewall of the second storage electrode pattern. Forming a storage electrode by anisotropically etching the first conductive layer using the second sidewall spacer as an etch mask, and removing the second sidewall spacer. The manufacturing method of a semiconductor memory device comprising a process. The method of claim 2, wherein the predetermined pattern comprises: forming a first first insulating layer on the entire surface of the first conductive layer; forming a photosensitive film on the entire surface of the first insulating layer; Forming a first photoresist pattern by defining the photoresist, anisotropically etching the first insulating layer using the first photoresist pattern as an etch mask, and isotropic etching using the first isotropic etching The first storage electrode pattern is formed by a process of etching the insulating layer, and the first storage electrode pattern is formed by etching the first conductive layer using the first photoresist pattern as an etching mask after forming a predetermined pattern. Method of manufacturing a semiconductor memory device, characterized in that. The method of claim 3, wherein, before the process of forming the first conductive layer on the semiconductor substrate, a second first insulating layer, a first second insulating layer, and a third first insulating layer are formed on the entire surface of the semiconductor substrate. A method for manufacturing a semiconductor memory device, comprising the step of laminating. The method of manufacturing a semiconductor memory device according to claim 4, wherein a material constituting the first and second sidewall spacers is the same as a material constituting the second insulating layer. The method of manufacturing a semiconductor memory device according to claim 4, further comprising: forming a second second insulating layer on the entire surface of the semiconductor substrate before forming the second first insulating layer. The method of claim 6, wherein the first sidewall spacer is formed of the same material as the material constituting the second insulating layer, and the second sidewall spacer is formed of the same material as the material constituting the first insulating layer. A method of manufacturing a semiconductor memory device. The method of claim 2, wherein the predetermined pattern comprises a step of laminating a third second insulating layer, a fourth first insulating layer, and a photosensitive film on the entire surface of the first conductive layer, wherein the photosensitive film is limited to each cell unit. Forming a second photoresist pattern by patterning; and anisotropically etching the fourth first insulation layer and the third second insulation layer by using the second photoresist pattern as an etching mask. In the first storage electrode pattern, after the anisotropic etching of the fourth first insulating layer and the third second ferroelectric layer using the second photoresist pattern as an etching mask, the fifth first insulating layer is formed on the entire surface of the resultant. Applying a layer; forming a third sidewall spacer on the predetermined pattern sidewall by anisotropically etching the fifth first insulating layer; and remaining on the third sidewall spacer and the first conductive layer. The first conductive layer using the fourth first insulating layer as an etch mask. A method for fabricating a semiconductor memory device being formed by a step of etching. 10. The semiconductor device of claim 8, wherein the fourth second insulating layer, the sixth first insulating layer, the fifth second insulating layer, and the seventh agent are formed on the entire surface of the semiconductor substrate before the step of forming the first conductive layer. (1) A method of manufacturing a semiconductor memory device, further comprising the step of forming an insulating layer. 10. The semiconductor memory device according to claim 9, further comprising a step of forming an eighth first insulating layer and a sixth second insulating layer after the step of forming the fourth second insulating layer. Manufacturing method. The method of claim 10, wherein the forming of the sixth second insulating layer is replaced with the depositing of the same material as the material of the first conductive layer. 3. The method of claim 2, wherein the first and second sidewall spacers are made of the same material as the first insulating layer. 4. The material constituting the first insulating layer and the second insulating layer according to any one of claims 3 to 12, wherein the etch rate is different from that of the material constituting the first conductive layer in any etching process. A method of manufacturing a semiconductor memory device, characterized by using this other material. The method of claim 13, wherein an oxide is used as a material constituting the first insulating layer, and a nitride is used as a material constituting the second insulating layer. The method of claim 13, wherein nitride is used as a material constituting the first insulating layer, and oxide is used as a material constituting the second insulating layer.