KR960000606B1 - Differential quardrature phase-shift keying - Google Patents

Abstract

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Description

Differential quadrature phase shift keying demodulator

1 is a block diagram of a general transmitter for performing DQPSK modulation in a spread spectrum communication system.

2 is a block diagram of an asynchronous receiver using a general DMF performing DQPSK demodulation in a spread spectrum communication system.

3 is a block diagram of a general digital matching filter.

4 is a block diagram of a conventional DQPSK demodulator.

5 is a block diagram of a DQPSK demodulator according to the present invention.

The present invention relates to a receiver of differential quadrature phase-shift keying (hereinafter referred to as "DQPSK") in a digital communication system, and more particularly, to a DQPSK demodulator.

In general, a carrier band digital transmission is a method of converting and transmitting a digital signal into a signal having a given frequency band by modulation. Representative of the carrier-band digital transmission is ASK (Amplitude-Shift Keying) for converting the amplitude of the carrier by a digital signal, FSK (Frequency-Shift Keying) for changing the frequency of the carrier by a digital signal, the digital signal of the phase of the carrier PSK (Phase-Shift Keying) method to change by. In general, the PSK method is used a lot among the three methods, and recently, the QPSK (Quardrature Phase Shift Keying) method is particularly used among the PSK method.

In the QPSK scheme, when the carrier is demodulated at the receiving end, the reference point of the phase is absent and the phase is ambiguous.

In order to solve the above problems, the DQPSK modulation and demodulation method is generally used.

1 is a block diagram of a typical transmitter for performing DQPSK modulation in a spread spectrum communication system.

The serial / parallel converter 102 receives data generated from the data source 101 and converts the data into parallel data. The DPSK encoder 103 differentially encodes the parallel-converted data and outputs them to inputs of one channel and a Q channel, respectively. The spreaders 107 and 108 receive the differentially encoded data and spread the signals by the PN codes generated from the PN generator 106 to output them.

The spread spectrum data is filtered through the first and second LPFs 109 and 110, respectively, and the first mixer 112 is an I-channel mixer, and receives the spread spectrum data from the first LPF 109 and generates a carrier generator. QPSK modulated output by mixing with the carrier of the In-Phase component generated from 111). In addition, the second mixer 113 is a Q-channel mixer, which receives filtered spread data from the second L PF 110 and mixes with the carrier of the 90-degree phase shifted component generated from the carrier generator 111 to perform QPSK modulation. Output

The combiner 115 receives the I, Q channel QPSK modulation outputs from the first and second mixers 112 and 113, respectively, and combines and outputs them. The BPF 120 band-filters and outputs the DQPSK modulated signal input from the combiner 115, and the amplifier AMP 130 amplifies the band-filtered signal and outputs it through the antenna 140.

2 is a block diagram of an asynchronous receiver using a general DMF for performing DQPSK demodulation in a spread spectrum communication system.

First, a low noise amplifier 202 (hereinafter referred to as LNA) amplifies and outputs a signal input through the reception antenna 201. The BPF 203 then filters and outputs the low noise amplified signal. The first mixer 205 receives an RF signal output from the RF frequency generator 204 and mixes the filtered signal and outputs the mixed signal. Thereafter, the second BPF 206 filters the mixed signal and outputs the mixed signal at an intermediate frequency.

Here, if the carrier frequency is fc, the RF frequency is f _RF , and the intermediate frequency is f _IF , the carrier frequency generally forms a relationship of fc = f _RF + f _IF .

The second mixer 209 and the third mixer 210 receive the output signal of the second BPF 206, respectively, and receive the intermediate frequency and the intermediate frequency shifted 90 degrees from the intermediate frequency generator 211, respectively. It is mixed with the signal and output as a band-spread signal with the intermediate frequency removed. In this case, the second mixer 209, which is an I-channel mixer, mixes in-phase components from the intermediate frequency generator 211, and the third mixer 210, which is a Q-channel mixer, mixes orthogonal components that have shifted the intermediate frequency by 90 degrees. do.

Output signals of the second and third mixers 209 and 210 are input and filtered to the first and second LPFs 213 and 214, respectively, and the first and second A / D converters 215 and 216 are filtered. The received signal is input and converted into digital data and output. At this time, the sampling frequency at the time of digital conversion is generally more than twice the spread signal band.

First and second digital matched filters 217 and 218 receive the digitally converted signal, and receive a PN code generated from a PN coder 219 and correlate with the digitally converted signal. Take the relationship and output the despread. In this case, the despreading output has a very large correlation value observed when the digitally converted signal coincides with the PN code, and a very small correlation value is observed when it does not match.

FIG. 3 is a block diagram of a general digital matching filter 217. Referring to FIG. 3, the operation of the digital matching filters 217 and 218 will be described in detail. First, the received input signal is a shift register array; Is shifted every clock. In addition, the PN code input from the PN code generator 219 is stored in the reference PN code register 304. Thus, the output of the shift register array 302 and the output of the reference PN code register 304 are simultaneously multiplied by the first-nth multipliers 205, 306, ... 307 for each clock, respectively, and the result is an adder 308, respectively. The output added to and added to the output is output to the outputs of the first and second digital match filters 217 and 218.

The first and second squarers 220 and 221 receive squares of output signals of the first and second digital matched filters 217 and 218, respectively. Thereafter, the adder 222 receives the squared outputs of the first and second squarers 220 and 221 at the same time, adds them, and outputs them. A square root circuit 223 receives the output of the adder 222 to calculate the square root. The output is then sent to the timing controller 224. In this case, the controller 224 mainly detects the peak value and restores the data clock corresponding to the square root calculated input. That is, during the baseband symbol duration, the highest peak value of the output of the square root circuit 223 is detected and output to the DQPSK demodulator 229. Accordingly, the DQPSK demodulator 229 receives the output signal of the timing controller 224 to sense and store the highest value among the outputs of the first and second digital matched filters 217 and 218. In addition, the timing controller 224 reproduces and outputs a clock for the baseband data when the symbol duration is completed, and controls the baseband data demodulation operation of the DQPSK demodulator 229.

When the output signal of the DMF 217 of the I channel selected for the Kth baseband data in the DQPSK demodulator 229 is I (K), and the output signal of the DMF 218 of the Q channel is Q (K), The I (K) and Q (K) are outputs of the first and second DMFs 217 and 218 when the highest peak value is detected by the controller 224 during the Kth symbol duration, respectively.

Further, if the input to the demodulator is sin (K), the I (K), Q (K) and sin (K) is represented by the following equation.

[Equation 1]

In the above formula

_mod (K): Phase component by DQPSK modulation

_offset (K): phase component by frequency offset of the received signal and local generator

θ: Component due to initial phase difference between received signal and local generator of receiver

Therefore, the DQPSK demodulator output Sout (K) is expressed as a phase difference between successive adjacent samples as in the following equation.

[Equation 2]

In addition, the above 8, 10, 11 formula is expressed as the following formula.

[Equation 3]

For DQPSK modulation, the phase shift Δψ _mod (K) due to modulation is 0 °, 90 °, 180 ° or 270 °, and Δψ _offset (K) is the drift by phase offse t of the transmit / receive local generator during one symbol duration. .

Here, in order to demodulate the DQPSK modulated data using equations 13 and 14, a decision limit must be determined and new coordinates must be set. However, setting the new axes is not easy, and incorrect settings can cause demodulation errors.

Therefore, in order to solve the above problem, the phase is shifted by 45 ° so that the decision limit can be determined only by the X- and Y-terms.

That is, if the phase shift of the 12 equations is further 45 °, the following equation is expressed.

[Equation 4]

Φshift = 45 ° in the case of DQPSK.

But by the 45 degree phase shift in As much signal as Must be scaled to

Therefore, 18 equation and 19 equation When scaled as follows.

[Equation 5]

Hereinafter, a conventional DQPSK demodulator will be described in detail with reference to the configuration and operation of the DQPSK transmission and reception of the digital communication system.

4 is a block diagram of a conventional DQPSK demodulator. The first adder 403 receives an input I (K) of an I channel and an inverting input -Q (K) of a Q channel and adds and outputs the two input signals. do.

The first and second adders 403 and 404 respectively receive the input I (K) of the I channel and the input Q (K) of the Q channel, and add and output the two input signals. Wherein the first and second adders 403, 404 are adders for the 45 degree phase shift given by equations 17, 18 and 19.

The first multiplier 406 receives the output signal of the first adder 403 Multiply the output by The second multiplier 407 receives the output signal of the second adder 404 Multiply the output by The first and second multipliers 406 and 407 output the outputs of the first and second adders 403 and 404. To attenuate Multiplication circuit for scaling by factor.

The first and second delayers 408 and 409 receive and output the output signals of the first and second multipliers 406 and 407.

Thereafter, the third multiplier 410 multiplies and outputs the input I (K) of the I channel and the output of the first delayer 408. The fourth multiplier 411 multiplies and outputs the input Q (K) of the Q channel and the output of the second delayer 409.

In addition, the fifth multiplier 412 receives the output of the second delayer 409 and the input I (K) of the I channel and multiplies the two inputs and outputs the multipliers. The sixth multiplier 413 receives the output of the first delay unit 408 and the input Q (K) of the Q channel and multiplies the two inputs and outputs the multiplied inputs.

The third adder 414 receives the multiplication outputs of the third and fourth multipliers 410 and 411, and adds the two inputs to output the multipliers. Here, the output of the third adder is X '(K) calculated according to the 20 expression.

The fourth adder 415 receives the inverted multiplication output of the fifth multiplier 412 and the multiplication output of the sixth multiplier 413, and adds two inputs.

The data decision unit 420 receives the X '(K) output of the third adder 414 and the Y' (K) output of the fourth adder 415 to finally receive I channel data and Q channel data. Outputs

However, the conventional DQPSK demodulator as described above does not have the addition result signal of the first and second adders 403 and 404 for 45 degree phase shift. Is amplified by a factor of 2 You need to perform the scaling operation twice. Therefore, the conventional DQPSK demodulator described above Two multipliers are needed to perform the double scaling operation, which causes a complicated circuit configuration.

Also, conventional DQPSK demodulator There was a problem that the correction factor could not be corrected by double scaling factor, which may cause distortion of the output signal after scaling.

Accordingly, an object of the present invention is to provide a DQPSK demodulator that simplifies the configuration of a DQPSK demodulation circuit in a DQPSK receiver of a digital communication system.

Another object of the present invention The present invention provides a DQPSK demodulator that performs double scaling to remove distortion of an output signal.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First, the formula for the configuration of the present invention is derived with reference to the above-described formula. When the 17 expressions are represented by the 18 expressions X (K) and the 19 expressions Y (K), they are expressed as follows.

[Equation 6]

Φshift-45 ° in the above formula.

That is, the calculation results of the equations of equation 22 and equation 24 are converted into equations 23 and 25 and the equations of equations 23 and 25 are shifted in phase by φ shift = 45 °, which means that the signal is It is exactly the same except that it is amplified by a factor of two.

That is, the 22-24 equation indicates that the 45-degree phase shift can be achieved by performing the equations 23 and 25 after calculating the 45-degree phase shift by X (K) and Y (K).

FIG. 5 is a block diagram of the DQPSK demodulator according to the present invention. The first delay unit 505 for receiving an I channel input signal I (K) and delaying it for one sampling period and outputting the Q channel input signal Q is shown in FIG. A second delay unit 506 that receives (K) and outputs the delayed signal for one sampling period, and receives the delayed output signal of the I channel input signal I (K) and the first delay unit 505, A multiplier of a first multiplier 503 for outputting a multiplication value of two input signals, a delay output signal of the Q channel input signal Q (K) and the second delay unit 506, and a multiplier of the two input signals A second multiplier 504 that outputs a second multiplier that receives the delayed output signals of the I-channel input signal I (K) and the second delayer 506 and outputs a multiplier of the two input signals; And a delay output signal of the Q channel input signal Q (K) and the first delay unit 505, and a multiplication value of the two input signals. A first multiplier 509 that receives an output of a fourth multiplier 508, a multiplier output of the first multiplier 503, and a multiplier output of the second multiplier 504, and calculates and outputs a sum of the two input signals; ), A second adder 510 that receives a multiplier output of the third multiplier 507 and a multiplier output of the fourth multiplier 50 8, calculates and outputs a difference between the two input signals, and the first multiplier. A third adder 513 that receives the output of the adder 509 and the output of the second adder 510, and computes and outputs the difference between the two input signals, the output of the first adder 509, and the first adder 509. A second adder 510 receives an output of the second adder 510, and outputs a fourth adder 514 that calculates and outputs the sum of the two input signals, an output of the third adder 513, and an output of the fourth adder 514. And a data determiner 517 which finally outputs I channel data and Q channel data.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the configuration of FIG. 5 described above.

The first multiplier 503 multiplies and outputs the I (K) of the current input sample of the I channel and the I (K-1) of the previous sample from the first delay unit 505. The second multiplier 504 multiplies and outputs Q (K) of the current input sample of the Q channel and Q (K-1) of the previous sample from the second delay unit 506.

Thereafter, the first adder 509 receives the multiplication output of the first multiplier 503 and the second multiplier 504 and adds the multiplied outputs. In this case, the output of the first adder 509 is X (K), and the output expression is according to the 13th expression.

The third multiplier 507 multiplies and outputs I (K) of the current input sample of the I channel and Q (K-1) of the previous sample from the second delay unit 506. The fourth multiplier 508 multiplies and outputs Q (K) of the current input sample of the Q channel and I (K-1) of the previous sample from the first delay unit 505.

Thereafter, the second adder 510 receives the multiplication output of the third multiplier 507 and the fourth multiplier 508 and outputs a difference between the two input signals. In this case, the output of the second adder 510 is Y (K), and the output equation is according to the above equation (14).

The third adder 513 receives the X (K) and the Y (K), calculates the difference between the two signals, and outputs X '(K) according to the equation of the equation 23, which is further shifted by 45 degrees. .

The fourth adder 514 receives the X (K) and the Y (K), calculates the sum of the two signals, and outputs Y '(K) according to the equation of the 25 equation which is further shifted by 45 degrees. .

The data determiner 517 receives the X '(K) output of the third adder 513 and the Y' (K) output of the fourth adder 514 and finally outputs I channel data and Q channel data. do. The data determiner 517 may be a data determiner 4 20 used in a conventional DQPSK demodulator.

According to the above, the present invention is as shown in equations 23 and 25 above. It does not eliminate the factor of, but there is no effect on signal distortion or data demodulation.

Therefore, as described above, the present invention simplifies the configuration because the two multipliers 406 and 407, which are essential components of the conventional DQPSK demodulator, are not required as the 45 degree phase shift is performed at the rear end.

Also Since scaling is not performed to eliminate the factor of, there is no signal distortion or data demodulation error that may occur during scaling.

Claims (1)

In a differential quadrature phase shift keying receiver of a digital communication system, a first delay means for receiving an I-channel input signal I (K) and delaying it for one sampling period and receiving a Q-channel input signal Q (K) is received. A second delay means for delaying output for one sampling period and a delay output signal between the I-channel input signal I (K) and the first delay means and receiving a delayed output signal for outputting a multiplication value of the two input signals; A multiplication means, a second multiplication means for receiving a delay output signal of the Q channel input signal Q (K) and the second delay means, and outputting a multiplication value of the two input signals, and the I channel input signal I ( K) and a third multiplication means for receiving a delay output signal of the second delay means and outputting a multiplication value of the two input signals, and a delay output of the Q channel input signal Q (K) and the first delay means. Receiving a signal and multiplying the two input signals A fourth multiplication means for outputting, a multiplication output of the first multiplication means and a multiplication output of the second multiplier, the first adding means for calculating and outputting the sum of the two input signals, and the third multiplication means of Receiving a multiplication output and a multiplication output of the fourth multiplication means, receiving a second adding means for calculating and outputting a difference between the two input signals, an output of the first adding means and an output of the second adding means, Third adding means for calculating and outputting a difference between the two input signals, fourth adding means for receiving an output of the first adding means and an output of the second adding means, and calculating and outputting a sum of the two input signals. And data determining means for receiving the output of the third adding means and the output of the fourth adding means and outputting I channel data and Q channel data.