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KR950035076A - Frequency synthesizer - Google Patents

Frequency synthesizer Download PDF

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Publication number
KR950035076A
KR950035076A KR1019950010085A KR19950010085A KR950035076A KR 950035076 A KR950035076 A KR 950035076A KR 1019950010085 A KR1019950010085 A KR 1019950010085A KR 19950010085 A KR19950010085 A KR 19950010085A KR 950035076 A KR950035076 A KR 950035076A
Authority
KR
South Korea
Prior art keywords
frequency
dividers
controlled oscillator
frequency signal
divider
Prior art date
Application number
KR1019950010085A
Other languages
Korean (ko)
Other versions
KR100343078B1 (en
Inventor
이사오 다께우찌
Original Assignee
오오가 노리오
소니 가부시끼가이샤
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Application filed by 오오가 노리오, 소니 가부시끼가이샤 filed Critical 오오가 노리오
Publication of KR950035076A publication Critical patent/KR950035076A/en
Application granted granted Critical
Publication of KR100343078B1 publication Critical patent/KR100343078B1/en

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03J—TUNING RESONANT CIRCUITS; SELECTING RESONANT CIRCUITS
    • H03J7/00—Automatic frequency control; Automatic scanning over a band of frequencies
    • H03J7/18—Automatic scanning over a band of frequencies
    • H03J7/20—Automatic scanning over a band of frequencies where the scanning is accomplished by varying the electrical characteristics of a non-mechanically adjustable element
    • H03J7/28—Automatic scanning over a band of frequencies where the scanning is accomplished by varying the electrical characteristics of a non-mechanically adjustable element using counters or frequency dividers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
    • H03L7/1974—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

간단한 구성으로 기준 신호의 정수배 이외의 주파수 신호를 출력시킬 수 있는 주파수 신세사이저를 제공하는 것을 목적으로 한다.It is an object of the present invention to provide a frequency synthesizer capable of outputting a frequency signal other than an integer multiple of a reference signal with a simple configuration.

전압 제어 발진기(5)와, 이 전압 제어 발진기(5)의 출력을 분주비 1/N 또는 1/(N+1)[N은 임의의 정수]로 분주할 수 있는 복수개의 분주기(14,15)와, 이 각 분주기(14,15)의 분주비 제어 수단(16)과, 기준 주파수 신호 공급 수단(1)로부터의 신호와 분주기(14,15)의 분주 신호와의 위상차를 개별적으로 검출하는 복수개의 위상 비교기(11,112)와, 이 위상 비교기(14,15)의 비교 오차 신호를 가산하는 가산기(13)과, 이 가산기(13)의 가산 출력을 직류화하여 전압 제어 발진기(5)에 공급하는 필터(4)로 구성되고, 제어 수단(16)의 제어로 각 분주기(14,15)의 분주비를 1/N 또는 1/(N+1)로 주기적으로 각각이 다른 타이밍에서 변화되도록 했다.A plurality of dividers 14 capable of dividing the voltage controlled oscillator 5 and the output of the voltage controlled oscillator 5 with a division ratio 1 / N or 1 / (N + 1) [N is an arbitrary integer]. 15 and a phase difference between the frequency division ratio control means 16 of each of the frequency dividers 14 and 15, and the signal from the reference frequency signal supply means 1 and the frequency division signals of the frequency dividers 14 and 15, respectively. A plurality of phase comparators (11, 112) detected by the step, an adder (13) for adding the comparison error signals of the phase comparators (14, 15), and an adder output of the adder (13) by direct current to the voltage controlled oscillator (5) Is a filter 4 to be supplied to the filter), and the frequency division ratios of the frequency dividers 14 and 15 are controlled to 1 / N or 1 / (N + 1) periodically under the control of the control means 16, respectively. To change.

Description

주파수 신세사이저Frequency synthesizer

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명의 일실시예에 따른 ½분주 신세사이저를 도시한 구성도, 제2도는 제1도 구성의 신세사이저의 동작 타이밍도, 제3도는 본 발명의 다른 실시예에 따른 ¼분주 신세사이저를 도시한 구성도, 제4도는 제3도 구성의 신세사이저의 동작 타이밍도.FIG. 1 is a block diagram showing a ½ dispense synthesizer according to an embodiment of the present invention, FIG. 2 is a timing diagram of the synthesizer of FIG. 1, and FIG. 3 is a quarter dispense synthesizer according to another embodiment of the present invention. 4 is a timing diagram of the synthesizer of FIG.

Claims (3)

전압 제어 발진기, 상기 전압 제어 발진기의 출력을 분주비 1/N 또는 1/(N+1)[N은 임의의 정수]로 분주할 수 있는 M[M은 2이상의 정수]의 분주기, 상기 M개의 분주기의 분주비를 제어하는 제어 수단, 기준이 되는 주파수 신호의 공급 수단, 상기 공급 수단으로부터 공급되는 기준 주파수 신호와 상기 M개의 분주기의 분주 신호와의 위상차를 개별적으로 검출하는 M개의 위상 비교기, 상기 M개의 위상 비교기의 비교 오차 신호를 가산하는 가산기 및 상기 가산기의 가산 출력을 직류화하여 상기 전압 제어 발진기에 공급하는 필터로 구성되고, 상기 제어 수단의 제어로 상기 M개의 분주기의 분주비를 1/N 또는 1/(N+1)로 주기적으로 변환시킴과 동시에, 이 분주비가 변화하는 1주기 중에 분주비가 1/N 또는 1/(N+1)이 되는 타이밍을 각 분주기마다 변화시키도록 한 것을 특징으로 하는 주파수 신세사이저.A voltage controlled oscillator, a divider of M [M is an integer greater than or equal to 2], where the output of the voltage controlled oscillator can be divided by a division ratio of 1 / N or 1 / (N + 1) [N is an arbitrary integer], wherein M Control means for controlling the division ratio of the four frequency dividers, the supply means for the reference frequency signal, and the M phases for individually detecting a phase difference between the reference frequency signal supplied from the supply means and the frequency division signals of the M frequency dividers. A comparator, an adder for adding the comparison error signals of the M phase comparators, and a filter for converting the adder output of the adder into a DC and supplying the voltage controlled oscillator, and the division of the M dividers under the control of the control means. The period is changed periodically to 1 / N or 1 / (N + 1), and the timing at which the division ratio becomes 1 / N or 1 / (N + 1) during each period in which the division ratio changes is set for each divider. To make changes Frequency of sinsesayijeo. 제1항에 있어서, 분주기를 2개로 하고, 한쪽의 분주기로 분주비를 1/N 또는 1/(N+1)로 교대로 변환시키고, 다른쪽의 분지기로 분주비를 1/(N+1)과 1/N로 교대로 변화시키며, 기준 주파수 신호의 (정수+0.5)배의 주파수 신호를 전압 제어 발진기가 출력하도록 한 것을 특징으로 하는 주파수 신세사이저.The frequency divider is divided into two dividers, and the dividing ratio is alternately converted into 1 / N or 1 / (N + 1) by one divider, and the dividing ratio is changed into 1 / (N by another divider. A frequency synthesizer characterized in that the voltage-controlled oscillator outputs a frequency signal (integer +0.5) times the reference frequency signal, alternately changed to +1) and 1 / N. 제1항에 있어서, 분주기를 4개로 하고, 이 4개의 분주기의 분주비를 기준 주파수 신호의 4주기에 1회씩 각각이 다른 타이밍에서 1/(N+1)로 하고, 그 밖의 타이밍에서 1/N으로 하며, 기준 주파수 신호의(정수=0.25)배의 주파수 신호를 전압 제어 발진기가 출력하도록 한 것을 특징으로 한 주파수 신세사이저.The frequency divider is set to four, and the division ratios of the four frequency dividers are set to 1 / (N + 1) at different timings once every four periods of the reference frequency signal, and at other timings. A frequency synthesizer characterized in that the voltage-controlled oscillator outputs a frequency signal equal to (integer = 0.25) times the reference frequency signal. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950010085A 1994-04-28 1995-04-27 Frequency synthesizer KR100343078B1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP94-092557 1994-04-28
JP6092557A JPH07297713A (en) 1994-04-28 1994-04-28 Frequency synthesizer
JP94-92557 1994-04-28

Publications (2)

Publication Number Publication Date
KR950035076A true KR950035076A (en) 1995-12-30
KR100343078B1 KR100343078B1 (en) 2002-12-16

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Application Number Title Priority Date Filing Date
KR1019950010085A KR100343078B1 (en) 1994-04-28 1995-04-27 Frequency synthesizer

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JP (1) JPH07297713A (en)
KR (1) KR100343078B1 (en)
CN (1) CN1099763C (en)
GB (1) GB2288931B (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19816656C2 (en) * 1998-04-15 2000-08-10 Suedwestrundfunk Anstalt Des O Method of generating frequencies
WO2000045515A1 (en) * 1999-01-29 2000-08-03 Sanyo Electric Co., Ltd. Pll apparatus and variable frequency-division device
JP5229081B2 (en) * 2009-04-10 2013-07-03 富士通株式会社 Semiconductor device
WO2012157234A1 (en) * 2011-05-18 2012-11-22 旭化成エレクトロニクス株式会社 Accumulator type fractional-n pll synthesizer and control method thereof
GB2580631B (en) * 2019-01-17 2022-04-27 Cml Microcircuits Uk Ltd Phase-locked loop circuitry

Also Published As

Publication number Publication date
GB9508511D0 (en) 1995-06-14
JPH07297713A (en) 1995-11-10
GB2288931A (en) 1995-11-01
CN1113053A (en) 1995-12-06
CN1099763C (en) 2003-01-22
GB2288931B (en) 1998-09-23
KR100343078B1 (en) 2002-12-16

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