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KR950034612A - 반도체 구조물 및 그 제조 방법 - Google Patents

반도체 구조물 및 그 제조 방법 Download PDF

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Publication number
KR950034612A
KR950034612A KR1019950012365A KR19950012365A KR950034612A KR 950034612 A KR950034612 A KR 950034612A KR 1019950012365 A KR1019950012365 A KR 1019950012365A KR 19950012365 A KR19950012365 A KR 19950012365A KR 950034612 A KR950034612 A KR 950034612A
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KR
South Korea
Prior art keywords
manufacturing
semiconductor structure
semiconductor
Prior art date
Application number
KR1019950012365A
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English (en)
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KR100187870B1 (ko
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of KR950034612A publication Critical patent/KR950034612A/ko
Application granted granted Critical
Publication of KR100187870B1 publication Critical patent/KR100187870B1/ko

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/661—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation
    • H10D64/662—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures
    • H10D64/663—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures the additional layers comprising a silicide layer contacting the layer of silicon, e.g. polycide gates
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/90—MOSFET type gate sidewall insulating spacer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/903—FET configuration adapted for use as static memory cell
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/915—Active solid-state devices, e.g. transistors, solid-state diodes with titanium nitride portion or region

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
KR1019950012365A 1994-05-19 1995-05-18 반도체 구조물 및 그 제조 방법 KR100187870B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/245,997 US5496771A (en) 1994-05-19 1994-05-19 Method of making overpass mask/insulator for local interconnects
US8/245,997 1994-05-19

Publications (2)

Publication Number Publication Date
KR950034612A true KR950034612A (ko) 1995-12-28
KR100187870B1 KR100187870B1 (ko) 1999-06-01

Family

ID=22928937

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950012365A KR100187870B1 (ko) 1994-05-19 1995-05-18 반도체 구조물 및 그 제조 방법

Country Status (4)

Country Link
US (2) US5496771A (ko)
EP (1) EP0683514A1 (ko)
JP (1) JP3245004B2 (ko)
KR (1) KR100187870B1 (ko)

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US5850096A (en) * 1994-02-25 1998-12-15 Fujitsu Limited Enhanced semiconductor integrated circuit device with a memory array and a peripheral circuit
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JPH09129732A (ja) * 1995-10-31 1997-05-16 Nec Corp 半導体装置の製造方法
JP2924763B2 (ja) * 1996-02-28 1999-07-26 日本電気株式会社 半導体装置の製造方法
US5723380A (en) * 1996-03-25 1998-03-03 Taiwan Semiconductor Manufacturing Company, Ltd. Method of approach to improve metal lithography and via-plug integration
JP3607424B2 (ja) * 1996-07-12 2005-01-05 株式会社東芝 半導体装置及びその製造方法
US6309971B1 (en) 1996-08-01 2001-10-30 Cypress Semiconductor Corporation Hot metallization process
US5977638A (en) * 1996-11-21 1999-11-02 Cypress Semiconductor Corp. Edge metal for interconnect layers
US5861676A (en) * 1996-11-27 1999-01-19 Cypress Semiconductor Corp. Method of forming robust interconnect and contact structures in a semiconductor and/or integrated circuit
US7067406B2 (en) * 1997-03-31 2006-06-27 Intel Corporation Thermal conducting trench in a semiconductor structure and method for forming the same
JP3077630B2 (ja) * 1997-06-05 2000-08-14 日本電気株式会社 半導体装置およびその製造方法
US6057227A (en) * 1997-06-23 2000-05-02 Vlsi Technology, Inc. Oxide etch stop techniques for uniform damascene trench depth
US6184083B1 (en) * 1997-06-30 2001-02-06 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
US6207543B1 (en) 1997-06-30 2001-03-27 Vlsi Technology, Inc. Metallization technique for gate electrodes and local interconnects
US6074921A (en) * 1997-06-30 2000-06-13 Vlsi Technology, Inc. Self-aligned processing of semiconductor device features
US6420273B1 (en) 1997-06-30 2002-07-16 Koninklijke Philips Electronics N.V. Self-aligned etch-stop layer formation for semiconductor devices
US5953612A (en) * 1997-06-30 1999-09-14 Vlsi Technology, Inc. Self-aligned silicidation technique to independently form silicides of different thickness on a semiconductor device
US5807779A (en) * 1997-07-30 1998-09-15 Taiwan Semiconductor Manufacturing Company Ltd. Method of making tungsten local interconnect using a silicon nitride capped self-aligned contact process
NL1008773C2 (nl) * 1998-04-01 1999-10-04 United Microelectronics Corp Werkwijze voor het vervaardigen van zelfuitgerichte lokale verbindingen en contacten.
US6221704B1 (en) * 1998-06-03 2001-04-24 International Business Machines Corporation Process for fabricating short channel field effect transistor with a highly conductive gate
US6174803B1 (en) 1998-09-16 2001-01-16 Vsli Technology Integrated circuit device interconnection techniques
US6399432B1 (en) 1998-11-24 2002-06-04 Philips Semiconductors Inc. Process to control poly silicon profiles in a dual doped poly silicon process
US6271596B1 (en) 1999-01-12 2001-08-07 Agere Systems Guardian Corp. Damascene capacitors for integrated circuits
TW471116B (en) * 1999-01-22 2002-01-01 United Microelectronics Corp Contact isolation structure and the manufacturing method thereof
US6221708B1 (en) 1999-07-23 2001-04-24 Micron Technology, Inc. Field effect transistor assemblies, integrated circuitry, and methods of forming field effect transistors and integrated circuitry
US6281084B1 (en) * 1999-08-31 2001-08-28 Infineon Technologies Corporation Disposable spacers for improved array gapfill in high density DRAMs
US6614056B1 (en) 1999-12-01 2003-09-02 Cree Lighting Company Scalable led with improved current spreading structures
US6399512B1 (en) 2000-06-15 2002-06-04 Cypress Semiconductor Corporation Method of making metallization and contact structures in an integrated circuit comprising an etch stop layer
US6635566B1 (en) 2000-06-15 2003-10-21 Cypress Semiconductor Corporation Method of making metallization and contact structures in an integrated circuit
JP2002009149A (ja) * 2000-06-20 2002-01-11 Toshiba Corp 半導体装置およびその製造方法
US6649480B2 (en) * 2000-12-04 2003-11-18 Amberwave Systems Corporation Method of fabricating CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs
US6830976B2 (en) * 2001-03-02 2004-12-14 Amberwave Systems Corproation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
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US6548347B2 (en) 2001-04-12 2003-04-15 Micron Technology, Inc. Method of forming minimally spaced word lines
US20020155261A1 (en) * 2001-04-24 2002-10-24 Sung-Hsiung Wang Method for forming interconnect structure with low dielectric constant
US7615829B2 (en) * 2002-06-07 2009-11-10 Amberwave Systems Corporation Elevated source and drain elements for strained-channel heterojuntion field-effect transistors
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US6960781B2 (en) * 2003-03-07 2005-11-01 Amberwave Systems Corporation Shallow trench isolation process
JP4610205B2 (ja) * 2004-02-18 2011-01-12 株式会社リコー 半導体装置
US7879663B2 (en) * 2007-03-08 2011-02-01 Freescale Semiconductor, Inc. Trench formation in a semiconductor material
US7910418B2 (en) * 2008-01-30 2011-03-22 International Business Machines Corporation Complementary metal gate dense interconnect and method of manufacturing
US9817822B2 (en) 2008-02-07 2017-11-14 International Business Machines Corporation Managing white space in a portal web page
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US9330983B1 (en) 2015-02-16 2016-05-03 International Business Machines Corporation CMOS NFET and PFET comparable spacer width
US11177171B2 (en) * 2019-10-01 2021-11-16 International Business Machines Corporation Encapsulated top via interconnects

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Also Published As

Publication number Publication date
EP0683514A1 (en) 1995-11-22
KR100187870B1 (ko) 1999-06-01
JP3245004B2 (ja) 2002-01-07
JPH0864822A (ja) 1996-03-08
US5677563A (en) 1997-10-14
US5496771A (en) 1996-03-05

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