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KR950026276A - Equalizer with shorter convergence time due to parallel processing of taps - Google Patents

Equalizer with shorter convergence time due to parallel processing of taps Download PDF

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Publication number
KR950026276A
KR950026276A KR1019940003301A KR19940003301A KR950026276A KR 950026276 A KR950026276 A KR 950026276A KR 1019940003301 A KR1019940003301 A KR 1019940003301A KR 19940003301 A KR19940003301 A KR 19940003301A KR 950026276 A KR950026276 A KR 950026276A
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KR
South Korea
Prior art keywords
filter
equalization
signal
coefficient
taps
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KR1019940003301A
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Korean (ko)
Inventor
김영상
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배순훈
대우전자 주식회사
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Priority to KR1019940003301A priority Critical patent/KR950026276A/en
Publication of KR950026276A publication Critical patent/KR950026276A/en

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  • Filters That Use Time-Delay Elements (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)

Abstract

본 발명에 따른 필터계수를 사용하여 입력받은 왜곡신호를 보정하여 등화필터링된 신호를 출력하는 등화필터부와, 상기 등화필터부로 부터 제공된 등화필터링된 신호를 입력 받아 왜곡신호와 원신호의 차인채널에러를 검출해 내는 에러 계산부와, 상기 에러 계산부로부터 제공되는 채널에러에 의해 갱신된 필터계수를 출력하는 계수 갱신 부를 갖는, 등화필터링에 필요한 탭(Tap)의 병렬처리에 의해 수렴시간이 단축된 등화기는, 상기 등화필터부가, 기설정된 갯수의 탭을 가지며, 입력된 왜곡신호를 제1필터계수를 사용하여 등화필터링하는 다수개의 제1등화필터수단과, 왜곡신호 및 필터 계수를 기설정된 기간동안 지연시키기 위해 다수개의 지연수단과, 기설정된 갯수의 탭을 가지며, 상기 지연수단에 의해 기설정된 기간 동안 지연된 후 입력된 왜곡신호를 상기 지연수단에 의해 기설정된 기간동안 지연된 후 제공되는 제2필터계수를 사용하여 등화필터링하는 다수개의 제2등화필터수단과, 상기 제1 및 제2등화 필터 수단으로부터 입력된 등화필터링된 신호들을 가산하는 다수개의 제1가산기 다수개의 제2가산기를 포함한다. 따라서, 본 등화기는 등화필터링에 필요한 탭을 병렬처리하여 수렴 시간을 단축시킬 수 있다.An equalization filter unit for correcting the distortion signal received using the filter coefficient according to the present invention and outputting an equalized filtered signal; The convergence time is shortened by parallel processing of taps required for equalization filtering, having an error calculating section for detecting a signal and a coefficient updating section for outputting a filter coefficient updated by a channel error provided from the error calculating section. The equalizer includes a plurality of first equalization filter means for equalizing and filtering the input distortion signal by using the first filter coefficient, wherein the equalization filter unit has a predetermined number of taps, and the distortion signal and the filter coefficient for a predetermined period. A distortion input having a plurality of delay means for delaying and a predetermined number of taps, and delayed for a predetermined period by said delay means A plurality of second equalization filter means for equalizing and filtering the signal using a second filter coefficient provided after the signal is delayed by the delay means for a predetermined period, and the equalized filtered signal input from the first and second equalization filter means And a plurality of first adders for adding them. Therefore, the equalizer can shorten the convergence time by parallelizing the taps required for equalization filtering.

Description

탭의 병렬처리에 의해 수렴시간이 단축된 등화기Equalizer with shorter convergence time due to parallel processing of taps

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 종래 등화기의 등화 필터부를 도시한 블럭도,2 is a block diagram showing an equalization filter part of a conventional equalizer;

제3도는 본 발명에 따른 등화기의 블럭도.3 is a block diagram of an equalizer according to the invention.

Claims (2)

필터계수를 사용하여 입력받은 왜곡신호를 보정하여 등화필터링된 신호를 출력하는 등화필터부(300)와 ; 상기 등화필터부(300)로 부터 제공된 등화필터링된 신호를 입력 받아 왜곡신호와 원신호의 차인채널에러를 검출해 내는 에러 계산부(350)와 ;상기 에러 계산부(350)로부터 제공되는 채널에러에 의해 갱신된 제1 및 제2 필터계수를 출력하는 계수 갱신부(400)를 갖는, 등화필터링에 필요한 탭(Tap)의 병렬처리에 의해 수렴시간이 단축된 등화기는, 상기 등화필터부(300)가, 기설정된 갯수의 탭을 가지며, 입력된 왜곡신호를 제1필터계수를 사용하여 등화필터링하는 다수개의 제1등화필터수단(30, 32, 34, 36)과, 왜곡신호 및 필터 계수를 기설정된 기간동안 지연시키기 위해 다수개의 지연수단(38, 39)과, 기설정된 갯수의 탭을 가지며, 상기 지연수단에 의해 기설정된 기간 동안 지연된 후 입력된 왜곡신호를 상기 지연수단에 의해 기설정된 기간동안 지연된 후 제공되는 제2필터계수를 사용하여 등화필터링하는 다수개의 제2등화필터수단과, 상기 제1 및 제2등화필터수단(31, 33, 35, 37)과 상기 제1 및 2 등화필터수단으로부터 입력된 등화필터링된 신호들을 가산하는 다수개의 제1가산기(301, 302, 303, 304)와 ; 상기 제1가산기(301, 302, 303, 304)로부터 제공된 신호를 가산하는 다수개의 제2가산기(305, 306)를 포함하는 것을 특징으로 하는 등화기.An equalization filter unit 300 for outputting an equalized filtered signal by correcting an input distortion signal using a filter coefficient; An error calculator 350 that detects a channel error between the distortion signal and the original signal by receiving the equalized filtered signal provided from the equalization filter unit 300; and a channel error provided from the error calculator 350. The equalizer having a coefficient update unit 400 for outputting the first and second filter coefficients updated by means of which the convergence time is shortened by parallel processing of taps required for equalization filtering is the equalization filter unit 300. A plurality of first equalizing filter means (30, 32, 34, 36) for equalizing and filtering the input distortion signal using the first filter coefficient, and having a predetermined number of taps. A plurality of delay means (38, 39) and a predetermined number of taps for delaying for a predetermined period of time, and the delayed signal input after being delayed for a predetermined period by the delay means for the predetermined period Provided after the A plurality of second equalization filter means for equalizing filtering using a second filter coefficient, the first and second equalizing filter means 31, 33, 35, 37, and equalization input from the first and second equalizing filter means A plurality of first adders (301, 302, 303, 304) for adding the filtered signals; And a plurality of second adders (305, 306) for adding signals provided from said first adders (301, 302, 303, 304). 제1항에 있어서, 상기 계수 갱신부(400)가 상기 에러 계산부(350)으로 부터 제공되는 채널에러와 상기 지연수단(38, 39)으로부터 제공되는 지연신호를 입력받아 제1필터 계수를 출력하는 제1계수 갱신 수단과 ; 상기에러계산부(350)으로부터 제공되는 채널에러와 상기 지연수단(38, 39)으로 부터 제공되는 지연신호를 입력받아 제2필터계수를 출력하는 제2계수 갱신수단을 포함하는 것을 특징으로 하는 등화기.The method of claim 1, wherein the coefficient updater 400 receives the channel error provided from the error calculator 350 and the delay signals provided from the delay means 38, 39 to output the first filter coefficients. First coefficient updating means for performing; Equalization, characterized in that it comprises a second coefficient updating means for receiving the channel error provided from the error calculator 350 and the delay signal provided from the delay means (38, 39) and outputs a second filter coefficient group. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940003301A 1994-02-24 1994-02-24 Equalizer with shorter convergence time due to parallel processing of taps KR950026276A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100714452B1 (en) * 2005-12-09 2007-05-04 한국전자통신연구원 Equalizer and its method for parallel processing structure for DS-CDMAA system
US8009728B2 (en) 2005-12-09 2011-08-30 Electronics And Telecommunications Research Institute Parallel equalizer for DS-CDMA UWB system and method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100714452B1 (en) * 2005-12-09 2007-05-04 한국전자통신연구원 Equalizer and its method for parallel processing structure for DS-CDMAA system
US8009728B2 (en) 2005-12-09 2011-08-30 Electronics And Telecommunications Research Institute Parallel equalizer for DS-CDMA UWB system and method thereof

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