KR950026276A - Equalizer with shorter convergence time due to parallel processing of taps - Google Patents
Equalizer with shorter convergence time due to parallel processing of taps Download PDFInfo
- Publication number
- KR950026276A KR950026276A KR1019940003301A KR19940003301A KR950026276A KR 950026276 A KR950026276 A KR 950026276A KR 1019940003301 A KR1019940003301 A KR 1019940003301A KR 19940003301 A KR19940003301 A KR 19940003301A KR 950026276 A KR950026276 A KR 950026276A
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- KR
- South Korea
- Prior art keywords
- filter
- equalization
- signal
- coefficient
- taps
- Prior art date
Links
- 238000001914 filtration Methods 0.000 claims abstract 7
- 230000003111 delayed effect Effects 0.000 claims abstract 4
- 238000000034 method Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Filters That Use Time-Delay Elements (AREA)
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
Abstract
본 발명에 따른 필터계수를 사용하여 입력받은 왜곡신호를 보정하여 등화필터링된 신호를 출력하는 등화필터부와, 상기 등화필터부로 부터 제공된 등화필터링된 신호를 입력 받아 왜곡신호와 원신호의 차인채널에러를 검출해 내는 에러 계산부와, 상기 에러 계산부로부터 제공되는 채널에러에 의해 갱신된 필터계수를 출력하는 계수 갱신 부를 갖는, 등화필터링에 필요한 탭(Tap)의 병렬처리에 의해 수렴시간이 단축된 등화기는, 상기 등화필터부가, 기설정된 갯수의 탭을 가지며, 입력된 왜곡신호를 제1필터계수를 사용하여 등화필터링하는 다수개의 제1등화필터수단과, 왜곡신호 및 필터 계수를 기설정된 기간동안 지연시키기 위해 다수개의 지연수단과, 기설정된 갯수의 탭을 가지며, 상기 지연수단에 의해 기설정된 기간 동안 지연된 후 입력된 왜곡신호를 상기 지연수단에 의해 기설정된 기간동안 지연된 후 제공되는 제2필터계수를 사용하여 등화필터링하는 다수개의 제2등화필터수단과, 상기 제1 및 제2등화 필터 수단으로부터 입력된 등화필터링된 신호들을 가산하는 다수개의 제1가산기 다수개의 제2가산기를 포함한다. 따라서, 본 등화기는 등화필터링에 필요한 탭을 병렬처리하여 수렴 시간을 단축시킬 수 있다.An equalization filter unit for correcting the distortion signal received using the filter coefficient according to the present invention and outputting an equalized filtered signal; The convergence time is shortened by parallel processing of taps required for equalization filtering, having an error calculating section for detecting a signal and a coefficient updating section for outputting a filter coefficient updated by a channel error provided from the error calculating section. The equalizer includes a plurality of first equalization filter means for equalizing and filtering the input distortion signal by using the first filter coefficient, wherein the equalization filter unit has a predetermined number of taps, and the distortion signal and the filter coefficient for a predetermined period. A distortion input having a plurality of delay means for delaying and a predetermined number of taps, and delayed for a predetermined period by said delay means A plurality of second equalization filter means for equalizing and filtering the signal using a second filter coefficient provided after the signal is delayed by the delay means for a predetermined period, and the equalized filtered signal input from the first and second equalization filter means And a plurality of first adders for adding them. Therefore, the equalizer can shorten the convergence time by parallelizing the taps required for equalization filtering.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제2도는 종래 등화기의 등화 필터부를 도시한 블럭도,2 is a block diagram showing an equalization filter part of a conventional equalizer;
제3도는 본 발명에 따른 등화기의 블럭도.3 is a block diagram of an equalizer according to the invention.
Claims (2)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019940003301A KR950026276A (en) | 1994-02-24 | 1994-02-24 | Equalizer with shorter convergence time due to parallel processing of taps |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019940003301A KR950026276A (en) | 1994-02-24 | 1994-02-24 | Equalizer with shorter convergence time due to parallel processing of taps |
Publications (1)
Publication Number | Publication Date |
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KR950026276A true KR950026276A (en) | 1995-09-18 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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KR1019940003301A KR950026276A (en) | 1994-02-24 | 1994-02-24 | Equalizer with shorter convergence time due to parallel processing of taps |
Country Status (1)
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KR (1) | KR950026276A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100714452B1 (en) * | 2005-12-09 | 2007-05-04 | 한국전자통신연구원 | Equalizer and its method for parallel processing structure for DS-CDMAA system |
US8009728B2 (en) | 2005-12-09 | 2011-08-30 | Electronics And Telecommunications Research Institute | Parallel equalizer for DS-CDMA UWB system and method thereof |
-
1994
- 1994-02-24 KR KR1019940003301A patent/KR950026276A/en not_active Application Discontinuation
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100714452B1 (en) * | 2005-12-09 | 2007-05-04 | 한국전자통신연구원 | Equalizer and its method for parallel processing structure for DS-CDMAA system |
US8009728B2 (en) | 2005-12-09 | 2011-08-30 | Electronics And Telecommunications Research Institute | Parallel equalizer for DS-CDMA UWB system and method thereof |
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