KR950022455A

KR950022455A - Output buffer type ATM switching system

Info

Publication number: KR950022455A
Application number: KR1019930031685A
Authority: KR
Inventors: 최재항; 홍진표
Original assignee: 정장호; 엘지정보통신 주식회사
Priority date: 1993-12-30
Filing date: 1993-12-30
Publication date: 1995-07-28

Abstract

본 발명은 출력버퍼형 ATM스위칭시스템에 관한 것으로, 사설교환망용 ATM스위칭 시스템으로 활용 가능하므로 동화상, 음성, 및 데이타를 제공하는 광대역 ISDN을 구축할 수 있다.The present invention relates to an output buffer type ATM switching system. Since the present invention can be used as an ATM switching system for a private switching network, it is possible to construct a broadband ISDN for providing moving picture, voice, and data.

Description

Output buffer type ATM switching system

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명에 의한 출력버퍼형 ATM스위칭 시스템 구성도.1 is a block diagram of an output buffer type ATM switching system according to the present invention.

제2도 및 제3도는 제1도에 도시된 포트 프로세서의 상세구성도.2 and 3 are detailed configuration diagrams of the port processor shown in FIG.

제4도는 제1도에 도시된 FIFO부의 상세구성도.4 is a detailed configuration diagram of the FIFO unit shown in FIG.

Claims

An ATM switching system comprising: a plurality of first port processors for converting a data cell supplied from the outside into a data cell format in the system and outputting the data cell in parallel; A plurality of multiplexing units 20 ₁ to 20 _{8 for} multiplexing and outputting data cells supplied from the port processors 10 ₁ to 10 ₁₆ in parallel; A plurality of FIFO units 30 ₁ to 30 ₁₆ for temporarily storing data cells supplied from the multiplexing units 20 and 208 and outputting the data cells according to their priorities; A plurality of second port processors 40 ₁ to 40 ₁₆ for converting and outputting the FIFO unit 30 ₁ to 30 ₁₆ in a transmission format; And a control processor 50 for supplying control information to the first port processors 40 ₁ to 40 ₁₆ , the FIFO units 30 ₁ to 30 ₁₆ , and the second port processors 40 ₁ to 40 ₁₆ . Output buffer type ATM switching system.

According to claim 1, Each of the first port processor (10 ₁ ~ 10 ₁₆ ) is a UNI unit 11 for extracting only the switching data cells from the data cells supplied from the outside, supplied from the UNI unit 11 A header for storing VPI / VCI values in parallel in the data cells from the receiving FIFO 12 according to the control information of the control processor 50 and temporarily storing and outputting the data cells. Output buffer type ATM switching system comprising a conversion unit (14).

The control unit (100) of claim 1, wherein each of the FIFO units (30 ₁ to 30 ₁₆ ) includes a delay unit (31) for delaying a data cell supplied from each of the multiplexers (20 ₁ to 20 ₈ ) for a predetermined time. The control unit 33 for comparing the VPI / VCI of the data cell and outputting a write / output control signal based on the control information of 50), and the data cell supplied from the delay unit 31 are An output buffer type ATM switching system comprising a FIFO (32) for storing and outputting according to a recording / output control signal.

2. The VPI of the data cell of claim 1, wherein each of the second port processors 40 ₁ to 40 ₁₆ is supplied from each FIFO unit 30 ₁ to 30 ₁₆ based on control information of the control processor 50. A header converting section 44 for replacing / VCI, a transmitting FIFO 43 for storing and outputting data cells supplied from the header converting section 44, and a data cell supplied from the transmitting FIFO 43. Output buffer type ATM switching system characterized in that it comprises a UNI unit 41 for outputting the converted format.

※ Note: The disclosure is based on the initial application.