KR950022157A - Dual Integral Analog-to-Digital Converter - Google Patents
Dual Integral Analog-to-Digital Converter Download PDFInfo
- Publication number
- KR950022157A KR950022157A KR1019930031609A KR930031609A KR950022157A KR 950022157 A KR950022157 A KR 950022157A KR 1019930031609 A KR1019930031609 A KR 1019930031609A KR 930031609 A KR930031609 A KR 930031609A KR 950022157 A KR950022157 A KR 950022157A
- Authority
- KR
- South Korea
- Prior art keywords
- control signal
- signal
- reference voltage
- comparator
- switch
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
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- Analogue/Digital Conversion (AREA)
Abstract
본 발명은 이중적분형 아날로그-디지탈 변화기에 관한 것으로, 적분제어신호에 따라 상기 아날로그 입력신호를 연결하는 제1스위치와 특정제어신호에 따라 기준전압을 연결하는 제2스위치와 자동제로신호에 따라 기준접지를 연결하는 제3스위치와 스위칭된 입력들을 적분하는 적분기와적분기의 츨력을 비교기준전압과 비교하는 비교기와 비교기의 출력을 입력하고, 적분제어신호, 측정제어신호, 자동제로신호, 잡음시간제어신호 및 클럭을 발생하는 타이밍 제어부와 적분제어신호와 자동제로신호와 잡음시간제어신호에 따라 비교기준전압을 발생하는 비교기준전압을 발생하는 비교기준전압발생기와 비교기의 출력과 측정제어신호를 입력하여 클럭에 따라 카운트하는 카운터를 구비하여 정밀하게 아날로그신호를 디지탈신호로 변환한다.The present invention relates to a dual-integral analog-to-digital changer, the first switch connecting the analog input signal according to the integral control signal and the second switch connecting the reference voltage according to the specific control signal and the reference ground according to the automatic zero signal. Input the outputs of the comparator and comparator to compare the output of the integrator and the integrator and the output of the integrator to integrate the third switch to connect the switch and the integrated control signal, measurement control signal, automatic zero signal, noise time control signal And clock output by inputting the output of the reference voltage generator and the comparator and the measurement control signal to generate the reference voltage for generating the reference voltage according to the timing controller for generating the clock, the integral control signal, the automatic zero signal, and the noise time control signal. A counter is counted accordingly, and the analog signal is precisely converted into a digital signal.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제3도는 본 발명에 의한 이중적분형 아날로그-디지탈 변화기를 도시한 회로도이고,3 is a circuit diagram showing a dual-integral analog-to-digital converter according to the present invention,
제4도는 제3도의 장치에 의한 신호파형 및 타이밍을 도시한 것이다.4 shows signal waveforms and timing by the apparatus of FIG.
Claims (3)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019930031609A KR950022157A (en) | 1993-12-30 | 1993-12-30 | Dual Integral Analog-to-Digital Converter |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019930031609A KR950022157A (en) | 1993-12-30 | 1993-12-30 | Dual Integral Analog-to-Digital Converter |
Publications (1)
Publication Number | Publication Date |
---|---|
KR950022157A true KR950022157A (en) | 1995-07-28 |
Family
ID=66853328
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019930031609A Ceased KR950022157A (en) | 1993-12-30 | 1993-12-30 | Dual Integral Analog-to-Digital Converter |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR950022157A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100901694B1 (en) * | 2006-12-08 | 2009-06-08 | 한국전자통신연구원 | Current sources mode Apparatus |
-
1993
- 1993-12-30 KR KR1019930031609A patent/KR950022157A/en not_active Ceased
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100901694B1 (en) * | 2006-12-08 | 2009-06-08 | 한국전자통신연구원 | Current sources mode Apparatus |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
PA0109 | Patent application |
Patent event code: PA01091R01D Comment text: Patent Application Patent event date: 19931230 |
|
PA0201 | Request for examination |
Patent event code: PA02012R01D Patent event date: 19931230 Comment text: Request for Examination of Application |
|
PG1501 | Laying open of application | ||
E902 | Notification of reason for refusal | ||
PE0902 | Notice of grounds for rejection |
Comment text: Notification of reason for refusal Patent event date: 19950828 Patent event code: PE09021S01D |
|
E601 | Decision to refuse application | ||
PE0601 | Decision on rejection of patent |
Patent event date: 19960112 Comment text: Decision to Refuse Application Patent event code: PE06012S01D Patent event date: 19950828 Comment text: Notification of reason for refusal Patent event code: PE06011S01I |