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KR950020564A - Regeneration Speed Control Circuit of Fixed Speed Regenerator - Google Patents

Regeneration Speed Control Circuit of Fixed Speed Regenerator Download PDF

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Publication number
KR950020564A
KR950020564A KR1019930028108A KR930028108A KR950020564A KR 950020564 A KR950020564 A KR 950020564A KR 1019930028108 A KR1019930028108 A KR 1019930028108A KR 930028108 A KR930028108 A KR 930028108A KR 950020564 A KR950020564 A KR 950020564A
Authority
KR
South Korea
Prior art keywords
speed
control circuit
regenerator
frequency
memory device
Prior art date
Application number
KR1019930028108A
Other languages
Korean (ko)
Inventor
강환진
Original Assignee
이헌조
엘지전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 이헌조, 엘지전자 주식회사 filed Critical 이헌조
Priority to KR1019930028108A priority Critical patent/KR950020564A/en
Publication of KR950020564A publication Critical patent/KR950020564A/en

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  • Signal Processing For Digital Recording And Reproducing (AREA)

Abstract

본 발명은 정선속도 재생기에 있어서 원형음을 재생할 때 그 재생속도를 제어하는 기술에 관한 것으로, 일반적인 정선속도 재생기에 있어서는 재생기의 조절하는 기능이 구비되어 있지 않아 상기와 같이 원형음을 보다 효과적으로 사용할 수 없는 결함이 있었는바, 본 발명은 이를 해결하기 위하여 메모리소자(2)에 기록된 음성데이타의 리드할 때, 그 리드신호(CS)의 주파수를 조정하는 수단으로 재생속도를 자유롭게 가변할 수 있게 한 것이다.The present invention relates to a technique for controlling the reproduction speed when playing a circular sound in a fixed speed player, the general fixed speed player is not equipped with a function of adjusting the player can be used more effectively as described above. In order to solve this problem, the present invention provides a means for adjusting the frequency of the read signal CS so as to freely change the playback speed when reading the audio data recorded in the memory device 2. will be.

Description

정선속도 재생기의 재생속도 제어회로Regeneration Speed Control Circuit of Fixed Speed Regenerator

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명 정선속도 재생기의 재생속도 제어회로에 대한 블록도.1 is a block diagram of a regeneration speed control circuit of the present invention.

제2도의 (가) 및 (나)는 리드신호의 파형도이고, (다) 및 (라)는 리드신호의 주파수에 따른 음성데이타의 출력 파형도.(A) and (b) of FIG. 2 are waveform diagrams of the read signal, and (c) and (d) are output waveform diagrams of audio data according to the frequency of the read signal.

Claims (1)

음성데이타를 출력하는 음성데이타 출력부(1)와, 상기 음성데이타 출력부(1)에서 출력되는 데이타를 순차적으로 저장한 후 입력되는 콘트롤신호(CS)의 주파수에 대응되는 속도로 기 저장된 데이타를 출력하는 메모리소자(2)와, 상기 가변저항(VR)에 의해 설정되는 전압에 따라 상기 콘트롤신호(CS)의 주파수를 변화시키는 마이크로 컴퓨터(3)와, 상기 메모리소자(2)에서 출력되는 음성데이타를 아날로그 신호로 변환함과 아울러, 그 변환된 아날로그의 음성신호를 소정 레벨로 증폭하는 D/A변환 및 증폭부(4)와, 상기 D/A변환 및 증폭부(4)에서 출력되는 아날로그의 음성신호를 저장하는 기록매체(5)로 구성한 것을 특징으로 하는 정선속도 재생기의 재생속도 제어회로.The voice data output unit 1 for outputting the voice data and the data output from the voice data output unit 1 are sequentially stored, and the prestored data is stored at a speed corresponding to the frequency of the control signal CS. A memory device 2 for outputting, a microcomputer 3 for changing the frequency of the control signal CS according to the voltage set by the variable resistor VR, and a voice output from the memory device 2 A D / A conversion and amplification section 4 for converting data into an analog signal and amplifying the converted analog audio signal to a predetermined level, and the analog output from the D / A conversion and amplification section 4. And a recording medium (5) for storing audio signals. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930028108A 1993-12-16 1993-12-16 Regeneration Speed Control Circuit of Fixed Speed Regenerator KR950020564A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019930028108A KR950020564A (en) 1993-12-16 1993-12-16 Regeneration Speed Control Circuit of Fixed Speed Regenerator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930028108A KR950020564A (en) 1993-12-16 1993-12-16 Regeneration Speed Control Circuit of Fixed Speed Regenerator

Publications (1)

Publication Number Publication Date
KR950020564A true KR950020564A (en) 1995-07-24

Family

ID=66850870

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019930028108A KR950020564A (en) 1993-12-16 1993-12-16 Regeneration Speed Control Circuit of Fixed Speed Regenerator

Country Status (1)

Country Link
KR (1) KR950020564A (en)

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Legal Events

Date Code Title Description
PA0109 Patent application

Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 19931216

PG1501 Laying open of application
PC1203 Withdrawal of no request for examination
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid