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KR950015610A - 집적 회로 제조 방법 - Google Patents

집적 회로 제조 방법 Download PDF

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Publication number
KR950015610A
KR950015610A KR1019940028839A KR19940028839A KR950015610A KR 950015610 A KR950015610 A KR 950015610A KR 1019940028839 A KR1019940028839 A KR 1019940028839A KR 19940028839 A KR19940028839 A KR 19940028839A KR 950015610 A KR950015610 A KR 950015610A
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KR
South Korea
Prior art keywords
layer
material layer
conductive
silicon oxide
forming
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KR1019940028839A
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English (en)
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KR100330438B1 (ko
Inventor
치티페디 사이레쉬
토마스 코크란 월리엄
Original Assignee
제이. 티. 레흐버그
에이티 앤드 티 코포레이션
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Publication of KR950015610A publication Critical patent/KR950015610A/ko
Application granted granted Critical
Publication of KR100330438B1 publication Critical patent/KR100330438B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • ing And Chemical Polishing (AREA)
  • Drying Of Semiconductors (AREA)
  • Weting (AREA)

Abstract

본 발명은 금속 전도체 에칭 및 전도체의 적층을 위한 방법에 관한 것으로 도프된 이산화 실리콘층(15)은 금속 위에 증착 또는 인으로 에칭될 전도층의 적층상에 증착된다. 다음에, 상기 이산화 실리콘층(15)은 부분적으로 에칭되며 포토레지스트는 제거된다. 다음의 에칭은 아래에 놓인 금속층(13) 또는 전도체의 적층을 에칭하기 위한 마스크로서 이산화 실리콘층(15)에 형성된 상승부를 유용하게 한다.

Description

집적 회로 제조 방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제5도는 본 발명의 실시예에 따른 집적 회로부의 단면도.

Claims (9)

  1. 기판상에 하나 이상의 전도층을 형성하는 단계, 상기 전도층(13)상에 재료층(15)을 형성하는 단계, 상기 재료층(15)상에 패턴형성된 포토레지스트(17) 을 형성하는 단계를 포함하는 집적 회로 제조 방법에 있어서, 제1마스크로서 상기패턴형성된 포토레지스트(17)를 사용하고 상기 재료층(15)을 통해 적어도 부분적 으로 에칭함으로서, 상승부(19)를 형성하는 단계와, 상기 포토레지스트를 제거하는 단계와, 마스크로서 상기 상승부(19)를 사용하고 상기 전도층(13)을 에칭하므로서, 상기 기판상에 전도성 상승부를 형성하는 단계와, 상기 상승부(19)가 제거되는 단계를 구비하는 것을 특징으로 하는 집적 회로 제조 방법.
  2. 제2항에 있어서, 상기 전도성 재료(13)는 구리, 알루미늄, 텅스텐 및 내화성 금속 실리사이드로 구성된 그룹으로부터 선택되는 것을 특징으로 하는 집적 회로 제조 방법.
  3. 제1항에 있어서, 상기 반사-방지 코팅(37)은 상기 전도층(35, 33)과 재료층(15) 사이에 형성되고, 상기 반사-방지 코팅(37)은 상기 전도층 보다 먼저 에칭되는 것을 특징으로 하는 집적 회로 제조 방법.
  4. 제3항에 있어서, 상기 반사-방지 코팅(37)은 질화 티타늄 및 티타늄 텅스텐으로 구성된 그룹으로부터 선택되는 것을 특징으로 하는 집적 회로 제조 방법.
  5. 제1항에 있어서, 질화 티타늄층(33)은 상기 전도성 재료층과 기판 사이에 형성되며, 상기 질화 티타늄층은 상기 전도층 다음에 에칭되는 것을 특징으로 하는 집적 회로 제조 방법.
  6. 제5항에 있어서, 티타늄층(33)은 상기 질하 티타늄층(31)은 상기 질화티타늄층(33) 다음에 에칭되는 것을 것을 특징으로 하는 집적 회로 제조 빙법.
  7. 제1항에 있어서, 상기 재료층(15)은 인, BPTEOS, BPSG, PPETROS 및 스핀-온 글래스로 도포된 산화물로 구성된 그룹으로부딕 선택되는 것을 특징으로 하는 집적 회로 제조 방법.
  8. 제1항에 있어서, 상기 재료층(15)은 이중층이고, 상기 이중층은, 플라즈마-항상된 인 도프된 산화 실리콘 하의 플라즈마-향상된 도프되지 않은 산화 실리콘과, 플리즈라-향상된 도프된 산화 실리콘 하의 질화 실리콘과, 도프된 산화 실리콘 하의 도프되지 않은 산화 실리콘으로 구성된 그룹으로부터 선택되는 것을 특징으로 하는 집적 회로 제조 방법.
  9. 제1항에 있어서, 상기 재료층(15)은 그 도핑이 바닥부에서 상부가지 점차로 증가되는 산화 실리콘인 것을 특징으로 하는 집적 회로 제조 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019940028839A 1993-11-05 1994-11-04 집적회로제조방법 KR100330438B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US147368 1993-11-05
US08/147,368 US5439847A (en) 1993-11-05 1993-11-05 Integrated circuit fabrication with a raised feature as mask

Publications (2)

Publication Number Publication Date
KR950015610A true KR950015610A (ko) 1995-06-17
KR100330438B1 KR100330438B1 (ko) 2002-11-27

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US (1) US5439847A (ko)
EP (1) EP0652588B1 (ko)
JP (1) JP3550195B2 (ko)
KR (1) KR100330438B1 (ko)
DE (1) DE69426618D1 (ko)

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US6133146A (en) * 1996-05-09 2000-10-17 Scb Technologies, Inc. Semiconductor bridge device and method of making the same
US5950106A (en) * 1996-05-14 1999-09-07 Advanced Micro Devices, Inc. Method of patterning a metal substrate using spin-on glass as a hard mask
US6281585B1 (en) 1997-06-30 2001-08-28 Philips Electronics North America Corporation Air gap dielectric in self-aligned via structures
US6133635A (en) * 1997-06-30 2000-10-17 Philips Electronics North America Corp. Process for making self-aligned conductive via structures
US6420099B1 (en) * 1999-08-02 2002-07-16 Infineon Technologies Ag Tungsten hard mask for dry etching aluminum-containing layers
US6261967B1 (en) * 2000-02-09 2001-07-17 Infineon Technologies North America Corp. Easy to remove hard mask layer for semiconductor device fabrication
US6772692B2 (en) 2000-05-24 2004-08-10 Lifesparc, Inc. Electro-explosive device with laminate bridge
US7538034B2 (en) * 2006-12-22 2009-05-26 Qimonda Ag Integrated circuit having a metal element

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EP0468071B1 (en) * 1990-07-25 1994-09-14 International Business Machines Corporation Method of producing micromechanical sensors for the AFM/STM/MFM profilometry and micromechanical AFM/STM/MFM sensor head
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Also Published As

Publication number Publication date
US5439847A (en) 1995-08-08
JP3550195B2 (ja) 2004-08-04
DE69426618D1 (de) 2001-03-01
JPH07258868A (ja) 1995-10-09
EP0652588A2 (en) 1995-05-10
KR100330438B1 (ko) 2002-11-27
EP0652588A3 (en) 1997-02-19
EP0652588B1 (en) 2001-01-24

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