KR950015065B1 - Vitual channel chang circuit by multistage look-up table - Google Patents

Abstract

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Description

Virtual channel conversion circuit using multi-stage lookup table

1 is an ATM cell structure to which the present invention is applied.

2 is a virtual channel conversion circuit using a multi-stage lookup table of the present invention.

3 is an exemplary view according to the present invention.

4 is a memory map diagram applied to an embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

301,305: Latch 302,303: OR gate

304,307,308: Memory 306: Multiplexer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a virtual channel conversion scheme using a multi-stage lookup table. In particular, the present invention relates to a virtual channel indicating a logical channel to which an ATM cell belongs as an area of a header of an ATM cell used in an asynchronous transfer mode (ATM). The present invention relates to a virtual channel conversion circuit using a multi-stage lookup table that converts a channel into a new virtual channel and then changes it in real time using a multistage lookup table.

In general, in the asynchronous communication mode, a logical virtual channel is allocated to each end subscriber for each call or connection, and then data is delivered in a fixed length packet called an ATM cell. The virtual channel is represented by 24 bits of an ATM cell header corresponding to a potential 5 bytes of an ATM cell having a total length of 53 bytes. In addition, several kinds of calls or connections are transmitted through statistical multiplexing, and each division is made by a virtual channel. In addition, in the ATM system of the international standard, an ATM cell is transmitted in a transmission path of 155.520 Mbps or 622.080 Mbps, so that a transmission time of one ATM cell is 2.73 μsec or 0.682 μsec.

However, a virtual channel is meaningful only between a specific subscriber and a communication network. Even though a virtual channel of a specific number is assigned to a specific call or connection of a specific subscriber (hereinafter, subscriber A), the other subscriber communicating with the subscriber A (hereinafter, It does not affect the virtual channel decision between subscriber B) and the communication network. Therefore, in the communication network, the operation of changing the virtual channel of the ATM cell transmitted from the subscriber A to the virtual channel of the subscriber B is necessary to enable communication between the subscriber A and the subscriber B.

As such, the transfer time of one ATM cell is 2.73 μsec or 0.682 μsec, and in the worst case, virtual channel conversion is required for every ATM cell. In addition, since the virtual channel is composed of 24 bits, logically 2 to 24 squared virtual channels are possible, so that the conversion of the conversion into a single lookup table requires a huge amount of memory elements. Since it is necessary for each subscriber matching unit, there is a problem that is difficult to realize in practice.

In order to solve the above problems, the present invention is limited to the number of virtual channels that can be written at the same time, but the lookup table is configured in three stages so that all regions that can be displayed in 24 bits can be used. It is an object of the present invention to provide a virtual channel conversion circuit using a multi-stage lookup table that can economically realize an ATM switch in a manner that dramatically reduces the number of memory elements by implementing a stage lookup table.

In order to achieve the above object, the present invention provides at least a pointer for inputting an address A1 when a VPI arrives and outputting a pointer of k bits for designating a virtual channel bundle, which the VPI means, to the data line D1. At least one second column lookup table that receives VCI1 as an address A2L and A2H together with at least one first column lookup table and a pointer output from the first column lookup table, and outputs a pointer of m bits At least one third column lookup that receives VCI2 as addresses A3L and A3H together with the pointer D2 output from the two-row lookup table and outputs the converted virtual channel VPI / VCI to the data line D3. It is characterized by including a table.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a structural diagram of an ATM cell for explaining the present invention. As shown in the figure, an ATM cell structure is a cell header of 1 byte to 5 bytes, and 48 bytes of 6 bytes to 53 bytes are payloads.

Each byte has bit 8 sent before bit 7, and byte 1 sent before byte 2.

In each region, the first transmitted bit is the most significant bit (MSB).

Bit 8 to bit 5 of 1 byte of 5 byte cell header are Generic Flow Control (GFC) .Virtual channel is 24 bits from bit 4 of byte 1 to bit 5 of byte 4, and the upper 8 bits are the virtual path identifier ( Virtual Path Identification (VPI) and the lower 16 bits are the Virtual Channel Identification (VCI), where the virtual channel is referred to collectively as the VPI and VCI.

In addition, the virtual path may be viewed as a bundle or bundle of virtual channels, that is, up to two 16 squared powers (65,536) of virtual channels are possible in one virtual path. To convert a virtual channel means to replace these 24 bits with a different value.

Byte 4 is bit 4 to bit 2 is PT (Payload Type), bit 1 is CLP (Cell Loss Priority), and byte 5 is HEC (Head Error Check).

2 is a schematic configuration diagram of virtual channel conversion using a multi-stage lookup table according to the present invention, in which 21 is a first column lookup table, 22 is a second column lookup table, and 23, 23-2, and 23-2. Denote a third column lookup table, respectively.

VPI means the upper 8 bits of FIG. 1 and VCI1 means the 8 bits from bit 4 of byte 2 to bit 5 of byte 3 of FIG. 1, and VCI2 means bit 4 of byte 3 to bit 5 of byte 4 8 bits each.

When the VPI arrives, it is input to the address A1 of the first column lookup table 21. The data line D1 outputs a pointer of k bits that designates a virtual channel bundle, which means VPI.

The VCI1 becomes the addresses A2L and A2H of the second column lookup table 22 together with the pointer output from the first column lookup table 21 to convert the third column lookup table 23 pointer D2 composed of m bits. Output it.

VCI2 then becomes the addresses A3L and A3H of the third column lookup table 23 together with the pointer D2 output from the second column lookup table 22 and the data line D3 of the third column lookup table 23. ) Outputs the converted virtual channel (VPI / VCI).

The data lines D1 and D2 are assigned to the upper bits of the address for accessing the next column lookup table, respectively.

By doing this, when k = m = 2, the system can allocate four VPIs to its subscribers, a total of 1024 virtual channels, each of two V8 powers (256) of each VPI. When each column is separated into two columns, one is required in the first column, one in the second column, and the third column is required to output 24 bits of data. In addition, according to this method, any number among 2 to 24 squared virtual channels can be used arbitrarily, but only the total number of virtual channels that can be used at the same time is determined by the memory capacity, thereby maximizing the flexibility of virtual channel number allocation.

3 is an embodiment of the present invention, where 301 and 305 are latches, 302 and 303 are OR gates, 304 and 307 and 308 memory, and 306 are multiplexers, respectively.

As shown in the figure, the virtual channel conversion circuit using the multi-stage lookup table implements a lookup table with three rows of memory in order to change a virtual channel composed of 24-digit binary numbers into different values in real time inside an ATM cell. The first column outputs a pointer to find the second column using the first 8 bits (VPI) of the virtual channel, and the second column uses the pointer output from the first column as the upper bit of the address, and the second 8 of the virtual channel. Outputs a pointer to find the lookup table in the third column using bit VCI1 as the lower bit of the address, the third column is the upper bit of the address as the pointer output from the second column, and the third 8 bits of the virtual channel are addressed. A virtual channel conversion circuit using a multi-stage lookup table that outputs a new virtual channel of 24 bits to be finally converted to the lower bits of.

The configuration is as follows.

8-bit parallel data is inputted so that one cycle appears at the output by a clock (CLK / 8) corresponding to one byte transfer time of the cell. A first latch 301 that appears from the least significant bit to the most significant bit of the first state; a status maintenance signal SVPI that maintains a logic 0 state while the virtual path identifier appears at the output of the first latch 301; and the first latch. A status maintenance signal SVCI that maintains a logic 0 state while the first byte VCI1 of the virtual channel identifier appears at the output of 301, and a second byte of the virtual channel identifier at the output of the first latch 301. While the VCI2) is displayed, the first OR gate 302 which receives the state holding signal SVCI2 which maintains the logic 0 state, and the second OR which inputs the SVPI signal and the SVCI1 signal and performs the OR operation. 303, the first of the two input / output ports, the lower bit of the output of the first latch 301 is connected to the lower bit of the address, the upper bit of the output of the first latch 301 is connected to the higher bit of the address and multiplexing The lower bit of the output is connected to the next higher bit of the address, the most significant bit of the multiplexing output becomes the most significant bit of the address, and the output of the first OR gate 302 is connected to the chip enable (/ CE) and the out enable (/ OE). And a signal for reading and writing (hereinafter, R / W signal) is kept in a reading state, and the second port is a first memory 304 connected to a general microprocessor and data of the first input / output port of the first memory 304. The output is the input, and the output of the second OR gate 303 is connected to the clock input terminal so that the input appears as an output in the rising transition thereof. A second latch 305 which causes the output from the lower bit to the higher bit, the first of the two input groups both remain in logic 0 state and the second group is connected to the output of the second latch 305 The first group is output while the SVPI signal is in logic 0 state and the second group is output while the SVPI signal is in logic 1 state and the output is connected to the upper address of the first port of the first memory 304. The first multiplexer 306 to make the most significant bit of the output of the second latch 305 become the most significant bit of the memory address, and the first of the two input / output ports is the lower bit of the output of the first latch 301 as the lower bit of the address. The upper bit of the output of the first latch 301 is connected to the upper bit of the address, and the most significant bit of the output of the first multiplexer 306 becomes the most significant bit of the address. A second memory connected to the next higher bit of the address, the SVCI2 signal connected to the chip enable (/ CE) and out enable (/ OE), the R / W signal read and the second port connected to a general microprocessor (307). The first of the two input / output ports has a lower bit of the output of the first latch 301 connected to the lower bit of the address, and an upper bit of the output of the first latch 301 connected to the upper bit of the address, and the first multiplexer 306. The most significant bit of the output is the most significant bit of the address, the most significant bit of the address, the next bit is connected to the next higher bit of the address, and the SVCI2 signal is connected to the chip enable (/ CE) and out enable (/ OE) and R / The W signal remains read and the second port consists of a third memory 308 connected to a general microprocessor.

Detailed description of the configuration is as follows.

It is shown that the virtual channel conversion circuit of the multi-stage lookup table can be easily implemented by accessing a single memory several times. The circuit for extracting VPI, VCI1 and VCI2 from the actual bit stream and the converted virtual channel are placed in the corresponding positions of the original ATM cell. The circuit to be inserted is omitted. The memory element is also a dual port memory having two input / output ports, one port for initializing in a microprocessor is simplified.

At the input of the first latch 301, an ATM cell converted in parallel to 8 bits is input, which is arranged in the order of VPI, VCI1, and VCI2. That is, referring to the cell format of the ATM of FIG. 1, the VPI spans two bytes from bit 4 of byte 1 to bit 5 of byte 2, but when inputted to the circuit, the VPI is arranged in one byte and then inputted. This input data is latched by the CLK / 8 signal and appears at the output. One period of this signal equals one byte transfer time of the ATM cell. The output of the first latch is connected from address bit 0 (AD0) to address bit 7 (AD7) of the first memory 304, the second memory 306, and the third memory 307.

The SVPI, SVCI1, and SVCI2 signals are the signals that maintain logic 0 while the VPI, VCI1, and VCI2 are present at the output of the first latch 301, respectively, and the first memory 304 through the three input OR gate (first OR gate). Is connected to the chip enable (CE /) and the out enable (OE /). The lower four bits DD0-DD3 of the data line of the first memory 304 are connected to the input terminal of the second latch 305 and appear at the output of the rising transition of the output of the first OR gate 302. An output of the second latch 305 is connected to four first inputs I11, I21, I31, and I41 on the first multiplexer 306, which selectively output one of the two inputs.

Logic 0 is input to the second inputs I12, I22, I32, and I42 of the first multiplexer 306, respectively. The selection terminal S of the first multiplexer 306 connects the SVPI so that the second input is output when the SVPI is in the logic 0 state and the first input is output when the logic is in the logic 1 state.

The outputs Y1 to Y4 of the first multiplexer 306 are sequentially connected to the address bits 11 (AD11) to the address bits 8 (AD8) of the first memory 304. In this way, when the SVPI signal is in the logic 0 state, the first memory 304 performs the function of the first column lookup table 21 of FIG. 2 and the second column lookup table (i.e., the data line of the first memory 304). A pointer for finding one of the 22 is output to the data bits 0 and 1 (DD0, DD1) so that the second latch 305 of the second latch 305 may not exist at the rising transition of the output of the first OR gate 302 (in this case, the rising transition of the SVPI). Appear in the output.

Subsequently, with SVCI1 being logic 0, the first multiplexer 306 selects the output of the second latch 305 to address bits 11 to 8 of the first memory 304 and sends the first bits to address bits 7 to 0. The VCI1 outputted from the latch 301 is input to perform the function of the second column lookup table 22 of FIG. 2, so that the third column lookup table 23 is applied to data bits 0 to 3 of the first memory 304. A pointer to find is output and it is latched to the second latch 305 at the rising transition of SVCI1.

Then, when SVCI2 is logic 0, the first multiplexer 306 selects the output of the second latch 305 and sends the address bits 11 to 8 of the first memory 304 to the output Y1 of the first multiplexer 306. Y2 is connected to the address bits 9 and 8 of the second and third memories 306 and 307, respectively, and the VCI2 outputted from the first latch 301 to the address bits 7 to 0 of the first, second and third memories 304, 306 and 307, respectively. Is input to the chip enable and out enable of the second and third memories 306 and 307, and the SVCI2 is connected to perform the lookup table 23 function of the third column shown in FIG. Bits 0 through 7 output the upper 8 bits of the last converted VPI / VCI, and data bits 0 through 7 of the second and third memories 306 and 307 output the upper and lower 8 bits of the converted VPI / VCI, respectively. The virtual channel conversion process by the multi-stage lookup table of the present invention is completed.

In the above embodiment, k = m = 2 and the lookup tables 21 to 23 of the first, second, and third columns are implemented in one memory (first memory), in which case there is one memory element. Therefore, when the physical position of the first column lookup table 21 is set to the binary values 00 and 00 of m and k, the same value cannot be used for the physical addresses of the second and third column lookup tables 22 and 23. Thus, up to three virtual paths and up to 768 virtual channels can be allocated to one subscriber. The final data required is a new 24-bit VPI / VCI value, which adds two memories. The total memory capacity is 4k bytes in the first memory 304 and 6k bytes in 1k bytes in the second and third memories 306 and 307, which is larger than the case in which each column is separated, but the number of elements is reduced by two. Considering that the memory size is 1kbyte or 4kbyte, the size of the device does not change and the price does not vary significantly. Therefore, the area of the lookup table is reduced when the PBA is implemented.

4 is a memory map for the first, second, and third memories of FIG. 3, which is an embodiment of the present invention.

Data bits that are fixed to 0 0, such as 0 0 a1 a2 or b1 b2 0 0, are used to prevent the same address from being used with the pointer or address to which the last converted virtual channel is to be written. If two bits are indicated, one subscriber can be assigned maximum VPI at the same time and maximum VCI at the same time.

Referring to this memory map, a process of initializing a memory to allocate 123456 (HEX) in hexadecimal to a specific connection and convert it to 654321 will be described below.

0001,0010 in DD3-0 of 0000 0001 0010 (B) address (corresponding to VPI = 12 (HEX)) of the first memory 304, even if 123456 (HEX) is newly assigned Write a value that is not already assigned to another VPI of, 0011 and initialize the first column lookup table (assuming 0010 here). In this case, the assigned 0010 is the upper bit of the address, 34 (HEX) corresponding to VCI1 is added, and the value that is not already used for another VCI among 0100, 1000, 1100 is assigned to 0010 0011 0100 (B). Initialize the lookup table (assuming 1100 here). At this time, the allocated 1100 is the upper bit and VCI2 56 (HEX) is added, and 65 (HEX), which is the upper byte of the virtual channel to be converted, is written to the address 1100 0101 0110 (B) of the first memory 304. In the second memory 306, 43 (HEX) is written to 11 0101 0110 (B) generated by removing the lower 2 bits of the 1100 of the address and lowering the upper 2 bits, and 11 0101 to the third memory 307. By writing 21 (HEX) to 0110 (B), the initialization of memory is completed, and the ATM cell whose virtual channel is 123456 (HEX) among the ATM cells that are input thereafter is changed to 654321 (HEX) and transferred to the next destination. .

The present invention configured and operated as described above is limited in the number of virtual channels that can be used simultaneously, but can use a virtual channel of a whole area that can be represented by a 24-digit binary number, can use a virtual channel, and translate a virtual channel. It is possible to economically realize the subscriber matching circuit of the ATM switch by drastically reducing the memory area for conversion.

Claims (4)

In the virtual channel conversion apparatus using the multi-stage lookup table, when the VPI arrives, it is inputted to the address A1, and the data line D1 outputs a k-bit pointer that designates the virtual channel bundle that the VPI means. At least one or more first column lookup table 21 and at least one or more VCI1s received as addresses A2L and A2H together with pointers output from the first column lookup table 21 and outputting pointers of m bits. The VCI2 is inputted to the addresses A3L and A3H together with the pointer D2 output from the second column lookup table 22 and the second column lookup table 22 and converted into a data line D3. And at least one third column lookup table (23) for outputting VPI / VCI). 2. The first column lookup table (21) according to claim 1, wherein the first column lookup table (21) receives data converted in 8-bit parallel and outputs the data to the output by a clock (CLK / 8) corresponding to one byte transfer time of a cell. In the present invention, the first latching means 301 in which the least significant bit of the input data from the least significant bit to the most significant bit of the output, and the virtual path identifier are shown in the output of the first latching means 301. A status maintenance signal SVPI that maintains a logic 0 state while a status maintenance signal SVCI that maintains a logic 0 state while the first byte VCI1 of the virtual channel identifier appears at the output of the first latching means 301. And a first logical sum calculating means 302 for inputting a state holding signal SVCI2 which maintains a logic 0 state while the second byte VCI2 of the virtual channel identifier is displayed at the output of the first latching means 301. ), A second logical sum calculating means 303 for performing an OR operation by inputting the SVPI signal and the SVCI1 signal as inputs, and a first bit of the two input / output ports connects a lower bit of the output of the first latching means 301 to a lower bit of an address; The upper bit of the output of the first latching means 301 is connected to the higher bit of the address, the lower bit of the multiplexed output is connected to the next higher bit of the address, and the most significant bit of the multiplexing output is the most significant bit of the address. Connect the output of the means 302 to chip enable (/ CE) and out enable (/ OE), keep the signal for reading and writing (hereinafter R / W signal) in read state, and the second port is a general microprocessor And a first memory means (304) connected to the virtual channel conversion circuit. The second column lookup table 22 is configured to input data output of the first input / output port of the first memory means 304, and output the second logic sum operation means 303 to a clock input stage. Second latching means 305, the first of the two input groups, such that the lower to upper bits of the data appear from the lower to upper bits of the output in connection so that the input appears as an output in its rising transition. The groups all remain in logic 0 state and the second group is connected to the output of the second latching means 305 so that the first group is output while the SVPI signal is in logic 0 state and the second while the SVPI signal is in logic 1 state. A group is output and the output is connected to the upper address of the first port of the first memory means 304 in the uppermost of the output of the second latching means 305 And a first multiplexer (306) for causing the bit to be the most significant bit of the memory address. According to claim 1, wherein the third column lookup table (23), the first of the two input and output ports of the first latch means 301 of the output of the lower bit is connected to the lower bit of the address and the first latching means ( 301) The upper bit of the output is connected to the upper bit of the address, the most significant bit of the output of the first multiplexer 306 becomes the most significant bit of the address, the next bit is connected to the next higher bit of the address, and the chip enable (/ Second memory means 307 connected to a common microprocessor and a first port of the two input / output ports, the first port being the first port The lower bit of the output of the latching means 301 is connected to the lower bit of the address, the upper bit of the output of the first latching means 301 is connected to the higher bit of the address, and the most significant bit of the output of the first multiplexer 306 is the most significant of the address. ratio The next bit connects to the next higher bit of the address, connects the SVCI2 signal to the chip enable (/ CE) and out enable (/ OE), and keeps the R / W signal read; And a third memory means (308) connected to the processor.