KR950014272B1 - Semiconductor device and manufacturing method - Google Patents

Abstract

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Description

Semiconductor device and manufacturing method

1 to 3 are process flowcharts showing a method of forming a wiring layer connected to a conventional gate electrode.

FIG. 4 is a cross-sectional view of a semiconductor device having a metal pattern for removing static charge generated during pre-applied plasma etching.

5 is a cross-sectional view of a semiconductor device having a MOS structure transistor for removing static charges generated during plasma etching according to the present invention.

6 to 10 are process flowcharts illustrating a first embodiment of a method of manufacturing a semiconductor device having a MOS structure transistor for removing static charges generated during plasma etching according to the present invention.

11 to 15 are process flowcharts illustrating a second embodiment of a method of manufacturing a semiconductor device having an MOS structure transistor for removing static charges generated during plasma etching according to the present invention.

16 to 20 are flowcharts illustrating a third embodiment of a method of manufacturing a semiconductor device having an MOS structure transistor for removing static charges generated during plasma etching according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device and a method for manufacturing the same, which can eliminate a problem occurring during a plasma etching process for a metal layer.

Recently, as the development of semiconductor manufacturing technology and the application field of memory devices are expanded, the development of large-capacity memory yarns is progressing, and the increase in the capacity of such memory devices is based on micro process technology, which is doubled for each generation. It has been promoted by research. In particular, the wiring technology in the semiconductor device is one of the important items in the miniaturization technology of the memory device, which is a contact with the gate electrode and the source (drain) diffusion region, which are also used as the wiring such as the word line of the memory. And metal wirings that interconnect each element.

1 to 3 are process flowcharts illustrating a method of forming a wiring layer connected to a conventional gate electrode, which will be described using a metal oxide semiconductor (MOS) transistor as an example.

FIG. 1 shows a process for forming a transistor. First, a gate electrode 2 is formed on the first conductive semiconductor substrate 100 via a gate oxide film 1, and the center of the gate electrode 2 is formed. Thus, the transistor is completed by forming the source region 3 and the drain region 4 of the second conductive type in both semiconductor substrates 100.

2 shows a process of forming the first interlayer insulating film 10 and the first contact hole CH1. First, the first interlayer insulating film 10 having a predetermined thickness is formed to cover the transistor, and then the first interlayer insulating film 10 is formed. A first photoresist is exposed by forming a photoresist pattern on the first interlayer insulating film through a process such as photoresist coating, mask exposure, and development to etch the first interlayer insulating film over the gate electrode 2. The contact hole CH1 is formed.

FIG. 3 illustrates a process of forming the first metal layer 12 and the photoresist pattern PR. The first metal layer l2, for example, aluminum, connected to the gate electrode 2 is formed on the entire surface of the resultant contact hole. After forming to a predetermined thickness, a photoresist pattern PR capable of patterning a first metal layer having a desired size is formed on the first metal layer 12 through photoresist coating, mask exposure, and development.

In the subsequent process, the first metal layer 12 is patterned by applying the photoresist pattern PR to form a wiring layer pattern connected to the gate electrode 2. At this time, the etching process of the aluminum film, which is the first metal layer, generally uses a plasma etching process. The etching process is performed by using a gas that has been plasma-ized on an aluminum film that is etched during the etching of the aluminum film. Electrostatic charge is generated, which causes stress to the gate oxide film of the transistor of the MOS structure connected to the aluminum film (via the charge discharge passage as shown in FIG. 3). There is a problem in that the characteristics of the gate oxide film are deteriorated. Therefore, the characteristics of the MOS structure transistor or the MOS structure capacitor are deteriorated, and the reliability of the gate oxide film is also a problem.

The problem of the prior art is that the charge generated during the plasma etching process does not have a path for discharging and thus accumulates continuously (so-called charge-up phenomenon). The strong electric field caused by the charge causes breakdown and the like in the gate oxide film.

Therefore, the present applicant has filed the application No. 92-11491 dated June 29, 1992 to solve the above-mentioned problems of the prior art (see Fig. 4).

However, in the structure of a pre- filed semiconductor device, there is a path through which electrostatic charges generated by plasma etching can be discharged only through a junction between a metal pattern and an impurity injection region. However, when the thickness of the gate oxide film of the transistor is gradually thinned and lowered to a certain limit due to the high integration, the charges remaining without being discharged cause stress on the gate oxide film and eventually breakdown occurs in the gate oxide film, thereby preventing product defects. Will result. In other words, when the electrostatic charge generated during plasma etching on the first metal pattern 12b is negative, it is discharged to the semiconductor substrate through the first metal pattern 12b and the impurity injection region 11 of the first conductive type. This easily occurs, but when the static charge generated during the etching process is a positive charge, the charges induced in the first metal pattern 12b are hardly discharged, and the charges are transferred to the gate oxide film 1 of the MOS structure transistor. (See FIG. 4, FIG. 4 shows a state where the first metal pattern is completed. However, the discharge path of the static charge generated during the etching process is before the first metal pattern is completely formed.) During the etching process). In particular, when a wiring layer is formed in a DRAM (Dynamic Random Access Memory) to be connected to the gate electrodes of MOS structure transistors of many memory cells, the stress applied to the gate oxide film of the transistor greatly affects the yield and the reliability of the product.

Accordingly, an object of the present invention is to provide a semiconductor device having a separate MOS structure transistor for discharging the electrostatic charge generated during plasma etching in order to solve the problems of the prior art as described above.

Another object of the present invention is to provide a manufacturing method capable of efficiently manufacturing a semiconductor device having the above-described MOS structure transistor.

In order to achieve the above object, the present invention provides a semiconductor device comprising a metal layer connected to each part of the predetermined results on a first conductive semiconductor substrate on which predetermined results are formed. Impurity injection regions of the first conductive type formed on the surface of the first conductive type semiconductor substrate which are not formed, and a first semiconductor element for removing static charge on the first conductive type semiconductor substrate on which the predetermined results are not formed. A first portion of the first semiconductor element and a metal layer, and a second portion of the first semiconductor element and an impurity implantation region of the first conductive type to connect the first portion of the first semiconductor element The third portion is configured to be connected by a separate metal pattern.

In order to achieve the above another object, the method of the present invention is a method of manufacturing a semiconductor device comprising the step of forming a metal layer connected to each part of a predetermined result formed on a semiconductor substrate of the first conductive type, Forming predetermined results on the first conductive semiconductor substrate and forming a first semiconductor element for removing static charge on the first conductive semiconductor substrate on which the predetermined results are not formed; Forming an impurity implantation region of a first conductivity type on a surface of a semiconductor substrate of a first conductivity type adjacent to the first semiconductor element, in which the predetermined products are not formed; And at the same time, the first portion of the first semiconductor element and the metal layer are connected, and the second portion of the first semiconductor element and the impurity injection region of the first conductive type are connected to each other. The third portion is characterized in that it comprises a process to be connected by a separate metal pattern.

Hereinafter, with reference to the accompanying drawings will be described the present invention.

FIG. 5 is a cross-sectional view illustrating a semiconductor device including an electrostatic charge removing MOS structure transistor generated during plasma etching according to an exemplary embodiment of the present invention. do.

Referring to FIG. 5, a gate electrode 2 having a gate oxide film 1 interposed therebetween on a semiconductor substrate 100 of a first conductivity type, and a source / drain region 3, which is an impurity implantation region of a second conductivity type, may be used. 4) An MOS structure transistor TR which is an active element formed of 4) is formed, and an electrostatic discharge is performed on the semiconductor substrate 100 of a portion which becomes a margin in a chip in which the MOS structure transistor TR which is the active element is not formed. The first transistor TRl for removing the lower portion is formed, and the first wiring layer 12a connected to the gate electrode 2 of the active element TR has a drain region of the first transistor TRl for removing the static charge. A first conductive type impurity implantation region 11 formed in the source region 3 of the first transistor TRl and the semiconductor substrate 100 in a portion of the chip, which is connected to (4); Connected to the second metal pattern 12c and connected to the gate electrode 2 of the first transistor TRl. The first metal pattern 12b of FIG. 1 is formed, and the first and second metal patterns 12b and 12c connected to the gate electrode 2 and the source region 3 of the first transistor TRl are respectively formed. The structure is interconnected by two metal layers 16. Here, reference numeral 10 denotes a first interlayer insulating film and 14 denotes a second interlayer insulating film, and the first transistor TR1 for removing static charge is a MOS structure transistor.

6 to 10 are process flowcharts illustrating a first embodiment of a method of manufacturing a semiconductor device having an MOS structure transistor for removing static charges generated during plasma etching according to the present invention.

6 shows an MOS structure transistor TR, which is an active element, a first transistor TR1 for eliminating static charges generated during a plasma etching process (hereinafter referred to as a first transistor for eliminating static charges), and an impurity implantation region ( 11 shows a process of forming a gate electrode 2 on a first conductive semiconductor substrate 100 with a gate oxide film 1 interposed therebetween, with both sides centering on the gate electrode 2. The MOS structure transistor TR, which is an active element, is completed by forming the source region 3 and the drain region 4 of the second conductive type in the semiconductor substrate 100 of FIG. At this time, the first transistor TR1 for eliminating static charges is formed on the semiconductor substrate 100 at the portion of the chip which is to be a margin. Subsequently, the active element TR and the portion of the static charge elimination first transistor TRl are covered with a predetermined mask pattern, and then the portion of the chip which does not form the electrostatic charge elimination first transistor TRl is not formed. The impurity implantation region 11 is formed by injecting an impurity of the first conductivity type into a predetermined portion of the semiconductor substrate 100.

FIG. 7 illustrates a process of forming the first interlayer insulating film 10 and the first, second, third, fourth and fifth contact holes CH1, CH2, CH3. CH4 and CH5. Forming a first interlayer insulating film 10 to insulate the transistors on the entire surface of the device TR and the first transistor TRl for removing static charge, and applying a photoresist on the first interlayer insulating film 10, Through the process of mask exposure and development, the gate electrode 2 of the MOS structure transistor TR, which is the active element, is exposed, and at the same time, the drain region 4 and the gate of the first transistor TRl for removing static charges are exposed. After forming a photoresist pattern having a predetermined size for exposing the electrode 2 and the source region 3 and the impurity injection region 11, the photoresist pattern is applied to the first interlayer insulating film 10. By etching, the gate electrode 2 of the MOS structure transistor TR, which is the active element, The first contact hole CHl to expose the drain region 4 of the first transistor TRl to remove the static charge, and the gate of the first transistor TRl to remove the static charge. The third contact hole CH3 exposing the electrode 2, the fourth contact hole CH4 exposing the source region 3 of the first transistor TRl for removing static charge and the impurity implantation region 11. The fifth contact hole CH5 exposing the same is simultaneously formed.

FIG. 8 illustrates a process of forming the first metal layer 12 and the first photoresist pattern PRl. The first metal layer 12, for example, aluminum is formed on the entire surface of the resultant after the process of FIG. The first photoresist pattern PRl is formed on the first metal layer 12 through photoresist coating, mask exposure, and development.

FIG. 9 illustrates a patterning process. By applying the first photoresist pattern PRl to pattern the first metal layer using a plasma etching process, the gate electrode of the MOS structure transistor TR, which is the active element, is formed. 2) and a first wiring layer 12a for simultaneously connecting the drain region 4 of the first transistor TRl for removing static charge and the gate electrode 2 of the first transistor TRl for removing static charge. The first metal pattern 12b and the second metal pattern 12c for simultaneously connecting the source region 3 and the impurity injection region 11 of the first transistor TR1 for removing static charge are formed. At this time, if the electrostatic charge is generated by the plasma gas during the plasma etching process, and charge is induced in the first wiring layer 12a, charge is induced in the first metal pattern 12b, thereby removing the electrostatic charge. The first transistor TRl becomes a turn-on condition. Therefore, the charges induced in the first wiring layer 12a pass through the second metal pattern 12c through the first transistor TRl for removing static charge, and then connect the semiconductor substrate 100 connected to the impurity injection region 11. By discharging through, an element which is not affected by the electrostatic charge can be obtained. That is, the present invention relates to the discharge of electric charges during the plasma etching process through a separate metal pattern, whereas the present invention provides the electrostatic charge removing transistor and then the patterning of the metal layer is performed. And to discharge the charge by turning on.

FIG. 10 illustrates a process of forming the second metal layer 16. First, the photoresist pattern is removed, and then a second interlayer insulating film 14 is formed on the entire surface of the resultant product, and the photoresist is formed on the second interlayer insulating film 14. A photoresist pattern is formed to expose predetermined portions of the first metal pattern 12b and the second metal pattern 12c through a process such as coating, mask exposure, and development. The second interlayer insulating layer 14 is etched by applying the photoresist pattern to form a contact hole exposing the first metal pattern 12b and the second metal pattern 12c, and then the second metal layer on the entire surface of the resultant product. (16) is formed and patterned to a predetermined size. Here, the first metal pattern l2b and the second metal pattern 12c are connected to the second metal layer 16 so that the first transistor TR1 for removing the static charges is generated in the plasma etching process. After discharging, it should be turned off in the normal state so that there is no problem in normal operation. Here, the reference numeral 50 is an equivalent circuit diagram showing a connection relationship between the first transistor TR1 for removing the static charge. In this case, the gate electrode 2 of the first transistor TR1 for removing the static charge is connected to the semiconductor substrate V _BB business card 100 to have a back bias level ba Bk bias level V _BB . When the node A of the symbol A is at the high potential level, the gate oxide film 1 of the first transistor TR1 for removing the static charge may be stressed due to a large potential difference during chip operation.

Therefore, a method using two electrostatic charge removing transistors to solve this problem will be described in the second embodiment.

11 to 15 are process flowcharts illustrating a second embodiment of a method of manufacturing a semiconductor device having an MOS structure transistor for removing static charges generated during plasma etching according to the present invention.

FIG. 11 illustrates a process of forming an MOS structure transistor TR, an electrostatic charge removing first transistor TRl, an electrostatic charge removing second transistor TR2, and an impurity injection region 11 as an active element. First, a gate electrode 2 is formed on the first conductive semiconductor substrate 100 with a gate oxide film 1 interposed therebetween, and a second conductive layer is formed on both semiconductor substrates 100 around the gate electrode 2. The MOS structure transistor TR, which is an active element, is completed by forming the source region 3 and the drain region 4 each of which have a shape. At this time, the first transistor TR1 and the second transistor TR2 for removing static charge are formed on the semiconductor substrate 100 as a part of the chip, at the same time as the active element TR. Subsequently, the active element TR, the electrostatic charge removing first transistor TRl, and the electrostatic charge removing second transistor TR2 are covered with a predetermined mask pattern, and then the electrostatic charge removing first and first parts are removed. The impurity implantation region 11 is formed by injecting an impurity of the first conductivity type into a predetermined portion of the semiconductor substrate 100 in a portion of the chip where no two transistors TRl and TR2 are formed. The drain region 4 of the first transistor TR1 for removing static charge is used as the source region 3 of the second transistor TR2 for removing static charge.

12 shows the first interlayer insulating film 10 and the first, second, third, fourth, fifth, sixth and seventh contact holes CH1, CH2, CH3, CH4, CH4, CH5, CH6, and CH7. The first interlayer insulating film 10 for insulating the transistors is formed on the entire surface of the product formed with the active element TR and the first and second transistors TR1 and TR2 for removing the static charge. And the gate electrode 2 of the MOS structure transistor TR, which is the activator device, is exposed through the process of applying photoresist, mask exposure, and development on the first interlayer insulating film 10. To expose the drain regions 4, the gate electrodes 2, and the source regions 3 of the first and second transistors TR1 and TR2 for removing static charge, and the impurity impurity implanted region 11. After forming a photoresist pattern having a predetermined size, the photoresist pattern is applied to etch the first interlayer dielectric layer 10 to MOS the active element. A first contact hole CHl exposing the gate electrode 2 of the structure transistor TR, a second contact hole CH2 exposing the drain region 4 of the electrostatic charge removal first transistor TRl, A third contact hole CH3 exposing the gate electrode 2 of the first charge removing transistor TRl, and a fourth exposing the source region 3 of the first transistor TRl removing the static charge. The sixth contact hole CH6 exposing the contact hole CH4, the fifth contact hole CH5 exposing the impurity injection region 11, and the drain region 4 of the electrostatic charge removal second transistor TR2. ) And a seventh contact hole CH7 exposing the gate electrode 2 of the second transistor TR2 for static charge removal. Here, the source region 3 of the second transistor TR2 and the drain region 4 of the first transistor TRl share the same region, and thus the source region 3 of the second transistor TR2. Without the formation of a separate contact hole for exposing the light source, the same effect of exposing the source region 3 of the second transistor TR2 by the formation of the second contact hole CH2 can be obtained.

FIG. 13 illustrates a process of forming the first metal layer 12 and the first photoresist pattern PRl. The first metal layer 12, for example, aluminum is formed on the entire surface of the resultant after the process of FIG. The first photoresist pattern PRl is formed on the first metal layer 12 through photoresist coating, mask exposure, and development.

FIG. 14 illustrates a patterning process. By applying the first photoresist pattern PRl to pattern the first metal layer using a plasma etching process, the gate electrode of the MOS structure transistor TR, which is the active element, is formed. 2) and a first wiring layer 12a for simultaneously connecting the drain region 4 of the second transistor TR2 for removing static charge and the gate electrode 2 of the second transistor TR2 for removing static charge. A fourth metal shell connected to the third metal pattern 12d to be connected to the drain region of the first transistor TR1 for removing the static charge (or the source region of the second transistor for removing the static charge: 4 (3)) 12e), a first metal pattern 12b connected to the gate electrode 2 of the first charge removing transistor TRl, and a source region 3 of the first transistor TRl removing the static charge, The second metal shell 12c for simultaneously connecting the impurity injection region 11 at the same time The Castle. At this time, if the electrostatic charge is generated by the plasma gas during the plasma etching process, and charge is induced in the first wiring layer 12a, the charge is also applied to the third metal pattern 12d and the first metal pattern 12b. In this case, the first and second transistors TR1 and TR2 for removing the static charge are turned on. Accordingly, the charges induced in the first wiring layer 12a are connected to the impurity injection region 11 through the second metal pattern 12c through the first and second transistors TR1 and TR2 for removing the static charge. By discharging through 100, an element which is not affected by the electrostatic charge can be obtained.

FIG. 15 illustrates a process of forming the second metal layer 16. First, after the process of FIG. 14, a second interlayer insulating film 14 is formed on the entire surface of the resultant product, and a photoresist is applied on the second interlayer insulating film 14. And exposing predetermined portions of the first metal pattern 12b, the second metal pattern 12c, the third metal pattern 12d, and the fourth metal pattern 12e through mask exposure and development. To form a photoresist pattern. By etching the second interlayer insulating layer 14 by applying the photoresist pattern, the first metal pattern 12b, the second metal pattern 12c, the third metal pattern 12d, and the fourth After forming the contact holes exposing the metal pattern 12e, the second metal layer 16 is formed on the entire surface of the resultant, so that the first metal pattern 12b and the second metal pattern 12c are connected, and the third The metal pattern 12d and the fourth metal pattern 12e are patterned to a predetermined size so as to be connected. Here, the electrostatic charge is formed by connecting the first metal pattern 12b, the second metal pattern 12c, the third metal pattern 12d, and the fourth metal pattern 12e to the second metal layer 16, respectively. The first and second transistors TR1 and TR2 for removal are turned off in the normal state after discharging the charge generated during the plasma etching process, so that there is no problem during normal operation. At this time, the ground terminal V _ss is connected to the second metal layer 16 connecting the third metal pattern 12d and the fourth metal pattern 12e to connect the impurity injection region 11 to the semiconductor substrate ( Discharge is also made to the ground terminal in case it is not discharged through 100). Reference numeral 53 is an equivalent circuit diagram showing a connection relationship between the first transistor TR1 and the second transistor TR2 for removing static electricity of the second embodiment.

16 to 20 are process flowcharts illustrating a third embodiment of a method of manufacturing a semiconductor device having an MOS structure transistor for removing static charges generated during plasma etching according to the present invention.

16 to 19 are the same as the processes of FIGS. 11 to 14, respectively.

FIG. 20 illustrates a process of forming the second metal layer 16. First, after the process of FIG. 19, a second interlayer insulating film 14 is formed on the entire surface of the resulting product, and a photoresist is applied on the second interlayer insulating film 14. And exposing predetermined portions of the first metal pattern 12b, the second metal pattern l2c, the third metal pattern 12d, and the fourth metal pattern 12e through mask exposure and development. To form a photoresist pattern. By etching the second interlayer insulating layer 14 by applying the photoresist pattern, the first metal pattern 12b, the second metal pattern 12c, the third metal pattern 12d, and the fourth After forming the contact holes exposing the metal pattern 12e, the second metal layer 16 is formed on the entire surface of the resultant, so that the third metal pattern 12d and the fourth metal pattern 12e are connected to each other. The first metal pattern 12b and the second metal pattern 12c are patterned to a predetermined size so as to be connected to each other. Here, the third metal pattern 13d and the fourth metal pattern 12e are connected to the second metal layer l6, respectively, and the first metal pattern 12b and the second metal pattern 12 are connected to each other. By connecting, the second metal layer 16 connected to the third metal pattern 12d is a line (signal input terminal) that receives a signal generated when a chip is operated, and the fourth metal pattern 12 The second metal layer l6 connected to 12e) is connected to the ground terminal V _ss to operate the second transistor TR2 for removing the static charge as a transistor turned on or off according to a chip operation. Therefore, the charge generated during the plasma etching process is discharged as in the second embodiment, and the first and second transistors TRl and TR2 for removing the static charge discharge the charge generated during the plasma etching process. After the normal operation, turn it off so that there is no problem during normal operation. Here, reference numeral 55 is an equivalent circuit diagram showing a connection relationship between the first transistor TR1 and the second transistor TR2 for removing static electricity of the third embodiment.

The present invention is not only applied to the three embodiments described above, of course, various applications are possible without departing from the technical spirit of the present invention. In addition, if the electrostatic charge removing transistor according to the present invention is configured as much as possible in the portion of the chip margin, a large amount of charge can be discharged, and the stress on the gate oxide film of the transistor in the cell portion can be reduced. Can improve the yield and reliability.

As described above, the present invention forms a separate electrostatic charge removal transistor by discharging the charge generated when the metal layer is patterned by the plasma etching process and discharges the semiconductor layer or the ground terminal after the metal layer is patterned, thereby achieving stable product characteristics and yield. And it is possible to improve the reliability of the device, to reduce the burden of improving the semiconductor manufacturing process for improving the damage (damage) due to the plasma etching, thereby improving productivity and competitiveness.

In addition, the problem improvement method through the conventional process improvement can minimize the damage caused during the plasma etching process, but could not be completely eliminated (because for etching, there must be basic elements such as RF power, gas pressure, etc. According to the present invention, damage caused by all the charges generated in the plasma etching process can be eliminated by a circuit configuration consisting of a separate electrostatic charge removing transistor, and almost perfect charges can be removed.

Claims (15)

A semiconductor device having a metal layer connected to a portion of each of the predetermined results on a first conductive semiconductor substrate on which predetermined results are formed, wherein the first conductive type semiconductor substrate is not formed. An impurity implantation region of a first conductivity type formed on a surface of the semiconductor substrate; and forming a first MOS transistor for removing static charge on a semiconductor substrate of the first conductivity type in which the predetermined results are not formed, wherein the first MOS transistor The drain region of the transistor and the metal layer are connected, and the source region of the first MOS transistor and the impurity implantation region of the first conductive type are connected, and the gate electrode of the first MOS transistor is connected by a separate metal pattern. A semiconductor device, characterized in that configured to. The semiconductor device according to claim 1, wherein the metal layer and the metal pattern are aluminum films. The semiconductor device according to claim 1, wherein each of the predetermined products is a gate electrode of a MOS structure transistor. The metal layer of claim 1, wherein the first MOS transistor for removing the static charges is not operated during a normal operation of the chip. The metal layer connects the source regions of the first MOS transistor and the respective metal patterns connected to the gate electrodes. Bandote device characterized in that it further comprises. The semiconductor device of claim 1, further comprising: a second MOS transistor for removing static charge on a semiconductor substrate of a first conductivity type in which the predetermined result is not formed between the predetermined result and the first MOS transistor for removing static charge. A semiconductor device, characterized in that. The method of claim 5, wherein the drain region of the second MOS transistor and the metal layer connected to each of the predetermined results are connected, and the source region and the gate electrode of the second MOS transistor are separated from each other by a separate metal pattern. And the drain region of the first MOS transistor and the source region of the second MOS transistor are connected to each other. 7. The semiconductor device according to claim 6, wherein the drain region of the first MOS transistor and the source region of the second MOS transistor share the same region. The method of claim 5, wherein the first and second MOS transistors for removing the static charges are not operated during the normal operation of the chip. A metal layer to be connected; A metal layer connecting a separate metal pattern connected to the source region of the second MOS transistor; And a metal layer connecting the metal pattern connected to the gate electrode of the second MOS transistor. The semiconductor device of claim 8, wherein a ground terminal is connected to a metal layer connecting a separate metal pattern connected to a source region of the second MOS transistor. The semiconductor device of claim 9, wherein the signal input terminal is connected to a metal layer connecting a separate metal pattern connected to the gate electrode of the second MOS transistor. The method of claim 8, wherein the metal layer connecting the separate metal pattern connected to the source region of the second MOS transistor and the metal layer connecting the separate metal pattern connected to the gate electrode of the second MOS transistor are connected to each other. A semiconductor device characterized by the above-mentioned. The metal layer of claim 11, wherein a metal layer connecting a separate metal pattern connected to the source region of the second MOS transistor and a metal layer connecting a separate metal pattern connected to the gate electrode of the second MOS transistor are connected to each other. A semiconductor device, characterized in that the ground terminal is connected. A method of manufacturing a semiconductor device comprising the step of forming a metal layer connected to each portion of a predetermined result formed on a semiconductor substrate of a first conductive type, wherein the desired result is formed on a semiconductor substrate of a first conductive type At the same time, forming a first MOS transistor for removing static charge on a semiconductor substrate of a first conductivity type in which the predetermined products are not formed; Forming an impurity implantation region of a first conductivity type on a surface of the semiconductor substrate of a first conductivity type adjacent to the first MOS transistor, on which the predetermined products are not formed; And at the same time, a drain region of the first MOS transistor and the metal layer are connected to each other, a source region of the first MOS transistor and an impurity injection region of the first conductive type are connected to each other, and a gate electrode of the first MOS transistor. The manufacturing method of a semiconductor device characterized in that it comprises a step to be connected by a separate metal pattern. 15. The method of claim 13, wherein the drain region of the first MOS transistor and the metal layer are connected at the same time, the source region of the first MOS transistor and the impurity injection region of the first conductive type is connected, The process of connecting the gate electrode of the transistor with a separate metal pattern may include: forming a first interlayer insulating film on the entire surface of the resultant after the process of forming the impurity implantation region of the first conductivity type; By etching the first interlayer insulating film by applying a first mask pattern on the first interlayer insulating film, a portion of the predetermined result, a drain region, a source region and a gate electrode of the first MOS transistor, and an impurity of the first conductive type are formed. Forming contact holes exposing the injection region; Forming the metal layer on the entire surface of the resultant; And etching a metal layer by applying a second mask pattern on the metal layer, thereby connecting a portion of the predetermined result to a drain region of the first MOS transistor, a source region of the first MOS transistor, and the first conductive layer. And forming a metal pattern connecting the impurity implantation region of the type and a separate metal pattern connected to the gate electrode of the first MOS transistor. The method of claim 13, wherein the first and second MOS transistors for removing the static charge are not operated during normal operation of the chip. Forming a metal layer to be connected; Forming a metal layer connecting a separate metal pattern connected to the source region of the second MOS transistor; And forming a metal layer that connects a separate metal pattern connected to the gate electrode of the second MOS transistor.