KR950010824B1 - Acceleration / deceleration control device of PLC positioning unit - Google Patents

Abstract

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Description

Acceleration / deceleration control device of PLC positioning unit

1 is a block diagram for linear acceleration and deceleration of a conventional PLC positioning unit.

2 is a configuration diagram for the S self-deceleration of the conventional PLC position determination unit.

Figure 3 is a block diagram for the S-shape and exponential acceleration and deceleration of the PLC positioning unit of the present invention.

4 is a control flow chart for the acceleration / deceleration control method of the PLC positioning unit of the present invention.

* Explanation of symbols for main parts of the drawings

1-3: first to second multipliers 4-6, 9, and 11: first to fifth adders

7, 8, 10: first to third antacid groups

The present invention relates to an acceleration / deceleration control device for positioning a PLC positioning unit. In particular, a positioning of a PLC allows a acceleration / deceleration pattern to be created without a floating point operation by a sprin algorithm. An acceleration / deceleration control device for a crystal unit.

As shown in FIG. 1, the configuration diagram for linear acceleration and deceleration of a conventional PLC positioning unit includes a buffer register (R ₁ -R _m ) for sampling and delaying an input speed point for a predetermined time and an input speed point. The adder 1 adds the delayed value and the feedback value through the buffer registers R ₁ -R _m , and the input terminal of the adder 1 by delaying the value added through the adder 1 for a predetermined time. A buffer register (R ₀ ) to be outputted by a controller, and a divider (2) which divides the number of buffer registers by the number of adders of the adder (1), and constitutes an S-shaped acceleration / deceleration of the PLC positioning unit. As shown in FIG. 2, a plurality of blocks for linear acceleration and deceleration are connected in series.

Referring to the conventional linear acceleration / deceleration configured as described above, first, when the input speed point f _i (k) is input, the input speed point is sampled through _m buffer registers R ₁ -R _m and delayed for a predetermined time. When the delayed value is input to the inverting terminal (-) of the adder 1, it is added from the input speed point f _i (k) and the adder 1 inputted to its non-inverting terminal (+), and eventually [f _i (k ) -f _i (km)], which is divided by the number of buffer registers (m) through the divider (2), resulting in [f _i (k) -f _i (km)] / m.

At this time, the added output of the adder (1) buffer registers (R ₀₎ because it is input to the input terminals which delay the final output once the end value of the feedback is an adder (1) through a final value (f ₀ (k) to be outputted to a )silver

(f ₀ (k)) = [f _i (k) -f _i (km)] m + f ₀ (k-1)... … … … … … … … … … … … … … (One)

For example, if the sample period is given by T _S , the acceleration and deceleration time is set to t _acc / _dec = T _S. For example, assuming that the input function f _i (k) is determined by the step function outputting 10 pulses for each sampling, the sampling time is 10 msec and the number of buffer registers (m) is 5, the accel / decel time is t _acc / _dec. = T _S = 50 msec.

It is calculated | required repeatedly from said Formula (1).

For example, if f ₁ (k) = 10

f ₀ (1) = [10-0] / 5 + f ₀ (0) = 2

f ₀ (2) = [10-0] / 5 + f ₁ (0) = 4

f ₀ (3) = [10-0] / 5 + f ₂ (0) = 6

f ₀ (4) = [10-0] / 5 + f ₃ (0) = 8

f ₀ (5) = [10-0] / 5 + f ₄ (0) = 10

And in the deceleration section, the calculation is reversed. The following basic equation is produced by serially connecting hardware with linear acceleration / deceleration characteristics calculated in this way.

f ₁ (k) = [f _i (k) -f _i (km ₁ )] / m ₁ + f ₁ (k-1)

f ₂ (k) = [f ₁ (k) -f ₁ (km ₂ )] / m ₂ + f ₂ (k-1)

f _0P (k) = [f _(P-) (k) -f _(P-) (km)] / m _P + f _0P (k-1)

Where mj, j = 1, 2,... , P denotes the number of buffer registers in the linear acceleration / deceleration configuration.

By suitably combining the size of P and the sizes of mjs, the desired S-shaped acceleration / deceleration characteristics can be obtained.

However, in order to implement such a conventional acceleration / deceleration pattern, hardware is configured, and in the case of an S-shaped acceleration / deceleration pattern, the hardware configuration is complicated by using a series of linear acceleration / deceleration hardware in combination. Since a digital signal processing (DSP) chip or the like must be used, the price increases.

Therefore, in order to solve the conventional problem, the present invention calculates a desired speed by using a multiplier, an adder, and a divider, obtains a pulse to be output for each sample section, and actually outputs a pulse to the motor to control the speed. The acceleration / deceleration control apparatus of the PLC positioning unit is invented, and will be described in detail below with reference to the accompanying drawings.

Turning first to the third output to the invention as a component for the S-curve and a deceleration factor of said position determining unit Piel also multiplied by the factor corresponding to receiving the input speed points (Y ₁ -Y ₄₎ as shown In Acceleration and deceleration of the third multiplier 1-3, the first to third adders 4-6 for adding the respective output values of the first to third multipliers 1-3, and the sample interval, that is, the counter value First and second dividers (7) (8) for dividing the outputs of the first and third adders (4) and (6) by the value divided by the number of steps, and the first dividers (7) and the second. A fourth adder 9 that adds to the output value of the adder 5, and third and fourth adders 6 through the first input speed point Y ₁ and the second and third dividers 8, 10; (9) comprises a fifth adder 11 to which the output value is added.

Referring to the operation and effects of the present invention configured as described above in detail.

If the user inputs the desired target velocity, four points required to use the Bezier Algorithm are obtained, and the velocity corresponding to each sampling section is calculated from the Bezier algorithm by the acceleration / deceleration time.

Velocity calculation by the Bezier Algorithm proceeds in the following order.

t = count / N _acc or N _dec ... … … … … … … … … … … … … … … … … … (2)

Where count≤N _acc or N _dec

Where N _acc or N _dec is the acceleration / deceleration time step number and the count is incremented for each sampling.

As shown in the flowchart of FIG. 4, when the user inputs a desired target speed, four points required to use the Bezier algorithm are calculated. When the calculated input speed points (Y ₁ -Y ₄ ) are input, the input is performed. In the first multiplier 1, Y ₁ is multiplied by -1, Y ₂ is multiplied by 3, Y ₃ is multiplied by -3, and Y ₄ is output to the first adder 4 as it is. In the second multiplier 2, Y ₁ is multiplied by 3, Y ₂ is multiplied by -6, and Y ₃ is multiplied by 3 to output to the second adder 5, and the third multiplier 3 is -3 in Y ₁ . Y ₂ is multiplied by 3 and output to the third adder 6.

Then, the values t _ay , t _by , and t _cy output through the first to third adders 4-6 are as follows.

t _ay = -1 x Y ₁ +3 x Y ₂ -3 x Y ₃ + Y ₄ . … … … … … … … … … … … … … … (3)

t _by = 3 x Y ₁ -6 x Y ₂ +3 x Y ₃ . … … … … … … … … … … … … … … … … … (4)

t _cy = -3 x Y ₁ +3 x Y ₂ . … … … … … … … … … … … … … … … … … … … … (5)

Acceleration / deceleration of the count value i through the first divider 7 as shown in equation (2) is the output t _ay of the first adder 4 having the same value as the above formula (3). Divide by the value t divided by the number of steps m. When the fourth adder 9 adds and outputs the divided value and the output of the second adder 5, the third divider 10 divides the output in the same manner. In the second divider 8, the output of the third adder 6 is also divided in the same manner as in the first divider 7.

If the count value is greater than the acceleration / deceleration time step number N _ac or N _dec , the process ends without further progressing. If the count value is not greater than the acceleration / deceleration time step number N _acc or N _dec , the fifth adder 11 may include the first point Y ₁ and the third divider of the input speed points Y _{1 to} Y ₄ . The output of the fourth adder 9 divided by 10) and the output value of the third adder 6 divided by the second divider 8 are respectively input from the fifth adder 11 in each sampling period. Calculate the output speed. This is expressed as follows.

V ₀ = {[t _ay × t] + t _by } × t + t _cy × t + Y ₁ . … … … … … … … … … … … … … … (6)

The S-shape and the exponential deceleration / deceleration pattern can be obtained by making and outputting the pulse amount to be output for each sample from the obtained speed.

As described in detail above, the present invention calculates the speed of the actual acceleration / deceleration pattern, obtains the pulse to be output for each sampling period, and actually outputs the pulse to the motor to control the speed.

Claims (1)

The first to third multipliers (1-3) and the respective output values of the first to third multipliers (1-3) are added to receive the input speed points (Y _{1 to} Y ₁ ) and multiply the corresponding factors. The first to third adders 4-6 and the sample interval (counter value) divided by the acceleration / deceleration step numbers to divide the outputs of the first and third adders 4 and 6, A second adder (7) (8), a fourth adder (9) that adds to the output values of the first adder (7) and the second adder (5), the first input speed point (Y ₁ ), PLC positioning consisting of a fifth adder 11 configured to add the output values of the third and fourth adders 6 and 9 through the second and third dividers 8 and 10 to obtain a final speed. Acceleration / deceleration control device of the unit.