KR950010664B1 - Thin Film Transistor Liquid Crystal Display Device - Google Patents
Thin Film Transistor Liquid Crystal Display Device Download PDFInfo
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- KR950010664B1 KR950010664B1 KR1019920020498A KR920020498A KR950010664B1 KR 950010664 B1 KR950010664 B1 KR 950010664B1 KR 1019920020498 A KR1019920020498 A KR 1019920020498A KR 920020498 A KR920020498 A KR 920020498A KR 950010664 B1 KR950010664 B1 KR 950010664B1
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- 239000010409 thin film Substances 0.000 title claims description 25
- 239000004973 liquid crystal related substance Substances 0.000 title claims description 19
- 230000001939 inductive effect Effects 0.000 claims description 15
- 229910000859 α-Fe Inorganic materials 0.000 claims description 9
- 238000003491 array Methods 0.000 claims description 2
- 239000010408 film Substances 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 230000014759 maintenance of location Effects 0.000 description 5
- 230000003071 parasitic effect Effects 0.000 description 5
- 229910021417 amorphous silicon Inorganic materials 0.000 description 4
- 101000619472 Homo sapiens Lateral signaling target protein 2 homolog Proteins 0.000 description 2
- 102100022150 Lateral signaling target protein 2 homolog Human genes 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 230000007847 structural defect Effects 0.000 description 2
- 230000032683 aging Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 150000003377 silicon compounds Chemical class 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
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Abstract
내용 없음.No content.
Description
제1도는 종래의 박막트랜지스터 액정표시 소자의 판넬구조도.1 is a panel structure diagram of a conventional thin film transistor liquid crystal display device.
제2도는 제1도의 단위화소의 등가회로도.2 is an equivalent circuit diagram of unit pixels of FIG.
제3도는 본 발명의 박막트랜지스터 액정표시 소자의 판넬구조도.3 is a panel structure diagram of a thin film transistor liquid crystal display device of the present invention.
제4도는 제3도의 단위화소의 등가회로도.4 is an equivalent circuit diagram of unit pixels of FIG.
제5도는 본 발명의 단위화소의 구조평면도.5 is a structural plan view of a unit pixel of the present invention.
제6도는 제5도의 A-A선 단면도이다.6 is a cross-sectional view taken along the line A-A of FIG.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
Cst : 저장용 정전용량 Lst : 유도리액턴스Cst: capacitance for storage Lst: inductive reactance
10 : 게이트부 20 : 드레인부10: gate portion 20: drain portion
30 : 소오스부 40 : 픽셀부30: source portion 40: pixel portion
50 : 페라이트 층 a-Si : H : 수소화비정질규소50: ferrite layer a-Si: H: hydrogenated amorphous silicon
본 발명은 박막트랜지스터 액정표시소자에 관한 것으로, 특히 박막트랜지스터를 스위칭소자로 하는 복수배열의 액정표시소자에서 각 저장용 정전용량에 직렬 또는 병렬로 유도형 리액턴스가 설치된 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a thin film transistor liquid crystal display device. In particular, in a multiple array liquid crystal display device using a thin film transistor as a switching device, an inductive reactance is provided in series or parallel to each storage capacitance.
일반적으로 박막트랜지스터를 스위칭소자로 하는 복수배열의 표시소자는 각 박막트랜지스터의 게이트와 드레인단에 각각 주사전극 구동회로와 데이타 신호전극 구동회로를 연결 사용하여 구동된다.In general, a plurality of arrays of display devices using thin film transistors as switching elements are driven by connecting scan electrode driving circuits and data signal electrode driving circuits to gate and drain terminals of the thin film transistors, respectively.
이는 제1도와 같이 도시할 수 있는바, 판넬상에 다수의 박막트랜지스터(Q)를 행과 열에 따라 배열 구성하고, 주사전극 구동회로(X)에 의한 각 주사전극(X1~Xn)은 각 행 상태로써 제공되고, 각 행에는 데이타 신호전극 구동회로(Y)의 데이타 신호전극(Y1~Ym)에 상응하는 갯수의 각 박막트랜지스터(Q) 게이트단이 각각 제공되며, 데이타 신호전극 구동회로(Y)에 의한 데이타 신호전극(Y1~Ym)은 각 열 상태로써 제공되고, 각 열에는 주사전극 구동회로(X)의 주사전극(X1~Xn)에 상응하는 갯수의 각 박막트랜지스터(Q) 드레인단이 각각 제공된다. 이때 단위 박막트랜지스터를 스위칭소자로 하는 단위화소의 등가회로는 제2도와 같이 도시할 수 있는바 임의의 주사전극(Xi)에 선택된 트랜지스터(Qi)의 게이트가, 임의의 데이타 신호전극(Yi)에 선택된 트랜지스터(Qi)의 드레인이 접속되고, 그 소오스에는 액정층의 화소(Pixel) 정전용량(Clc) 및 저장용 정전용량(Cst)이 인가되고, 화소정전용량(Clc)에는 저항(RlC)이, 선택된 트랜지스터(Qi)의 게이트와 소오스에는 기생정전용량(Cgs)이 형성되는 것으로 도시할 수 있다. 즉, 임의의 주사전극(Xi)과 데이타 신호전극(Yi)이 선택되어 해당화소의 선택된 트랜지스터(Qi)가 턴온되어 데이타 신호전극 구동회로(Y)에서 전달하고자 하는 데이타가 화소정전용량(Clc)으로 표시된 액정유전체에 대전되어 데이타를 축전함으로써 액정화소를 표시할 수 있게된다. 그러나 제조시 구조적 결함등에 의하여 원치도 않는 기생정전용량(Cgs)이나 트랜지스터(Qi) 또는 액정등의 누설전류로 인하여 전압강하 및 디케이(Decay)등이 생겨 심할경우 화소자체가 어둡거나 플릭커링(Flickering ; 깜박거리는 현상)등이 생기기 쉽고 전체적인 화질이 나빠지면 노화현상이 두드러지게 나타나는 단점이 있었다.As shown in FIG. 1, a plurality of thin film transistors Q are arranged in rows and columns on a panel, and each scan electrode X1 to Xn by the scan electrode driver circuit X is arranged in each row. Each row is provided with a number of gate ends of the thin film transistors Q corresponding to the data signal electrodes Y1 to Ym of the data signal electrode driving circuit Y, and the data signal electrode driving circuit Y is provided in each row. Data signal electrodes Y1 to Ym are provided in respective column states, and in each column, the number of drain terminals of each thin film transistor Q corresponding to the scan electrodes X1 to Xn of the scan electrode driving circuit X is provided. Each of these is provided. At this time, the equivalent circuit of the unit pixel using the unit thin film transistor as the switching element can be shown in FIG. 2, where the gate of the transistor Qi selected to the arbitrary scan electrode Xi is connected to the arbitrary data signal electrode Yi. A drain of the selected transistor Qi is connected, a pixel capacitance Clc and a storage capacitance Cst of the liquid crystal layer are applied to the source thereof, and a resistor RlC is applied to the pixel capacitance Clc. The parasitic capacitance Cgs may be formed in the gate and the source of the selected transistor Qi. That is, the arbitrary scan electrode Xi and the data signal electrode Yi are selected, the selected transistor Qi of the corresponding pixel is turned on so that the data to be transferred from the data signal electrode driving circuit Y is pixel capacitance Clc. A liquid crystal pixel can be displayed by charging the liquid crystal dielectric indicated by " " However, if the voltage drops and decay occur due to undesired parasitic capacitance (Cgs), transistor (Qi) or liquid crystal leakage current due to structural defects during manufacturing, the pixel itself is dark or flickering. Aging phenomenon is prominent when the image quality deteriorates easily.
본 발명은 이를 해결코자 연구개발한 결과 저장정전용량에 직렬 또는 병렬상태로 유도형 리액턴스를 연결시켜 데이타 보유상태 및 시간을 안정케함을 특징으로 한다.In order to solve this problem, the present invention is characterized by stabilizing the data retention state and time by connecting the inductive reactance in series or parallel state to the storage capacitance.
즉, 박막트랜지스터를 스위칭소자로 하는 복수배열의 액정표시소자에서, 각 박막트랜지스터의 소오스단에 화소정전용량과 별도로 등가적으로 저장용 정전용량과 직렬 또는 병렬로 접속되는 유도리액턴스 특성을 가지는 페라이트 필름층을 접속시키도록한 것이다.That is, in a multi-array liquid crystal display device using a thin film transistor as a switching element, a ferrite film having an inductive reactance characteristic connected in series or in parallel with a storage capacitance equivalently to a pixel capacitance at a source end of each thin film transistor. To connect the layers.
이를 위해 본 발명은 각 박막트랜지스터의 소오스단에 픽셀층과 별도로 등가적으로 저장용정전용량과 유도리액턴스 특성을 갖는 페라이트층을 게이트층과 일정간격을 두고 나란하게 형성시킨 것이다.To this end, in the present invention, a ferrite layer having a storage capacitance and an inductive reactance characteristic is formed side by side with the gate layer at the source end of each thin film transistor to be equivalent to the pixel layer.
이하 도면을 참조하여 상세히 설명하며 종래와 동일한 부분을 동일부호로 표시한다.DETAILED DESCRIPTION Hereinafter, the same parts as in the prior art will be described with reference to the drawings.
제3도는 본 발명의 박막트랜지스터 액정표시소자를 액티브 매트릭스판넬 구조상태로 도시한 것으로, 주사전극구동회로(X)의 각 주사전극(X1~Xn)과, 데이타 신호전극 구동회로(Y)의 데이타 신호전극(Y1~Ym)을, 행과 열로 배열된 박막트랜지스터(Q)의 게이트와 드레인단에 각각 매트릭스 상태로 제공하고 ; 각 트랜지스터(Q)의 소오스단에는 저장정전용량(Cst)과 유도리액턴스(Lst)가 병렬접속된다.3 shows the thin film transistor liquid crystal display device of the present invention in an active matrix panel structure, in which the scan electrodes X1 to Xn of the scan electrode driver circuit X and the data of the data signal electrode driver circuit Y are shown. The signal electrodes Y1 to Ym are provided in a matrix state at the gate and drain terminals of the thin film transistor Q arranged in rows and columns, respectively; The storage capacitance Cst and the inductive reactance Lst are connected in parallel to the source terminal of each transistor Q.
제4도는 본 발명의 박막트랜지스터 액정표시소자의 단위화소 등가회로도로써, 임의의 주사전극(Xi)이 선택된 트랜지스터(Qi)의 게이트에 인가되고, 임의의 데이타 신호전극(Yi)이 선택된 트랜지스터(Q1)의 드레인단에 제공되며, 소오스단에 액정층의 화소정전용량(Clc) 및 저항(Rlc)이 병렬로 연결되며, 게이트와 소오스단에는 기생정전용량(Cgs)이 발생함은 종래와 같다.4 is a unit pixel equivalent circuit diagram of a thin film transistor liquid crystal display device according to an embodiment of the present invention, in which an arbitrary scan electrode Xi is applied to a gate of a selected transistor Qi, and an arbitrary data signal electrode Yi is selected. ), The pixel capacitance Clc and the resistor Rlc of the liquid crystal layer are connected in parallel to the source terminal, and the parasitic capacitance Cgs is generated at the gate and the source terminal.
이에더하여 본 발명은 저장용정전용량(Cst)과 병렬로 유도리액턴스(Lst1)를, 또는 점선상태와 같이 직렬로 유도 리액턴스(Lst2)를 접속시킨다.In addition, the present invention connects the inductive reactance Lst1 in parallel with the storage capacitance Cst, or the inductive reactance Lst2 in series as in the dotted line state.
제5도는 본 발명에서의 단위화소의 평면도이고, 제6도는 제5도의 A-A선 단면도로써 게이트부(10)가 행으로 위치되고, 게이트부(10)의 일부 돌출된 부위 일단에는 게이트부(10)와 직각인 열방향으로 드레인부(20)가 위치되며, 드레인부(20)와 반대방향의 게이트부(10)의 돌출된 부위 일단에는 소오스부(30)가 위치되며, 페라이트 필름층(50) 상부에 위치하고 소오스부(30) 일부를 포함하는 부위에 투명전극의 픽셀부(40)가 위치되고, 게이트부(10)와 직각방향으로 픽셀(40) 하부에는 저장용 정전용량(Cst) 및 유도형 리액턴스(Lst) 기능을 수행하는 페라이트(Ferrite) 필름층(50)을 형성한다.5 is a plan view of a unit pixel according to an exemplary embodiment of the present invention, and FIG. 6 is a cross-sectional view taken along line AA of FIG. The drain portion 20 is positioned in a column direction perpendicular to the second side, and the source portion 30 is positioned at one end of the protruding portion of the gate portion 10 opposite to the drain portion 20, and the ferrite film layer 50 is disposed. The pixel portion 40 of the transparent electrode is positioned on a portion including the source portion 30, and the storage capacitance Cst and the lower portion of the pixel 40 in a direction perpendicular to the gate portion 10. A ferrite film layer 50 performing an inductive reactance (Lst) function is formed.
상기에서 본 발명은 페라이트 필름층(50)이 등가적으로 저장용 정전용량(Cst)과 직렬 또는 병렬상태로 유도형 리액턴스(Lst)가 결합된 특성을 가지고 있음을 발견하고 이를 본 발명에 적용하였다.The present invention has been found that the ferrite film layer 50 has the characteristic that the inductive reactance (Lst) is equivalently coupled to the storage capacitance (Cst) in series or parallel state and applied to the present invention. .
결국 임의의 주사전극(Xi)과 데이타 신호전극(Yi)이 선택되었다 할때 해당화소(Pixel)에 대한 박막트랜지스터((Q)는 일반적 표현이고 임의로 선택된 것은 제4도와 같이 (Qi)로 표시함)가 턴온되어 데이타 신호전극 구동회로(Y)에서 전달하고자 하는 데이타가 액정층의 화소정전용량(Clc) 유전체에 대전되어 데이타를 축전하고 있다가 공정상, 구조적 결함으로 기생정전용량(Cgs)이나 액정등의 누설전류등에 의해 전압강하 요인이 생겨도 유도리액턴스(Lst1 or Lst2)가 자체특성에 의해 이를 반발하여 원래의 전압을 유지케하므로 데이타 보유상태와 보유시간을 안정되게끔 증가시켜 화소자체의 어둠현상이나 깜빡거리는 플릭커링(Flickering) 현상등을 예방하여 전체 화질개선과 수명연장 및 소비전력감소 등을 피할 수 있다. 아울러 제5도 및 제6도에서와 같이 박막트랜지스터를 이루는 소오스부(30)(예를들어 n+층) 위에 페라이트 필름층(50)의 박막을 증착하여 능동층(a-Si 비정질규소화합물층)의 광차단 역할 및 유도리액턴스를 유발할 수 있게된다.After all, when a certain scan electrode (Xi) and data signal electrode (Yi) is selected, the thin film transistor (Q) for the pixel (Pixel) is a general expression and the arbitrarily selected one is represented by (Qi) as shown in FIG. ) Is turned on and the data to be transmitted from the data signal electrode driving circuit (Y) is charged to the pixel capacitance (Clc) dielectric of the liquid crystal layer to accumulate the data.As a result of the structural defect, the parasitic capacitance (Cgs) Induced reactance (Lst1 or Lst2) resists this by its own characteristics and maintains the original voltage even when voltage drop occurs due to leakage current of liquid crystal lamps, so that the data retention state and retention time are increased to stabilize the darkness of the pixel itself. By preventing phenomena or flickering flickering, it is possible to avoid the improvement of the overall quality, the extension of the life and the reduction of power consumption. In addition, as shown in FIGS. 5 and 6, a thin film of the ferrite film layer 50 is deposited on the source portion 30 (for example, the n + layer) forming the thin film transistor to form an active layer (a-Si amorphous silicon compound layer). It is possible to cause the light blocking role and inductive reactance.
이상과 같이 본 발명은 박막트랜지스터를 스위칭소자로 하는 복수행열 배열의 액정표시소자에서 각 박막트랜지스터의 소오스단에 저장용정전용량과 유도리액턴스를 겸하는 페라이트 필름층을 결합시켜 기생용량이나 누설전류에 의해 전압강하가 발생할 경우 유도리액턴스가 이를 반발하여 데이타 보유상태와 보유시간을 안정되게끔 증가시키므로 전체화질 개선과 수명연장 및 소비전력 감소를 이루어 대형 고화질 표시소자 제조와 홀딩타임 개선 및 플릭커링등의 문제를 해결가능하다.As described above, the present invention combines a ferrite film layer having both a storage capacitance and an inductive reactance at a source terminal of each thin film transistor in a liquid crystal display device having a multi-row array as a switching element, thereby causing parasitic capacitance or leakage current. In case of voltage drop, inductive reactance rebounds to increase data retention state and retention time stably, resulting in improvement of overall quality, extended life and reduced power consumption, and problems such as large size display device manufacturing, holding time improvement and flickering It is possible to solve.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019920020498A KR950010664B1 (en) | 1992-11-03 | 1992-11-03 | Thin Film Transistor Liquid Crystal Display Device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019920020498A KR950010664B1 (en) | 1992-11-03 | 1992-11-03 | Thin Film Transistor Liquid Crystal Display Device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR940011985A KR940011985A (en) | 1994-06-22 |
| KR950010664B1 true KR950010664B1 (en) | 1995-09-21 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019920020498A KR950010664B1 (en) | 1992-11-03 | 1992-11-03 | Thin Film Transistor Liquid Crystal Display Device |
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|---|---|
| KR (1) | KR950010664B1 (en) |
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1992
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| KR940011985A (en) | 1994-06-22 |
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