KR950010565B1 - Video RAM for High Speed Serial Light Transmission - Google Patents

Abstract

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Description

Video RAM for High Speed Serial Light Transmission

1 (a) and (b) show a serial write transmission operation according to the prior art.

1C is a block diagram of a block selection signal generation circuit according to the prior art.

2 is a diagram showing a serial write transmission operation according to the present invention.

3 is a block diagram of a block selection signal generation circuit according to the present invention.

4 is an operation timing diagram of a block selection signal generation circuit according to the present invention.

5 is a diagram conceptually illustrating a serial write transmission operation according to the present invention.

6 is a block diagram of a data transmission pulse generating circuit according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a dual port memory of a semiconductor memory device, and more particularly to a video RAM for a high speed serial write transfer operation.

Video RAM is a dual port memory having a random access memory (RAM) (hereinafter referred to as "RAM") and a serial access memory (SAM) (hereinafter referred to as "sam"). Memory devices are widely used in high-definition television (VTR), high-definition television (HDTV), etc. Video RAM has random access from the central processing unit (CPU) and read-only access for displaying the CRT (Cathod Ray Tube). The video RAM has functions such as serial read transfer and serial write transfer for input and output of serial data, and serial read transfer is stored in a random port (RAM). Refers to the operation to send the data to the serial port (Sam) and read it. The serial write transmission is to write predetermined data to the serial port (Sam). After said operations to storage to send it to the random port (RAM). The serial write transfer is a function that the application where to require a high-speed data processing such as the particular image as a very important function in the video RAM.

FIG. 1 is a diagram illustrating a serial write transmission operation according to the prior art, and a fountain structured by four blocks M'1, M'2, M'3, and M'4 is exemplarily illustrated. A RAM constructed of blocks M1, M2, M3, and M4 corresponding to each of the blocks M'1, M'2, M'3, and M'4 is shown.

Referring to FIG. 1, predetermined data input through a data input buffer (not shown) is written to a block of a fountain selected according to a signal generated by the block select signal generation circuit 20. As shown in FIG. FIG. 1 (a) is a diagram showing that the M'1 block is selected among the blocks of Sam, and FIG. 1 (b) is a diagram showing that the M'2 block is selected among the blocks of the Sam. 1C is a diagram showing the configuration of the block selection signal generation circuit 20 for selecting a block of a fountain. The block select signal generation circuit 20 outputs a signal for selecting a block of a sample by logically multiplying the block select address inputted from the address input burner 10 and the block select enable clock. The address input buffer 10 buffers an address input from the outside as a normal address input buffer and outputs it as an internal address of the block selection signal generation circuit 20.

Referring to FIG. 1 (a), data written to the M'1 block of Sam is stored in the RAM according to the DTP generated by the data transfer pulse generating circuit 1 (hereinafter referred to as "DTP"). Sent to M1 block. A process of executing serial write transfer operation to another RAM in succession is shown in FIG. Referring to FIG. 1B, in order to perform serial write transfer operation to the M2 block of the RAM, the block selection signal generation circuit 20 performs an operation of serially writing the input data to the M'2 block of Sam. . Then, the data written to Sam's M'2 block is serially transmitted to the M2 block of RAM through the control of the DTP generation circuit (1).

Summarizing the serial write transfer operation according to the prior art, in order to perform a serial write transfer operation to i predetermined blocks of RAM, after writing data to one block of Sam, the written data is transferred to one block of RAM, Again, after writing data to another block of Sam, the process of transferring the written data to another block of RAM must be repeated i times. This serial write transfer operation represents a serial write transfer operation currently widely used in the art.

However, the serial light transmission operation according to the prior art is a big obstacle in the field requiring high speed data processing such as image processing, which is also the next generation ASIC (Application Specific IC) which needs to process a large amount of data at high speed. , Field memory, graphic memory, and so on.) Memory remains a problem to be solved.

Accordingly, an object of the present invention is to provide a video RAM for the serial light transmission operation is fast to perform data processing at a high speed.

Another object of the present invention is to provide a block selection signal generation circuit for selecting all blocks of a fountain during a serial write transmission operation of a video RAM.

In order to achieve the above objects, the present invention selects all the blocks of the Sam in the write operation and writes data to all the selected blocks, and selectively writes the data written in the Sam's block into the predetermined subblock of the RAM during the serial transfer operation. Characterized in that the transmission.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. Hereinafter, the serial write transmission operation according to the present invention will be described by dividing the write operation of writing data into the sam and the serial transmission operation of transmitting data written into the RAM.

FIG. 2 includes a second diagram (a) and a second diagram (b), each of which shows a serial write transmission operation according to the present invention.

First, the serial write transmission operation according to the present invention will be described with reference to FIG. As shown, when the block select signal generation circuit 20 enables all the fountains, data is written to the fountains by one selection operation. After that, the data written to all the blocks of the Sam is serially transmitted only to a predetermined block of the RAM selected by the control of the DTP generation circuit 30.

Next, referring to FIG. 2 (b), the serial write transmission operation according to the present invention includes a RAM in which a plurality of blocks are divided into two subblocks, and a block connected to each subblock of the RAM. Applies to the fountain. Here, the input port is not shown, and this input port is connected to Sam 1 and Sam 2 and related to input and output of data data. In Fig. 2B, the configuration on the upper side indicates a write operation. If either one of Sam 1 or Sam 2 is selected, the data transmitted from the input port is recorded in all blocks of the selected Sam. In other words, in the prior art, when data data is written to a block of SAM, another block cannot be selected first until one serial transmission operation is completed. Therefore, in the present invention, data data is written to all blocks and a data transmission enable signal. When is generated, select a block of RAM to perform serial transfer operation. 2 (b) shows that all the blocks of Sam 2 are selected as an embodiment of the present invention.

The configuration in the lower side of the drawing in the direction of the arrow in FIG. 2 (b) shows a serial transfer operation when using the block selection signal generating circuits 20A and 20B according to the present invention. When the write operation shown in the upper configuration of FIG. 2 (b) is completed, the subblock of the RAM to which the data is to be transmitted is selected and the data is transmitted to the subblock of the selected RAM under the control of the DTP generation circuit 30B. do. Considering the characteristics of the RAM that can be randomly accessed by address designation, when the block selection signal generation circuits 20A and 20B according to the present invention are used, a plurality of subblocks of RAM can be simultaneously selected during serial transmission operation. In an embodiment of the present invention, two subblocks of RAM are simultaneously selected. The RM1 subblock of the M1 block of the RAM and the RM3 subblock of the M3 block are selected to transmit data data. At this time, the DTP generation circuit 30B connects the RM'1 and RM'3 blocks of the SAM 2, which store the data to be transmitted, to the RM1 and RM3 subblocks of the corresponding RAM, and does not connect other blocks. As an embodiment of the present invention, the subblock of the RAM to which the data data is to be transmitted may be selected by addressing using, for example, Row Addres RA7 or RA8.

3 is a diagram illustrating a configuration of the block selection signal generation circuit 20 of FIG. 2 provided to perform a serial write transmission operation according to the present invention. 5 is a block diagram conceptually illustrating the serial write transmission operation according to the present invention.

Referring to Fig. 3, the configuration of the block selection signal generation circuit 20 according to the present invention will be described. The block selection signal generation circuit 20 inputs and transmits? DTE, which is a data transmission enable signal, as a control signal, and inputs and transmits BLSC, which is a block selection signal, and? WTE, which is a write transmission enable signal (light transmission master click), respectively. First and second latch circuits 32 and 33: L1 for latching output signals of the first and second transmission stages TM1 (TM2) and the first and second transmission terminals TM1 (TM2), respectively ( 35, 36: L2, a first NAND gate 37 for one input of the output of the first and second latch circuits 32, 33: L1 (35, 36: L2), and a first latch circuit, respectively. Outputs of the first and second latch circuits 37 and 38, and the second NAND gate 38 for performing one input of the inverted signal of the output signal of L1 and the output signal of the second latch circuit L2, respectively. Latches the output signals of the third and fourth transmission terminal TM3 (TM4) and the third and fourth transmission terminal TM3 (TM4), which are controlled by the control of the? RTE signal, which is a read transmission enable signal. Having a predetermined light through It consists of: (L4 44, 45) the third and the fourth latch circuit (41, 42, L3) for outputting the other. Each output end of the third and fourth latch circuits L3 and L4 is controlled by the inverter 40 and the inverter 43 and øINT, which is an initial value setting signal. Transistors 46 and 47 for initial value setting are set.

In FIG. 3, when the data transmission enable signal? DTE is in the " high " state, the block selection signal BLSC and the write transmission enable signal? WTE are passed through the first and second transmission terminals TM1 and TM2. The latch circuit L1 is transferred to L2. The signal BLSC and the signal? WTE transmitted to the first and second latch circuits L1 and L2 are the first even when the first and second transmission terminals TM1 and TM2 are turned off because the signal? DTE is turned "low". And an initial input state by the second latch circuit L1 (L2). The output signals of the first and second latch circuits L1 and L2 are input to the third and fourth transmission terminals TM3 and TM4 via the NAND gates 37 and 38, and at this time, a read transfer enable signal. When? RTE (Read Transfer Enable) becomes " low ", it is transferred to the third and fourth latch circuits 13 (L4). The third and fourth latch circuits L3 and L4 also maintain their input state regardless of turning off of the third and fourth transfer terminals TM3 and TM4. The transistors 46 and 47 "low" the initial state of the third and fourth latch circuits L3 and L4 by the signal? INT as a VCC start-up clock that generates a power supply voltage. Set to. The outputs of the third and fourth latch circuits L3 and L4 are generated as block selection information signals? BSI1 and? BSI2 for selecting a block of the thumb via the inverters 40 and 43.

In order to perform the above-described serial write transfer operation, the signal? BSI1 is connected to select the M'1 block and the M'3 block of Sam 2 of FIG. 2 (a), and the signal? BS12 is the M 'block, M' of the Sam 2; 3 blocks are selected to select. The signal? DTE and the signal? WTE are respectively input in the " high " state, and the block select signal generation circuit 20 constructed as shown in Fig. 3 selects all the blocks of the spring regardless of the signal BLSC value.

4 is an operation timing diagram of the block selection signal generation circuit 20 during the serial write transmission operation according to the present invention. When the signals? DTR and? WTE in the " high " state are input, respectively, the output signal passing through the NAND gates 37 and 38 indicates the " high " state at points A and B, respectively, regardless of the state of the signal BLSC. These output signals are again input to the third and fourth transmission stages TM3 and TM4, and show "low" states at points C and D via the third and fourth latch circuits L3 and L4, respectively. The output signals of the third and fourth latch circuits L3 and L4 pass through the inverters 40 and 43, respectively, and output the block selection information signals? BSI1 and? BSI2 in the "high" state, and consequently all the blocks M of Sam. '1-M'4 is selected.

To help understand the above operation, the serial write transmission operation according to the present invention will be described with reference to the block diagram shown in FIG. After the write operation is completed on all blocks (i.e., all blocks of the fountain) through the block selection signal generation circuits 20 of FIG. 2 and 3 (54), a predetermined block to be transmitted is selected as the BLSC (55). When the predetermined data transfer pulse? DTP is enabled (56), the data written to the fountain is selectively transmitted (57) to the RAM.

On the other hand, the DTP generation circuit 30 for generating a data transmission pulse for the serial write transmission operation according to the present invention can be implemented as an embodiment as shown in FIG. 6, a low address (RA8) as shown in FIG. Appropriate control signals DTP1 to DTP4 can be output to enable only a predetermined selected block by the input of.

The block selection signal generation circuit 20 according to the present invention shown in FIG. 3 is an embodiment optimally configured to realize the spirit of the present invention, which means that logic can be used as long as the write operation can be performed on all blocks of the fountain. It is to be understood that different configurations may be considered.

As described above, the serial write transfer operation according to the present invention has the advantage of being easy to implement by writing to all the blocks of the fountain simultaneously, and the transfer operation is quick, resulting in high-speed data processing.

Claims (7)

A RAM comprising a plurality of blocks each having a predetermined number of subblocks, and a spring comprising at least one block connected to each of the plurality of blocks of the RAM; A video RAM for performing at least a serial write transfer rate of transmitting data input from the outside to the RAM and then transferring the data written to the RAM to the RAM. Block selection control means for outputting a block selection information signal for simultaneously selecting all blocks so that input data is written to each block of the fountain simultaneously; And data transmission control means for transmitting only input data written in a block connected to a block of RAM corresponding to the block selection information signal among all blocks of the SAM to a block of a RAM corresponding to the block selection information signal. Featuring video RAM. 2. The apparatus of claim 1, wherein the block selection control unit comprises: first and second transmission terminals which respectively input the address and the predetermined write transmission enable signal and are commonly operated by the control of the predetermined data transmission enable signal; First and second latch circuits for latching respective output signals of the first and second transmission stages; first and second NAND gates each having two output signals of the first and second latch circuits, respectively; And third and fourth transmission terminals commonly input by output signals of the first and second NAND gates respectively and controlled by a predetermined serial read transmission enable signal, and each of the third and fourth transmission terminals. And a third and a fourth latch circuit for outputting the first and second block selection information signals after latching the output signals, respectively. 3. The video of claim 2, further comprising an initial value setting transistor coupled to output terminals of the third and fourth latch circuits, respectively, to reset the initial states of the third and fourth latch circuits. lamb. A video RAM comprising: a RAM comprising a plurality of memory cell blocks comprising a first subblock and a second subblock; And a plurality of subblocks connected to at least one subblock of the RAM, wherein the plurality of subblocks correspond to a first thumb corresponding to the first subblocks of the RAM and to the second subblocks of the RAM. A fountain consisting of a second fountain to make; First and second transmission stages which are commonly operated by the control of the data transmission enable signal and inputting an address and a write transmission enable signal respectively specifying a predetermined block, and each output of the first and second transmission terminals; The first and second NAND gates each having two signals as inputs and a serial read transfer enable signal are operated in common. The output signals of the first and second NAND gates are respectively inputted from the outside. Third and fourth transmission stages for outputting first and second block selection information signals for writing data to the first or second fountains, and blocks of RAM corresponding to the first and second block selection information signals. Data transmission control means for transmitting only input data written to the block of the first or second fountain connected to the RAM block corresponding to the first and second block selection information signals; Video RAM, characterized in that consisting of. 5. The apparatus of claim 4, further comprising: first and second latch circuits for latching respective output signals of the first and second transmission stages, and third and latching respective output signals of the third and fourth transmission stages, respectively. And a fourth latch circuit. 6. The video according to claim 5, further comprising an initial value setting transistor connected to output terminals of the third and fourth latch circuits, respectively, to reset the initial states of the third and fourth latch circuits. lamb. 7. The method of claim 6, wherein the third and fourth latch circuits output the first and second block selection information signals for writing input data to all blocks of the first or second fountain. Video RAM.