KR950010339B1 - Error correction device - Google Patents

Abstract

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Description

Error correction device

1 is a block diagram showing an error correction apparatus of a conventional compact disk.

2 is a diagram illustrating an example of decoding of C1 and C2 codes when an error occurs in the error correction range limit of FIG.

3 is a diagram illustrating a decoding process of C1 and C2 codes when an error exceeding the error correction range of FIG. 1 occurs.

4 is a block diagram showing an error correction apparatus according to an embodiment of the present invention.

FIG. 5 is an exemplary embodiment showing a process in the case where an error occurs in FIG.

* Explanation of symbols for main parts of the drawings

1: control unit 100: C1 decoder

200: delay unit 300: first switching unit

400; 1st auxiliary memory 500: 2nd switching part

600: C2 decoder 700: third switching unit

800: second auxiliary memory 900: fourth switching unit

The present invention relates to an error correction apparatus for digital data using a decoder of a RS (Reed-Solomon) code, and more particularly, to an error correction apparatus for improving error correction capability by reducing the number of concatenation errors within a correction range within a predetermined length. It is about.

In general, RS codes are useful for data error correction when data corruption occurs due to defects that may occur in media such as disks or tapes of digital sound equipment (DAT, CD, DCD, etc.). Computer auxiliary storage devices such as hard disks, CD-ROMs, and satellite communications are widely used for the same purpose. In addition, the RS code generates an encoder for generating parity for the purpose of protecting data during reproduction of a digital signal and generates one codeword including the data and the parity, and is transmitted from the encoder. It has been used in various coding schemes in a system of an information channel protection device having a decoder which protects a received codeword from noise and then decodes it.

The dual R-S code is a non-binary BCH code that occupies an important position among Bose (Choseh-Chaudhuri-Hocquenghem (BCH)) codes, which is a type of cycle code, and is known as the most powerful code for correcting multiple errors.

FIG. 1 is a block diagram showing an error correction apparatus of a conventional compact disc player using an R-S code, and data output through an analog / digital converter (ADC) is input to a C1 decoder 10 of a (32, 28) method. The C1 decoder 10 performs error correction when there is one error, but when there are two or more errors, all 28 bytes are flagged with an erasure (error that knows the error position and does not know the error value). The deinterleaving unit 20 delays the predetermined time and outputs the C2 decoder 30 of the (28, 24) method. The C2 decoder 30 receives the data D1-D28 output from the deinterleaving unit 20 and corrects the error according to a formula for calculating an error value when the number of errors is four or less. However, if the number of errors exceeds four, only four are corrected and the rest is transmitted to the interpolator 40 connected to the rear stage.

FIG. 2a shows the output of the C1 decoder 10 when four consecutive errors occur in the data inputted through the ADC of FIG. 1, and at least one error has occurred. It is processed by an edger and input to the deinterleaving unit 20.

FIG. 2B shows the data D1-D28 input from the deinterleaving unit 20 as the error correction range limit of the C2 decoder in the C2 decoder 30 when four aggregation errors occur as shown in FIG. 2A. Shows the process of distributing errors below.

FIG. 3a shows the output of the C1 decoder 10 when five consecutive errors occur in the data inputted through the ADC of FIG. 1, and since at least one error has occurred, all 28 bytes are processed by erasure. The input is input to the C2 decoder 30 through the deinterleaving unit 20. At this time, the correction range of the C2 decoder 30 is determined within a predetermined length (CL).

FIG. 3B illustrates the decoding of data D1-D28 input from the deinterleaving unit 20 by the C2 decoder 30 when five aggregation errors occur as in FIG. 3A and the predetermined length is 27 × 4 bytes. In this case, since there is a concatenation error exceeding the correction range of the C2 decoder 30 within a predetermined length, the C2 decoder 30 cannot perform error correction.

As described above, if a predetermined number of consecutive errors exceeding the correction range of the C2 decoder 30 within a predetermined length, the C2 decoder 30 corrects the errors only until it can correct them, and the rest of the interpolation unit 40 in the next step. ).

Therefore, if a concatenation error occurs beyond the correction range of the C2 decoder within a predetermined length, the C2 decoder may not perform full error correction.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to further include a controller for controlling the use of an auxiliary memory and a flag so as to reduce the number of concatenation errors into a correction range of a C2 decoder within a predetermined length. An error correction apparatus for improving the correction capability is provided.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to further include a controller for controlling the use of an auxiliary memory and a flag so as to reduce the number of concatenation errors into a correction range of a C2 decoder within a predetermined length. An error correction apparatus for improving the correction capability is provided.

In order to achieve the above object, an error correction apparatus according to the present invention includes a C1 decoder for performing error correction when one error is detected and flagging with an eraser and delaying the output for a predetermined time when two or more errors are detected. An error correction apparatus comprising a C2 decoder for performing error correction only up to an error correction range limit when the number of errors exceeds an error correction range, wherein the error correction range is provided when the number of errors detected by the C1 decoder exceeds an error correction range. A first auxiliary memory for temporarily storing codewords exceeding and transferring to the next frame, and the first auxiliary memory for returning a codeword stored in the first auxiliary memory to an original position after an error is corrected in the C2 decoder. Second report that temporarily stores the error-free codewords that took the place of codewords stored in Control signals to a memory, first to fourth switching means for switching to temporarily store data in the first and second auxiliary memories, and to the first to fourth switching means according to the number of errors generated. It further comprises a control means for providing.

Hereinafter, an embodiment of an error correction apparatus according to the present invention will be described in detail with reference to the accompanying drawings.

4 is a block diagram of an error correction apparatus according to the present invention.

As shown in the figure, a CI decoder 100 that performs error correction only when one concatenation error occurs is connected to an output terminal of an ADC that converts analog data transmitted from an encoder (not shown) into digital data. A delay unit 200 for delaying the output of the CI decoder 100 for a predetermined period is connected to an output terminal of the CI decoder 100, and a first output terminal 01 according to a control signal to the output terminal of the delay unit 200. Alternatively, the first switching unit 300 for selectively switching the second output terminal 02 is connected.

In addition, a first auxiliary memory 400 for storing code words output from the delay unit 200 is connected to the first output terminal 01 of the first switching unit 300 when an error occurs. The first input terminal i1 of the second switching unit 500 is connected to the second output terminal 02 of the first switching unit 300, and the second switching unit 500 is connected to the output terminal of the first auxiliary memory 400. Is connected to the second input terminal i2. The C2 decoder 600 is connected to the output terminal 01 of the second switching unit 500.

Meanwhile, an input terminal i1 of the third switching unit 700 is connected to an output terminal of the C2 decoder 600, and an error is generated at the C2 decoder 600 at the first output terminal 01 of the third switching unit 700. The second auxiliary memory 800 is connected to temporarily store an error-free codeword in order to return the codeword stored in the first auxiliary memory 400 to its original position after the correction. The first input terminal i1 of the fourth switching unit 900 is connected to the second output terminal 02 of the third switching unit 700, and the fourth output terminal of the fourth auxiliary memory 800 is connected to the second output terminal 02. The second input terminal i2 of the switching unit 900 is connected.

In addition, an interpolation unit 950 for outputting an error corrected signal through a DAC is connected to the output terminal 01 of the fourth switching unit 900. The first to fourth switching units 300, 500, 700, and 900 are three-state analog switches, and are switched according to a control signal output from the controller 1. That is, the controller 10 sets the variables necessary for the control of the first to fourth switching units 300, 500, 700, and 900 as follows.

CL (Constraint Length): A fixed length in which the soft error should not exceed the maximum value, referred to as a frame in the present invention.

max_burst: The maximum value of a concatenation error that can be error corrected in the CL.

burst_count: This indicates how many aggregation errors are in the CL.

length_count: Indicates how many codewords have entered the C2 decoder 600 (0 ≦ length_count ≦ CL).

M1_count ≦ max burst).

In this case, the variables are properly combined in the controller 1 to control the switching of the first to fourth switching units.

According to the present invention configured as described above, the data input through the ADC is input to the C1 decoder 100 in the (32,38) manner. The C1 decoder 100 performs error correction when there is one error, but when there are two or more errors, all 28 bytes are flagged with an eraser and output to the delay unit 200. In the delay unit 200, The output of the C1 decoder 100 is delayed for a predetermined time and then output to the input terminal i1 of the first switching unit 300.

At this time, if it is determined that there is no error in the codeword passing through the C1 decoder 100 and the delay unit 200, the controller 1 sets the input terminal i1 of the first switching unit 300 to the second output terminal 02. The first input terminal i1 of the second switching unit 500 is connected to the output terminal 02. Accordingly, the codeword output from the delay unit 200 is input to the C2 decoder 600 of the (28, 24) method through the first and second switching units 300 and 500.

On the other hand, if it is determined that there is an error, it is input to the first auxiliary memory 400 or the C2 decoder 600 according to the number of errors.

That is, if burst_count <max_burst, the codeword output from the delay unit 200 is input to the C2 decoder 600 through the first and second switching units 300 and 500, and if the burst_count≥max_burst, the delay unit 200 The output codeword is input to the first auxiliary memory 400 through the first output terminal 01 of the first switching unit 300.

In this case, length_count does not increase when the codeword is stored in the first auxiliary memory 400. On the other hand, when the next frame is started (that is, when lenght_count = 0), the codeword in the first auxiliary memory 400 is controlled by the control signal of the controller 1 through the second input terminal i2. Is entered. Thereafter, the output of the C1 decoder 100 is input to the first auxiliary memory 400.

In addition, after the error is corrected in the C2 decoder 600, the codeword stored in the first auxiliary memory 400 should be returned to its original position. Accordingly, the third switching unit 700 transmits the error-free codeword that occupied the codeword digit entered into the first auxiliary memory 400 by the control signal of the controller 1 through the first output terminal 01. It is temporarily stored in the auxiliary memory 800. The codeword of the first auxiliary memory 400, which is error corrected in the next frame, is set to the original position. Through such a method, the codewords are arranged in the original order and input to the interpolator 950.

That is, when three consecutive errors occur in the data input through the ADC as shown in FIG. 5A, error correction is impossible in the related art. However, in the present invention, a codeword exceeding max_burst as shown in FIG. 5B is stored in the first auxiliary memory 400. The error correction is possible by temporarily storing the data in the next frame and passing it to the next frame 2.

As described above, according to the error correcting apparatus according to the present invention, a codeword exceeding the error correction range of the C2 decoder within a predetermined length is temporarily stored in the auxiliary memory, and then transferred to the next frame, thereby counting the number of concatenation errors within the correction range of the C2 decoder. In other words, it has a big effect of improving error correction ability.

Claims (1)

If the error is one, the error correction is performed, and if two or more, the C1 decoder 100 outputs the flag with an eraser and delays the predetermined time, and the number of errors detected by the C1 decoder 100 exceeds the error correction range. An error correction apparatus including a C2 decoder 600 that performs error correction only up to a written error correction range limit, wherein the code beyond the error correction range when the number of errors detected by the C1 decoder 100 exceeds the error correction range A first auxiliary memory 400 that temporarily stores a word and provides the C2 decoder 600 when an error of the next frame is corrected, and is stored in the first auxiliary memory after an error is corrected in the C2 decoder 600. A second auxiliary message for temporarily storing an error-free codeword that has occupied a codeword position stored in the first auxiliary memory 400 to return a codeword to an original position. Memory 800, first to fourth switching means 300, 500, 700, and 900 to switch to temporarily store data in the first and second auxiliary memories, and the first to fourth according to the number of errors generated. And error control means (1) for providing a control signal to the switching means (300,500,700,900).