KR950009239B1 - Burst gate pulse occurence circuit - Google Patents

Abstract

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Description

Burst Gate Pulse Generator Circuit

1 is a schematic structural block diagram of the present invention.

2 is a detailed circuit diagram of the present invention.

3A is a timing diagram for explaining the operation of the burst gate pulse generator.

3B is a timing diagram for explaining the operation of the delay signal generator.

3C is a timing diagram for explaining the operation of the reset signal generator.

* Explanation of symbols for main parts of the drawings

100, 104: burst gate pulse generator 102: delay signal generator

106: reset signal generator

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a burst gate pulse generator circuit, and more particularly to a back porch portion of a horizontal synchronous signal in which a burst signal as a reference of a color signal is generated in a video tape recorder (VTR) system. The present invention relates to a burst gate pulse generation circuit composed of logic for generating pulses and accurately recording and reproducing the color of a color signal.

The burst signal is a color carrier of about 4.8 kHz after the horizontal sync signal among the composite video signals. In general, the NTSC (National Television System Committee) method uses a frequency of 3.57 MHz (Mega Hertz).

In addition, the burst gate pulse is a pulse that is active during the period in which the burst signal is input from the composite video signal, and detects the burst signal included in the composite video signal, and the detected burst signal is applied to the local oscillator so that the color signal can be demodulated. To generate a signal.

In general, in order to generate a burst gate pulse, a television (Television) system generates a burst gate pulse by inputting a fly back pulse (FBP).

For a technique for generating a burst gate pulse in the TV system, reference may be made to an already filed patent (application number 92-18786).

However, there is a problem in that the retrace pulse is applied only to a TV system and is not applicable to a VTR system.

In addition, since the burst gate pulse generation circuit used in the conventional VTR system is an analog circuit, it not only occupies a larger volume than a full logic circuit, and it is difficult to induce cost reduction.

Accordingly, an object of the present invention is to solve the above problems and to provide a burst gate pulse generation circuit which is configured as a logic circuit and can be miniaturized.

In order to achieve the above object, the present invention provides a burst gate pulse generation circuit comprising a horizontal synchronous signal and a reference clock as inputs, and a back porch section in which a burst signal is present among elements constituting a composite video signal. By counting the reference clock with the reference clock as input to generate a pulse during the back porch period, a burst gate pulse generator for generating a burst gate pulse, the horizontal synchronization signal and a predetermined delay signal as input A reset signal generator for providing a reset signal to the burst gate pulse generator by latching the horizontal synchronization signal and the delay signal, and a predetermined first output signal from the reference clock and the burst gate pulse generator; Delay the first output signal by a predetermined time Delay signal generator for outputting a delay signal by characterized in that it includes parts.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a schematic structural block diagram of the present invention. Referring to FIG. 1, a configuration of the burst gate pulse generation circuit is as follows.

A burst gate pulse is output by inputting an output pulse of the hex counter 104 and the hex counter 104 that outputs l pulses for every six pulses of the VTR internal oscillation signal as an input of the VTR internal oscillation signal. Generates a reset signal for providing a first reset signal and a second reset signal to the hex counter 104 and the octal counter 100 by inputting an octal counter 100, a horizontal synchronization signal, and a delay signal, respectively. Section 106, and a delay for generating the delay signal.

It is comprised by the signal generation part 102. FIG.

2 is a detailed circuit diagram of the present invention. A detailed circuit configuration of the schematic configuration of FIG. 1 will be described with reference to FIG. 2 as follows.

First, the circuit configuration of the hex counter 104 will be described.

The hex counter 104 outputs one pulse for every six pulses of the VTR internal oscillation signal as the input of the VTR internal oscillation signal.

The VTR internal oscillation signal passes through the inverter IN1 and the inverter IN2 and then clocks the D-flop flop F8, the D-flop flop F9, and the D-flop flop F10 (hereinafter referred to as CLK). Are each entered.

The first reset signal is input to a reset terminal (hereinafter referred to as R) of the D-flip flop F8, the D-flip flop F9, and the D-flip flop F10, respectively.

An output terminal (hereinafter referred to as Q) of the D-flop flop F8 is connected to an input terminal (hereinafter referred to as D) of the D-flop flop F9, and an output supporting means of the D-flop flop F9 ( GB) is connected to D of the D flip-flop F10. In addition, Q of the D-flip flop F10 is connected to D of the D-flip flop F8.

Q of the D-flip flop F9 outputs a signal in which the VTR internal oscillation signal is hex counted through the inverter IN3 and the inverter IN4.

Next, a circuit configuration of the octal counter 100 will be described.

The output signal of the hex counter 104 is input to the CLKs of the D-flip flop F1, the D-flip flop F2, the D-flip flop F3, and the D-flip flop F4, respectively.

The second reset signal is input to R of the D-flip flop F1, the D-flip flop F2, the D-flip flop F3, and the D-flip flop F4, respectively.

The GB of the D-flop flop F1 is connected to D of the D-flop flop F4, and the Q of the D-flop flop F4 is connected to D of the D-flop flop F3. In addition, Q of the D-flop flop F3 is connected to D of the D-flop flop F2, and Q of the D-flop flop F2 is connected to Q of the D-flop flop F1. do.

If the signal from Q of the D-flop flop F1 is called a first output signal, and the signal from GB of the D-flop flop F3 is passed through the inverter IN10 as a second output signal, The negative logic gate NAND1 outputs a burst gate pulse by inputting the first output signal and the second output signal.

Further, the first output signal and the signal from GB of the D-flip flop F1 are input to the delay signal generator 102, and the signal from Q of the D-flip flop F3 is converted to an inverter ( The reset signal generator 106 is input to the reset signal generator 106 via IN5 and the inverter IN6.

The hex counter 104 and octal counter 100 constitute a burst gate pulse generator.

Accordingly, the operation of the burst gate pulse generator will be described with reference to FIG. 3A, which shows a timing diagram for explaining the operation of the burst gate pulse generator.

In general, the VTR internal oscillation signal uses a 5.04 MHz signal of a voltage controlled oscillator (hereinafter referred to as VCO). Thus, as shown in the first timing diagram of FIG. 3A, the period of the VTR internal oscillation signal is about 0.2 ms (micro-secind), which is an inverse of 5.04 MHz.

In addition, the width of the low level pulse of the horizontal synchronization signal is about 4.8 kHz.

Accordingly, it can be seen that the low level pulse of the horizontal synchronization signal is generated during the four pulse periods of the signal output through the inverter IN4 by counting the internal oscillation signal of the VTR.

The signal output through the inverter IN4 passes through the D-flip flop F4, and octal counts the output signal of the inverter IN4 from 1.2 ㎲ through Q of the D-flip flop F4. A pulse of 9.6 ms is generated.

The signal output through Q of the D-flop flop F4 is output by the signal delayed by 1.2 Hz through the Q of the D-flop flop F3 via the D-flop flop F3, and the D- The signal output through Q of the flip-flop F3 is output by the signal delayed by 1.2 dB through the Q of the D-flip flop F2 via the D-flip flop F2.

In addition, the signal output through Q of the D-flip flop F2 is output by the signal delayed by 1.2 dB through the Q of the D-flip flop F1 via the D-flip flop F1. In this case, a signal in which the first output signal, which is an output signal from Q of the D-flip flop F1, and the output signal from QB of the D-flip flop F3, are inverted through the inverter IN10, that is, the The burst gate pulse can be obtained by inputting the second output signal, which is the signal from Q of the D-flip flop F3, to the negative logic gate NAND1.

Next, a circuit configuration of the delay signal generator 102 will be described.

The delay signal generating unit 102 inputs the internal oscillation signal of the VTR, the first output signal, and the inverted signal of the first output signal as inputs, and generates 0.4 at a falling edge of the high level pulse of the first output signal. The delay signal, which is a low level pulse having a width of, is output.

The VTR internal oscillation signal is input to CLK of T-flip flop F5, and the signal from Q of T-flip flop F5 is input to CLK of T-flip flop F6. Further, the signal from QB of the T-flip flop F6 is input to the CLK of the D-flip flop F7.

The first output signal is input to D of the D flip-flop F7. The negative logic gate NAND2 receives the signal from Q of the D-flop flop F7 and the signal from QB of the D-flop flop F1, that is, the inverted signal of the first output signal. Output the delay signal.

Thus, the operation of the delay signal generator 102 will be described with reference to FIG. 3B, which is a timing diagram for explaining the operation of the delay signal generator 102.

The QB of the T-flip flop F6 outputs a signal obtained by quaternary counting the VTR internal oscillation signal, that is, a signal having a period of 0.8 ms.

The first output at the falling edge of the signal from QB of the D-flop F7 by inputting the output signal from QB of the T-flop F6 into the CLK of the D-flop flop F7 The state of the signal is output through Q of the D-flip-flop F7.

In this case, the negative logic gate NAND2 outputs the delay signal by inputting the signal from Q of the D-flip flop F7 and the inverted signal of the first output signal.

Finally, a circuit configuration of the reset signal generator 106 will be described.

The reset signal generating unit 106 receives the delay signal, the horizontal synchronization signal, and the signal from Q of the D-flip F3 output through the inverter IN6 as the input and the first reset signal. The second reset signal is output.

The horizontal synchronization signal and the delay signal are respectively input to the negative logical gate NAND3 and the negative logical gate NAND4, and the signals of the output terminals of the negative logical gate NAND4 and the negative logical gate NAND3 are respectively input. The negative logic gate NAND3 and the negative logic gate NAND4 are fed back to each other.

The negative logic gate NAND5 receives an inverted signal of a signal output through the inverter IN6 and a signal of an output terminal of the negative logic gate NAND3.

The negative logic gate NAND6 outputs the second reset signal by inputting the delay signal and the signal of the output terminal of the negative logic gate NAND5.

The signal at the output terminal of the negative logic gate NAND4 becomes the first reset signal through the inverter IN8 and the inverter IN9.

The operation of the reset signal generator 106 will now be described with reference to FIG. 3C, which shows a timing diagram for explaining the operation of the reset signal generator 106.

Since the negative logic gate NAND3 and the negative logic gate NAND4 constitute an RS-latch, a signal of an output terminal of the negative logic gate NAND3 has a logic state of the delay signal and the horizontal synchronization signal. When they are not equal to each other, a signal that is a logic state of the delay signal is output. When the logic states of the delay signal and the horizontal synchronization signal are both at a high level, the previous state is maintained.

Therefore, the signal at the output terminal of the negative logic gate NAND3 becomes low level from when the delay signal becomes low level until the next low level pulse of the horizontal synchronization signal occurs, and otherwise, always maintains the high level. do.

The signal of the output terminal of the negative logic gate NAND4 is an inverted signal of the signal of the output terminal of the negative logic gate NAND3, which becomes the first reset signal.

The signal of the output terminal of the negative logic gate NAND5 is high whenever the operation of the octal counter 100 and the delay signal generator 102 proceeds normally. Since the level is maintained, the signal of the output terminal of the negative logic gate NAND6, that is, the second reset signal, is output as an inverted signal of the delay signal.

As described above, in the present invention, the burst gate pulse generation circuit is composed of a logic circuit in a VTR system that does not use a feedback pulse (FBP). It is possible to prevent a problem that is difficult to induce cost savings, and also has the advantage of enabling compact integration by simplifying the circuit.

Claims (6)

A burst gate pulse generation circuit having a horizontal synchronization signal and a reference clock as an input, wherein the reference clock is input to generate a pulse during a back porch section in which a burst signal exists among elements constituting a composite video signal. A burst gate pulse generator for generating a burst gate pulse having a predetermined width during the back porch period by counting a clock; A reset signal generator for providing a reset signal to the burst gate pulse generator by latching the horizontal sync signal and the delay signal by inputting the horizontal sync signal and a predetermined delay signal; And a delay signal generator for outputting a delay signal by delaying the first output signal by a predetermined time by inputting a predetermined first output signal from the reference clock and the burst gate pulse generator. Burst gate pulse generator circuit. The first pulse of claim 1, wherein the burst gate pulse generator generates a first pulse having a width obtained by dividing a width of a low level pulse of the horizontal synchronization signal by four by counting a pulse of the reference clock with the reference clock as an input. First pulse generating means for generating; By counting the first pulse with the first pulse as an input, a second pulse is generated which is twice the width of the low level pulse of the horizontal synchronization signal, and the high level pulse of the second pulse is the horizontal synchronization signal. The first output signal and the high level pulse of the second pulse delayed by four times the period of the first pulse from the falling edge of the low level pulse of the first pulse from the falling edge of the low level pulse of the horizontal synchronization signal. Second pulse generating means for providing a second output signal delayed by twice the period of? And a logic comparing means for logically comparing the first output signal and the second output signal to output the burst gate pulse by inputting the first output signal and the second output signal. Pulse generator circuit. 3. The method of claim 2, wherein the first pulse generating means is a first counting means for counting the reference clock as a clock signal and the first reset signal as a reset signal to have a period of the first pulse. Burst gate pulse generator circuit. The method of claim 2, wherein the second pulse generating means is a second counting means for counting the first pulse as a clock signal and the second reset signal as a reset signal to have a period of the second pulse. A burst gate pulse generator circuit. The method of claim 1, wherein the reset signal generation unit receives the horizontal synchronization signal and the delay signal as inputs and latches the horizontal synchronization signal and the delay signal until the falling edge of the delay signal is generated from the falling edge of the horizontal synchronization signal. Latch means for generating a latch signal for indicating a; And a comparison signal for generating a comparison signal for negative logic multiplication with the delay signal in order to generate the second reset signal by performing a negative logic on the latch signal and the second output signal by inputting the latch signal and the second output signal. A burst gate pulse generating circuit comprising a generating means. 2. The apparatus of claim 1, wherein the delay signal generator comprises: delay signal clock generation means for generating a delay signal generation clock that is four times the reference clock pulse width by counting the reference clock as the reference clock; Delay means for delaying the first output signal by half of the delayed signal generation clock period and outputting the delayed signal generation clock as a clock signal; And a negative logic to generate the delayed signal by inputting an output signal of the delay means and an inverted signal of the first output signal as negative inputs of the output signal of the delay means and the inverted signal of the first output signal. A burst gate pulse generator circuit comprising a gate.