KR950007532B1 - Figure processing system and figure processing method - Google Patents

Abstract

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Description

Figure processing system and figure processing method

1 is a block diagram showing the outline of the present invention.

2 is a block diagram of a graphics processing apparatus according to the present invention.

3 is a diagram showing an example in the case where one pixel is displayed in four bits.

FIG. 4 is a diagram showing an example of the specific configuration of the logic address calculation unit in FIG.

FIG. 5 is a diagram showing a specific configuration example of the physical address computation unit in FIG. 2; FIG.

FIG. 6 is a diagram showing an example of the specific configuration of the color data calculation unit in FIG.

7 is a functional explanatory diagram of each field of a microinstruction.

Fig. 8 shows the bit structure of the display memory in each mode.

FIG. 9 is an explanatory diagram of pixel addresses corresponding to FIG. 8; FIG.

10 is an explanatory diagram of a spatial arrangement of the display memory in the 4-bit / pixel mode.

FIG. 11 is a diagram schematically showing a flow of drawing operations of one pixel (4 bits / pixel). FIG.

FIG. 12 is a diagram illustrating components in the case of converting to a physical address corresponding to a logical address in FIGS. 4 and 5, and adding some additional functions.

13 is an explanatory diagram showing the relationship between a physical address, a logical address space, and a display screen in a certain mode (4 bits / pixel).

14 (a) to 14 (c) are operation explanatory diagrams related to FIG.

FIG. 15 is a diagram showing correspondence between a bit mode and a bit address indicating a pixel position in one word corresponding thereto. FIG.

16A to 16D are explanatory diagrams showing the relationship between mask data and bit addresses.

FIG. 17A is a diagram showing a basic computing process in address conversion; and (b) is a diagram showing a bit address offset value.

18 is a diagram showing an example of linear drawing in the case of using the present invention.

FIG. 19 is a diagram showing an example of application of the transfer of pixel information, for convenience, omission of the process of FIGS.

20 (a) and 20 (b) are explanatory diagrams of the operation of FIG.

21 is a diagram showing an example of transmission of one pixel data.

Fig. 22 is a diagram schematically showing the flow of the transfer process.

Fig. 23 is a diagram showing a pointer movement direction of transmission in quadrangular area designation.

FIG. 24 is a configuration of arithmetic control of the pixel position, showing only those related to FIG. 4 to FIG.

25 (a) to 25 (e) show the format of a transmission (copy) command.

Fig. 26 is a conceptual diagram of its operation.

27A is a diagram showing the structure of a code register, and (b) and (c) are examples of the format of a pattern command.

28 is a processing flow diagram of a kopi command.

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a raster scanning type CRT (cathod ray tube) display device and the like, which includes a microprocessor for inputting / outputting data, collecting data, and displaying graphics, and is stored in a microprogram memory. A figure processing system and a figure processing method are provided which have a drawing function which performs control by a micro program.

Most of the conventional CRT controllers are dedicated to display control and do not have a drawing function. For example, US Pat. No. 4,149,264. In addition, even if there is an image processing apparatus in which the graphic processing function is realized with an integrated circuit, it is only processing the graphic display data of a single color displaying one pixel with one bit. However, with the advancement of information processing, many cases of multicolor or multi-gradation image processing are performed, and the processing speed at that time becomes a problem. For example, in the case of multi-color (n-color) or multi-gradation (n-gradation) processing, when rewriting the stored contents, the same image processing is repeated n times or n times in order to display one pixel of one bit. Image processing was necessary.

Therefore, there is a problem that the processing time of n times is required for the binary image processing. Although a method of processing with one processing unit for each of the n display memories is considered, there has been a problem that the apparatus becomes larger and more complicated and the load on the central processing unit increases.

In addition, a case may be considered in which an operation process is executed by drawing a straight line in the XY coordinate space with any one point as the origin. Assume the case of connecting a straight line between any two points Ps (Xs, Ys) and P _E (X _E , Y _E ). In this case, the inclination of the straight line is calculated from the coordinate values of these two points, and the coordinate values of the points on the straight line are calculated to create figure data for each point, and then write. Such processing is performed sequentially for all the points existing on the straight line. However, the calculated coordinate values are completely independent of the memory address of the display memory into which the figure data is written. Need to be converted to display memory address

However, since one word of the display memory contains single or plural pixel data, the calculated logical address is divided into two physical addresses in the form of a memory address of the display memory or a bit address indicating the pixel position. Will be converted.

To convert from a logical address to a physical address, it is necessary to know the physical address corresponding to the origin and the size of the horizontal direction of the screen memory. That is, since the logical address is information indicating the relative position from the origin, when the logical address is (X, Y), the horizontal direction of the screen memory is multiplied by Y in the vertical direction (Y direction), and the horizontal direction (X Direction), the target memory address can be calculated by adding and subtracting a value obtained by dividing the value of X by the number of pixels included in one word to the physical address corresponding to the origin. Further, by setting the remainder obtained by dividing the value of X by the number of pixels included in one word as a bit address, a physical address for processing figure data is obtained.

However, until now, the calculation of the logical address and the conversion to the physical address have been entirely performed by software program processing. Therefore, when a general-purpose microprocessor is used, one pixel data is stored in the display memory. It is a fact that the process was not able to be speeded up by several hours by several tens of microsec.

Moreover, in the figure processing system for creating figure display data, transfer processing of figure display data is performed in the display memory, but the processing speed has been a problem.

For example, there is a case where one pixel data is to be transferred to another pixel position. In general, one word of the memory stores data of a plurality of pixels that are continuous in the horizontal direction. Therefore, in the case of transferring certain pixel data to another pixel position, a shift process or an extraction process of the source pixel data is required to make the bit positions of the operation uniform. Conventionally, this transfer process is performed by software. For example, in the case of the process of transferring data of a quadrangular area, a process of moving a pointer specifying a source pixel and a destination pixel, counting the transfer frequency, and the like. Is added. As a result, when a general-purpose microprocessor is used, several microseconds to tens of microseconds of transfer processing per pixel are required, and therefore, the speed of the processing is a problem.

SUMMARY OF THE INVENTION The present invention provides a figure processing system and figure processing method for realizing the above-described high speed processing such as rewriting, drawing, and transferring pixel data in multi-color and multi-gradation.

In addition, related examples of this type of graphic processing system include GB2087696A.

An object of the present invention is to provide a figure processing system and a figure processing method capable of drawing at substantially the same processing speed as in the case of a binary image even in the case of multi-color or multi-gradation in which one pixel is represented by a plurality of bits.

Another object of the present invention is to provide a graphics processing system and graphics processing method which can calculate display memory at high speed from logical coordinate values of an image.

According to the present invention, there is provided an output device for outputting graphic data, the display device being connected to the output device, one pixel data comprising a plurality of bits, and holding the graphic data constituting one word with a plurality of the pixel data. A graphics processing apparatus for reading graphic data of one word designated by a memory and a read address, specifying predetermined pixel data in the read one word graphic data, and writing the specified pixel data in accordance with a write address. It provides a figure processing system having a.

Further, according to the present invention, one pixel data is composed of a plurality of bits, and a processing is performed by accessing a display memory for holding graphic data constituting one word with a plurality of pixel data, and processing the graphic data to an output device. For outputting, reading out one word of graphic data specified by the read address, specifying predetermined pixel data in the read one word of graphic data, and writing the specified pixel data according to the writing address. There is provided a figure processing method having a step of writing.

Next, embodiments of the present invention will be described in detail with reference to the drawings.

1 is a block diagram showing the overall configuration of a graphics processing system according to the present invention, and a block diagram showing an example of a system to which the graphics processing system according to the present invention is applied.

In FIG. 1, the figure processing apparatus includes an arithmetic unit 30 which writes, rewrites and reads and controls the display data in the display memory 13, and a control unit which controls the arithmetic unit 30 in a certain order. It consists of 20. In addition, the display data read out from the display memory 13 by the graphics processing device is displayed on the display device 50 as a video signal by the display conversion device 40. The display conversion device 40 and the display device 50 constitute an output device.

The arithmetic unit 30 controlled by the control unit 20 sequentially performs a pixel address consisting of an address of the display memory 13 and information specifying a pixel position in the display data of one word in the display memory 13. Calculates and reads one word of display data in the display data 13 from the address information of the display data 13 in the calculated pixel address. The display data read in this manner is read into the pixel address. The result of performing such a logical operation having information for designating a plurality of bit positions corresponding to the designated pixel positions formed by decoding the pixel position designation information in the symbol, and drawing only the bits of the predetermined pixel of the display data. To the display memory 13 again.

Numeral 60 denotes an external calculator, in which the graphics processing apparatus operates in accordance with control data CDT such as commands and parameters transmitted from the external calculator 60.

2 is a block diagram showing an embodiment of a figure processing apparatus according to the present invention.

In FIG. 2, the control device 20 includes a micro program memory 100, a micro program address register 110, a return address register 120, a micro command register 130, and a micro command decoder 200. ), A flag register 210, a pattern memory (RAM) 220, and a command control register 230.

In addition, the arithmetic unit 30 is composed of an arithmetic control unit 300 and a FIFO (First-In, First-Out) memory 400. The operation control device 300 is composed of a logical address operation unit (A unit) 310, a physical address operation unit (B unit) 320, and a color data operation unit (C unit) 330.

In the A unit 310, the drawing point is mainly calculated according to the drawing algorithm, and in the B unit 320, the necessary address of the display memory is calculated, and the C unit 330 writes in the display data. To calculate the color data.

FIG. 3 shows a configuration of a display device for displaying one pixel with four bits, and display data designated by the graphic processing device in FIG. 2 is displayed on the display device 50. As shown in FIG.

In FIG. 3, D ₀ , D ₄ , D ₈ , and D ₁₂ of the display data DT read out from the display data 13 according to the address AD instruction from the figure processing apparatus (FIG. 2) are the display conversion apparatus. Supplied to a 4-bit parallel-to-serial converter 410 in 40. The video signal VD ₀ is obtained from this parallel-to-serial converter 410. Similarly, D ₁ , D ₅ , D ₉ , and D ₁₃ in the display data DT are supplied to the parallel-to-serial converter 420 in the display change device 40, and the video signal VD ₁ from this parallel-to-serial converter 420 is provided. Is obtained. D ₂ , D ₆ , D ₁₀ , and D ₁₄ in the display data DT are supplied to the parallel-to-serial converter 430 in the display converter 40, and the video signal VD ₂ is obtained from the parallel-to-serial converter 430. Lose. In addition, D ₃ , D ₇ , D ₁₁ , and D ₁₅ in the display data DT are supplied to the parallel-to-serial converter 440 in the display converter 40, and the video signal VD ₃ is received from the parallel-to-serial converter 440. Is obtained. The video signals VD _{0 to} VD ₃ are sent to the video interface circuit 450 and displayed on the display device 50 after processing such as color conversion or DA conversion.

Next, a specific configuration of each unit of the arithmetic and control device 300 will be described.

4 is a detailed view of the logical address operation unit 310, which is an A unit, and includes a FIFO buffer (FBUF) 3101 and a general register group (TROX, TROY, TR1X, TR1Y, TR2X, TR2Y, CPX, CPY) (3102). Area management registers (XMIN, YMIN) (3103) and (XMAX, YMAX) (3105), area judgment comparator (ACMP) 3104, endpoint registers (XEND, YEND) (3106), end judgment comparator (ECMP) 3107, source latches (SFTA, SLAV) 3108 and (SLAU) 3109, Sansol logic operator (ALU) 3110, destination latch (DLA) 3111, bus A switch 3112, read buses UBA and VBA 3113 and 3114, and a write bus WBA 3115 are provided.

5 is a detailed view of the physical address operation unit 320 that is a B unit, and includes a destination latch (DLB, SFTB) 3201, an arithmetic operator (AU) 3202, and a source latch (SLBV) 3203. (SLBU) 3204, Offset Register (OFS) 3205, Screen Width Register (MW) 3206, Command Register (CR) 3207, and General Purpose Register Groups (DPH, DPL, RWPH). RWPL, T2H, and T2L (3208), read bus (UBB) 3209, and write bus (WBB) 3210 are provided. The general register group 3208 includes current address registers DPH and DPL of pixel unit commands, address registers RWPH and RWPL of word unit commands, and working registers T2H and T2L.

6 is a detailed view of the color data calculation unit 330 which is a C unit. The C unit includes a shift shifter barrel shifter (BRLS) 3301, a color register (CL0, CL1, EC, EDG) 3302, a mask register (CMSK, GMSK) 3303, and a color comparator (CLOMP) ( 3304, logical operator (LU) 3305, write data buffer (WDBR) 3306, pattern RAM buffer (PBUF) 3307, pattern counter (PCNT) 3308, and pattern control register ( PP, PS, PE) 3309, read data buffer (RDBR) 3310, memory address registers (MARL, MARH) 3311, memory output bus 3312, memory input bus 3313, And an input / output buffer circuit 3400. In addition, the mask register 3303 is composed of a register CMSK and a register GMSK.

Next, the operation of the embodiment configured as described above will be described. First, the basic operation of each element will be described.

The display control data CDT shown in FIG. 1, FIG. 2, etc., is a parallel or parameter sent from another apparatus such as a central processing unit, and is written to the memory (FIFO) 400 on one side and to the command control register 230 on the one side. Is written.

The command control register 230 stores various graphic bit modes, and according to this embodiment, one of five pixel modes can be selected as described later. This selection can be made by use data CDT.

The memory 400 is a so-called "First-In, First-Out" (FIFO) memory, which reads the instructions stored in the FIFO memory 400 by the operation control device 300, and the operation control device 300 ) Is stored in a FIFO buffer (FBUF) 3101, which is a register within the block. In addition. Some CIDs of this command information are transmitted to the microprogram address register 110.

The microprogram address register 110 manages an address of the microprogram memory 100, which is updated in synchronization with a clock. Microinstructions as shown in FIG. 7 are read out from the microprogram memory 100 in accordance with the address output from the microprogram address register 110. The command read out from the microprogram memory 100 is made up of 48 bits as shown in FIG. 7, and a control mode such as # 0 to # 7 can be selected. The flash is temporarily stored in the microcommand register 130, and generates a predetermined control signal CCS through the microcommand decoder 200 operating in accordance with the selected mode of the command control register 230 to generate the operation control device ( Control each part of 300). Here, the function of each field of the microinstruction in FIG. 7 will be described.

In FIG. 7, [RU] is an instruction to designate a register connected to the read bus (UBA) 3113. In FIG. [RV] is an instruction to designate a register connected to the read bus (VBA) 3114. [RW] is an instruction to designate a register into which data on the write bus (WBA) 3115 is written. [FUNCA] is an instruction to specify the operation of the arithmetic logic operator 3110 of the A unit. [SFT] is an instruction to specify the shift mode of the shifter SFTA added to the source latch 3108. [ADF-L] is an instruction to designate the lower 4 bits of the next address returned to the microprogram address register 110. [AC] is a command for controlling the next address of the micro instruction. [ADF-H] is a command for specifying the upper 6 bits of the next address returned to the microprogram address register 110. In addition, in each micro instruction of # 4 to # 7, the upper 6 bits of the address cannot be updated. [FUNCB] is an instruction to specify the operation mode of the arithmetic operator 3202 of the B unit. [ECD] is an instruction to specify the execution condition of the operation. [BCD] is an instruction to specify the condition of a branch. [FLAG] is a command for specifying reflection of the flag on the flag register 210. [V] is a command to specify whether or not to test whether access to the display memory 13 is tested. [FIFO] is a command to control reading and writing to the FIFO memory 400. [LITERAL] is an instruction to specify literal data of 8 bits. [LC] is a command to specify the generation mode of literal data. [FF] is a command to control the set and reset of each special flip-flop. [S] is a command for specifying the code flag selection.

[MC] is a command to control reading and writing of the display memory 13. [DR] is a command to control the scanning of the pattern RAM. [BC] is an instruction to control the input path to the arithmetic operator 3202 of the B unit. [RB] is a command for selecting the read and write registers of the B unit.

The microinstruction has the above-described instructions, whereby the control device 20 controls the computing device 30.

The return address register 120 also stores the return address of the subroutine. The flag register 210 stores various condition flags. The pattern memory 220 stores a basic pattern used for figure processing.

Next, the bit layout of each data used in the present embodiment will be described.

First, the graphic mode will be described.

In this embodiment, five different operation modes can be selected in accordance with the designation of the graphic bit mode GBM stored in the command control register 230.

8A to 8E show the bit structure of one word of the display memory in each mode.

(a) 1 bit / pixel mode (GBM = 000)

This mode is used for displaying one pixel with one bit, such as a black and white image. One word of the display memory 13 stores 16 consecutive pixels of data.

(b) 2 bit / pixel mode (GBM = 001)

This represents one pixel with two bits. It can be used to display up to four colors or up to four gradations. Therefore, one pixel of the display memory 13 stores eight consecutive pixels of data.

(c) 4 bit / pixel mode (GBM = 010)

This represents one pixel with four bits. Consecutive four-pixel data is stored in one word of data of the display memory 13.

d) 8 bit / pixel mode (GBM = 011)

This represents one pixel in eight bits. Two words of data are stored in one word of the display memory 13.

(e) 16 bit / pixel mode (GBM = 100)

This represents one pixel with 16 bits. One word of the display memory 13 corresponds to one pixel data.

Formula 8 (f) shows an example of the command control register 230.

Next, the pixel address will be described.

9 illustrates the pixel address corresponding to each mode of FIG. In the general register group 3208 of the physical address calculation unit, a bit address (material address) WAD having 4 bits added to the lower part of the memory address is managed. The lower four bits of information WAD are used to specify the pixel position in one word, and operate in accordance with each bit / pixel mode.

In the figure, a "*" mark indicates a bit unrelated to an operation.

Fig. 10 shows the spatial arrangement of the display memory 13 by taking [4 bit / pixel mode] of the above (c) as an example. The memory address is assigned as a linear address as shown in the memory map of FIG. 10 (a), and this is displayed as a two-dimensional image as shown in FIG. 10 (b). The horizontal axis of the screen is stored in the screen width register (MW) 3206 of FIG. 5, and this MW indicates how many bits the horizontal axis of the screen is composed of. Therefore, in the 4-bit / pixel mode, the horizontal direction The pixel is displayed. In addition, since one pixel is displayed in four bits, data of one word is displayed as data of four pixels continuous in the horizontal direction as shown in Fig. 10C. In the offset generating circuit 2001 of FIG. 5, "4" is generated as an offset value and stored in the offset register 3205. FIG. Therefore, it can be seen that the offset value may be added or subtracted to move the physical address by one pixel in the vertical direction. In order to move one pixel in the vertical direction, the value of the screen width register (MW) 3206 may be added or subtracted. The above is the layout of the bits of data used in the present embodiment.

Next, an operation of storing image data in the display memory 13 by using the data will be described.

Control data CDTs such as commands and parameters sent from an external central processing unit are written to the FIFO memory 400 on one side and to the command control register 230 on the other side.

Here, an example in which the graphic bit mode GBM stored in the command control register 230 and designated is the 4-bit / 1 pixel mode (GBM = 010) will be described.

When the graphic bit mode (GBM) is designated as 4 bits / 1 pixel by the command control register 230, data of one word in the subsequent display memory 13 is 4 bits as shown in Fig. 8C. It is treated as divided each time.

Signals CDT such as commands and parameters from an external central processing unit are sequentially stored in the FIFO memory 400. The data stored in this FIFO memory 400 is taken into the FIFO buffer 3101 of the A unit 310. The data taken into the FIFO buffer 3101 are mutually transmitted and received between the read bus 3113 and stored in respective necessary registers. It is input from the bus to the arithmetic logic operator (ALU) 3110 via a source latch (SLAU) 3109 to perform a predetermined operation and the result is stored in a temporary destination latch (DLA) 3111. This result is stored in the general register group 3102 via the write bus (WBA) 3115. The general register group 3102 stores the current coordinate point in the coordinate space of the parameter.

The current X-Y coordinates in general register group 3102 are read out via either of read buses 3113 and 3114, which are input to an arithmetic logic operator (ALU) 3110. The result calculated by this arithmetic logic operator (ALU) 3110 is stored in the general purpose register group 3102 again through the destination latch (DLA) 3111 and the write bus 3115. These series of operations are executed in accordance with the instructions of the microprogram shown in FIG.

The data on the write bus 3115 are input to the area management registers 3103 and 3105, and are compared in the area determination comparator 3104. From these data, the area judgment comparator 3104 determines whether the minimum value of the X axis or the maximum value of the X axis, the minimum value of the Y axis, or the maximum value of the Y axis is determined, and the result of the determination is sent to the flag register 210.

The data of the write bus 3115 is stored in the end point register 3106 and input to the end decision comparator 3107 through this. The end decision comparator 3107 compares the end points of the X-axis and the Y-axis stored in the end decision comparator 3107 with the data in advance, and detects whether the end point and the data coincide. The comparison detection result is reflected in the flag register 210.

As described above, the results of the area decision comparator 3104, the end decision comparator 3107, and the arithmetic logic operator 3110 are gathered in the flag register 210 and input to the micro instruction decoder 200, so as to flow the microprogram. It will be used to convert.

As described above, the A unit 310 operates to decode the X-Y coordinate values given by the parameters, and for example, to interpret a command such as drawing a line or drawing a circle, respectively.

Next, the operation of the B unit 320 will be described with reference to FIG.

The display control data is input to the general register group 3206 through the read bus (UBB) 3209, the arithmetic operator (AU) 3202, the destination latch (DLB) 3201, and the write bus (WBB) 3210. Initial setting. Data of the general register group 3208 is input to the calculation operator (AU) 3202 through the read bus 3209 and the source latch 3204. The result calculated by the arithmetic operator 3202 is temporarily stored in the destination latch 3201, and is output to the buses 311, 3114, 3209 and 3210. Here, the data is written to the general register group 3208 via the write bus 3210. This general register group 3208 has two 16-bit one-word words in one word configuration, and stores physical addresses in 32-bit one words in total. This general-purpose register group 3208 has three types of registers of 32 bits, and can store three types of data. That is, the registers DP (DPL, DPH) of this general purpose register group 3208 store the physical address of the actual drawing point corresponding to the current drawing point X-Y. Accordingly, when the XY coordinates of the general register group 3102 of the A unit 310 move, the physical address of the register DP moves correspondingly.

The physical address can be changed by adding or subtracting a predetermined value (value up to the point to be moved to the offset value X) to the original physical address in the X-axis direction. You can add or subtract. That is, in accordance with the image mode designated by the offset generation circuit 2001, the offset register 3205 is set with a constant when the pixel address is moved by one pixel in the horizontal direction. By calculating this constant and the data with the arithmetic operator 3202, the horizontal moving address is calculated. For example, when the pixel mode is [1 bit / pixel mode], the constant is 1, and shifting 1 pixel only shifts 1 bit. When this is [4 bit / pixel mode], the constant becomes 4, and shifting 1 pixel shifts 4 bits.

In addition, in order to move by one pixel vertically here, it is possible to move by one pixel by performing calculation using a constant set in the screen width register 3206.

As described above, the B unit 320 operates to obtain an actual physical address corresponding to the X-Y coordinate determined by the A unit 310.

Next, the operation of the C unit 330 will be described with reference to FIG.

The C unit 330 is connected to the display memory 13 shown in FIG. 10 by a memory output bus 3312 and a memory input bus 3313. The address information AD is first output to the memory output bus 3312 from the C unit 330, and then the data DT is output.

First, the address information AD is written to the memory address register 3311 via the read unit (UBB) 3209 via the B unit 320 and stored in MARL and MARH of the memory address register 3311. When the memory address stored in the memory address register 3311 is sent to the display memory 13 via the memory output bus 3312, the display memory from the display memory 13 via the memory input bus 3313 The display memory DT of the designated one word of (13) is read. The read display data DT is stored in the read data buffer 3310. Here, when the display data DT draws a figure, it is input to the logical operator 3305.

Next, mask information (information specifying which bit in one word is used as a mask) from the mask register 3303 is input to the logic operator 3305. The mask information can be stored in the register (CMSK) directly written from the write bus (WBB) 3210 or from the register (GMSK) for storing data generated by the address decoder 2002 in one word. Is sent out.

Color information is also selected by the color register 3302 and given to the logical operator (LU) 3305. The logical operator 3305 performs a logical operation according to the data DT, mask information, and color information, and outputs the result of the calculation to the write data buffer (WDBR) 3306. Further, the color information and the pattern information are specified by address signals formed in the pattern counter (PCNT) 3308 and the pattern control registers (PP, PS, PE) 3309, whereby the pattern memory (RAM) 220 from the pattern RAM It is stored in the buffer (PBUF) 3307.

In this way, the C unit 330 operates to convert the color information.

Next, the method of drawing operation is demonstrated. Fig. 11 schematically shows the flow of drawing operation of one pixel in the case of 4 bit / pixel mode.

Data read from the pattern memory 220 by the addresses specified in the pattern control registers (PP, PS, PE) 3309 and the pattern counter (PCNT) 3308 is transferred through the pattern RAM buffer 3307 through the color register 3302. Are stored in CL0 and CL1. The data C _a , C _b , C _c , and C _d read out from the display memory 13 are stored in the read data buffer 3310. In this example, the color data, the read data, and the like are 4-bit color information or gradation information, respectively.

Pattern data of one bit is read from the pattern memory 220, and color register 0 (CL0) or color register 1 (CL1) in accordance with "0" and "1" (X = 1 or X = 0) of the data. ) Is selected and supplied to the logic operator 3305.

The lower 4 bits of the physical address information stored in the memory address register 3311 are " 10 ** " in the drawing. This information is mask information GMSK in the mask register 3303 through the address decoder 2002 in one word. Occurs. On the other hand, the upper field except the lower 4 bits of the memory address register 331 is output as the display memory address so that one word of the display memory 13 is read. The logical operator 3305 performs logical operation only on the portion designated by the bit of "1" of the GMSK of the mask register 3303 to obtain the write data C _y and store it in the write data buffer 3306. Here, the types of logical operations of the calculator 3305 include rewriting the values of the color register, logical operations (AND, OR, NOR), conditional drawing (only when the read color satisfies a predetermined condition), and the like. . In the case where the bit / pixel mode is different, the GMSK information generated is different and the same operation is performed. In this manner, the memory information bus 3312 is sent out from the meridian address register 3311 and the write data buffer 3306 in the order of the address information AD and the data DT, and is then transferred to the predetermined address of the display memory 13. Is written.

As described above, according to the present embodiment, since one pixel of data can be updated at one time by one read, update, and write process, drawing with good processing efficiency is made possible. Also, in a case other than the 16-bit / pixel mode, since the data of a plurality of pixels are arranged in a 16-bit length and processed, the use efficiency of the memory is good, and the data transfer efficiency between the other device and the display memory is also good. In addition, in this embodiment, since the operation modes for five types having different bit lengths per pixel are set, the configuration is highly versatile.

Next, the figure processing which can calculate the physical address corresponding to a logical address at high speed is demonstrated by this invention. That is, the case where address conversion is performed at high speed using the A unit 310 and the B unit 320 in FIG. 2 will be described.

FIG. 12 shows those related to address translation and patented additions according to the configurations shown in FIG. 4 and FIG. The same thing as FIG. 4 and FIG. 5 uses the same code | symbol.

The arithmetic data selector 3500 is controlled by the CCS, selects one of the data from the screen width register (MW) 3206 and the data from the offset register (OFS) 3205, and the arithmetic operator (AU). It is supplied to 3320. The arithmetic operator 3202 calculates a physical address corresponding to the logical address.

Next, the physical address space, the logical address space corresponding thereto, and the display screen corresponding thereto will be described. FIG. 13 shows a physical address space in a mode in which one pixel is displayed in four bits, a logical address space corresponding thereto, or a display screen corresponding thereto. The relationship between the physical address as the size MW in the horizontal direction, the display memory in the logical address space, and the display screen is as shown. In the physical address space, four pixels are included in one word 16 bits (pixel data represented by four bits). In this case, one pixel is allocated to each memory plane for each color in the memory in the logical address space. It is synthesized so that one pixel displayed in 16 colors (or 16 gradations) is output on the screen. The data of four pixels in one word become pixel data continuous in the horizontal direction on the memory in the logical address space and on the display screen.

FIG. 14 shows the relationship between the physical address, the logical address, the memory width MW, and the pointer address PA shown in FIG. First, Fig. 14A shows the memory address MA and the bit address BA in the physical address space, and again shows the relationship between the display screen and the memory address MA. When the memory address of one word including a pixel vertically adjacent to one pixel in one word designated by the memory address MA1 is MA2, the memory width MW is as shown in Fig. 14C. Any point (x, y) on the screen shown in Fig. 14 (a) indicates that the pointer address is shown in Fig. 14 (b) when the corresponding physical address is the memory address MA and the bit address is indicated by BA. It is expressed as

Incidentally, the embodiment shown in FIG. 12 has a function that can efficiently process even when data of one pixel is represented by multiple bits (multicolor or multi-gradation), and the setting mode for the command control register 230 is shown. There are five different operation modes to choose from. This is by FIG. 8 above.

FIG. 15 shows the correspondence between the bit mode shown in FIG. 14 and the bit address indicating the pixel position in one word corresponding thereto. According to this, the bit address is made to coincide with the data start bit number of the pixel data. For example, in the 4-bit / pixel mode, when the bits 4 to 7 of the pixel data are calculated by the color data operation unit 330, the bit address of the lower 4 bits of the pointer address register of the general register group 3208 is [4]. ] Is stored.

16A to 16D show the relationship between the mask data stored in the mask register 3303 and the bit address in the case of the 4 bit / pixel mode. As described above, 4 is generated as a bit address when the bits 4 to 7 of the pixel data are calculated. In this case, the mask data is set to "1" corresponding to only the bit where the pixel data operation is performed. "0" is set to correspond to the bits that do not require operation. In other words. For example, when the bit address is "4", mask data in which only bits 4 to 7 are "1" is generated by the address decoder 2002 and stored in the mask register 3303.

FIG. 17A shows the basic arithmetic processing executed in the logical address computing unit and the physical address computing unit in the embodiment shown in FIG. 12, and FIG. 17B shows the bit address offset in each bit mode. The bit address offset value n generated by the generator is shown. From the bit address offset value, this is for bit address updating, and the data of "4" in the 4 bit / pixel mode is "1" in the 1 bit / pixel mode. The generated offset register 3205 is stored in the next offset register 3205 that is generated.

The processing shown in the seventeenth (a) will be described. This is a process in which the logical address at the point P that represents a certain pixel (X, Y) and the physical address are represented by PA are moved when the point P is moved by ± 1 in the logical address in the horizontal or vertical direction. It is shown. First, when the point P is set to ± 1 to draw pixel data in the X-axis (horizontal direction) forward direction, the data address X is read from the CPX of the current pointer in the general register group 3102 by the logical address operation unit 310. After that, +1 is added to the arithmetic logic operator 3110 through the source latch 3109. The calculation result (X + 1) is a new logical address X, which is stored again in the current register CP3 of the general-purpose register group 3102 through the day latch 3111. At the same time, the physical address calculation unit 320 reads the pointer address from the pointer address register of the general register group 3208 and gives it to the calculation operator 3202 through the source latch 3204 as operation data. On the other hand, the data from the offset register 3205 is selectively outputted from the arithmetic data selector 3500 and given to the arithmetic operator 3202 through the source latch 3203 as arithmetic data. Therefore, in the calculation operator 3202, addition is performed between the pointer address PA and the bit address offset value n. This addition result (PA + n) is again stored in DPL and DPH of the pointer address register of the general register group 3208 through the destination latch 3201 as a new pointer address. The address decoder 2002 which generates mask data after this storage generates mask data according to the lower 4 bits of data stored in the pointer address register of the general register group 3208, that is, the bit address and the bit mode, but the mask data is masked. It is sent to the logical operator 3305 through the register 3303, and is provided to the operation of the pixel data.

In addition, when the point P is moved by +1 in the positive direction of the Y direction (vertical direction), the logic address calculation unit 310 similarly performs a calculation to +1 the data of the current pointer Y (CPY of 3102). On the other hand, the physical address operation unit 320 simultaneously performs operations on the data of the DPL and DPH of the pointer address register of the general register group 3208.

In the calculation in the X direction, addition and subtraction are performed between the offset values and in the calculation in the Y direction, the addition and subtraction (in this case, subtraction) is performed between the data from the screen width register 3206. The operation control signal generator generates the addition and subtraction signals in the arithmetic operation unit 3202 in the physical address operation unit 320 when the addition and the calculation in the X direction are performed in the logical address operation unit 310, while the logical address operation unit 310 is generated. In the Y direction addition and subtraction, the arithmetic operation unit 3202 generates a subtraction and addition signal, but this is determined by the address assignment of the display memory corresponding to the display screen. By performing the above arithmetic processing, the physical address after the movement of the point P is derived. 18 shows an example of linear drawing according to the present invention.

When linear drawing is performed from the starting point p _s (x _s , y _s ) to the end point P _e (x _e , y _e ) of the linear drawing process, the physical address of the origin is first processed as the first preprocessing. The micropoint decoder is set to DPL and DPH of the pointer address register of the general-purpose register group 3208 from the device or another control device, and the current pointer X (CPX of 3102) and the current pointer Y (CPY of 3102) are control units. Cleared to "0" by the control from (200). By setting the origin, the correspondence between the logical address and the physical address is obtained. Next, as a second preprocess, the logical addresses (x _s , y _s ) of the starting point P _s of the straight line are stored in the current pointers X (CPX) and Y (CPY), respectively, but accordingly the physical address calculation unit 320 In the above, physical addresses corresponding to logical addresses (x _s and y _s ) are obtained. As the third preprocess, the logical addresses (x _e , y _e ) of the end point P _e are stored in the general-purpose register group 3102, whereby all preprocesses are finished. Then, the microinstruction decoder 200 serving as the control unit receives a command from the central processing unit or another control unit to draw a straight line from the point P _s to the point P _e , and starts the present process. The control command is output to each of the operation units 310, 320, and 33 in accordance with the control procedure. In the logical address calculation unit 310, intermediate information required for the drawing process such as the inclination of a straight line is obtained from the logical addresses (x _s , y _s ) of the starting point P _s and the logical addresses (x _e , y _e ) of the end point P _e . After being stored in the general-purpose register group 3102, the logical addresses (x ₁ , y ₁ ) of the next drawing point P ₁ and the physical addresses corresponding to the logical addresses (x ₁ , y ₁ ) are calculated according to these data. It is supposed to. The address operation in the X direction and the address operation in the Y direction in total two times are executed by the logical address operation unit 310 and the physical address operation unit 320.

In parallel with this, the pixel data corresponding to the starting point P _s is read from the display memory, and the pixel data of the ending point P _e is calculated. After the calculation of the pixel data is completed, the pixel data after the calculation is written back into the display memory. That is, while two memory accesses are executed for a certain point, in parallel with this, the logic address operation unit 310 and the physical address operation unit 320 calculate the logical addresses for the following drawing points and the corresponding physical addresses. Is executed. By repeating this process up to the end point P _e of the straight line, the pixel data for linear drawing is stored in the display memory sequentially.

In addition, the pixel data read out from the display memory is stored in the display memory again in a special case and replaced with constant data. However, in general, pixels existing on a straight line to be drawn are not limited to the same luminance or the same color. Therefore, in such a case, the readout pixel data is stored in the display memory as new pixel data for display, such as a calculation being performed with other data.

In the above embodiment, the logical space is shown in the case of two-dimensional, but it is also applicable to two-dimensional or more. According to this, even when the pixel data is displayed in plural bits, the logical address and the physical address corresponding to the logical address can be obtained at high speed.

Next, a description will be given of the case where high-speed transfer of pixel information to different pixel positions is performed in a method of storing data of a plurality of pixels in one word of a memory. It is realized by the characteristic hard structure, and high speed processing is attained. For convenience of explanation, FIG. 19 omits portions of the hard configuration shown in FIGS. 4 to 6 that are not related to the transfer process. The micro-instruction decoder 200 includes an address decoder 2002 and a shift amount decoder 2003 within one word. The command control register 230 stores a transfer mode, a bit mode, and the like.

The display memory 13 is provided with a sequential address in a structure in which one word is 16 bits. The source address is stored in (T2H, T2L) and the destination address is stored in (DPH, DPL) in the general-purpose register group 3208, respectively. That is, the address of the transfer source and the transmission line is managed by connecting two registers of 16 bits. The lower four bits of each address information designate a bit position in one word of the memory, and the upper bits designate an address of the display memory.

The shift amount decoder 2003 decodes the shift information to control the shift amount in the barrel shifter 3301. In the transfer process, the difference between the lower four bits of the destination address and the source address is the arithmetic logic operator (ALU) ( 3110, and the result is supplied to the shift amount decoder 2003 through a destination latch (DLA) 3111.

The address decoder in one word corresponds to the bit mode and transfer mode stored in the command control register 230. Based on the information of the difference between the lower 4 bits of the address information temporarily stored in the memory address register 3311 and the lower 4 bits of the source address and the destination address stored in the destination latch 3111, predetermined mask information is obtained. Is generated and sent to the mask register 3303.

20 (a) and 20 (b) are explanatory diagrams of the operation of the embodiment of FIG. The case of two transfer modes designated as transfer modes stored in the command control register 230 is shown. FIG. 20A shows the case of the one-pixel transfer mode in which only one pixel of data is transferred at a time. First, the source addresses T2H and T2L are selected, and one word of data including the source pixel is read out from the display memory 13 and sent to the barrel shifter 3301 via the read data buffer 3310. On the other hand, in the arithmetic logic operator 3110, the lower four bits of the source address and the destination address are subtracted, and a shift operation of a plurality of bits is performed by the barrel shifter 3301 through the shift amount decoder 2003. Next, DPL and DPH of the destination address register of the general-purpose register group 3208 are selected, and one word of data including the destination switch is read out, and the logical operator 3305 is read through the read data buffer 3310. Is sent to. On the other hand, the lower four bits of the destination address are decoded by the address decoder 2002 in one word, and mask information specifying the destination pixel position is output. In the logical operator 3305, the substitution operation is performed on the output of the barrel shifter 3301 only for the bit position designated by the mask information in the single word data of the destination. The result of this operation is stored in the destination address of the display memory via the write data buffer 3306. By repeating the transfer processing of one pixel while sequentially updating the source address and destination address, a large amount of data can be transferred at high speed regardless of the word boundary of the memory.

FIG. 20 (b) illustrates the operation of the multiple pixel transfer mode. In this case, the address decoder 2002 assigns " 1 " to the plurality of bit positions in accordance with the specification of the transfer mode bit in the command control register 230. FIG. Set. Therefore, it is possible to further speed up when transmitting a plurality of horizontally continuous bits.

As described above, according to the present embodiment, even when a plurality of pixels of data are stored in one word of the display memory, three or more memory accesses of source reading, destination reading and destination writing are performed for one or a plurality of arbitrary pixel positions. Pixel data can be transferred, and high-speed transfer is possible. By the GBM of the command control register 230, for example, five different operation modes (see Fig. 8) can be selected.

21 shows transmission of one pixel data in the case of 4 bit / 1 pixel mode. A process of reading one word data included in the source pixel and embedding only the source pixel data in the destination pixel position is necessary. 22 shows the flow of the transfer process. First, one word of the display memory 13 including the source pixel is read out and temporarily stored in the read data buffer 3310. On the other hand, the lower 4 bits of the address information specifying the source pixel and the lower 4 bits of the address information specifying the destination pixel are subtracted. This value represents the difference between the bit position of the source pixel and the destination pixel. The source read data is shifted to the barrel shifter 3301, and the source pixel C _s is adjusted to the position of the destination pixel. Subsequently, one word including the destination pixel C _d is read out, and a calculation with the source pixel C _s is performed by the logic operator 3305. At this time, since "1" is generated only at the destination pixel position as the mask information, only one pixel of the destination is updated to obtain write data. Types of logical operations may be substituted, logical operations, and the like. Also in the case of the 4 bit / pixel mode, only the format of the mask information is different, and the same operation is determined.

As described above, according to the present embodiment, even when data of one pixel is displayed with a plurality of bits, the pixel data can be transferred to any pixel position in three memory accesses of source read, destination read, and destination write. There is an effect.

FIG. 23 shows the pointer movement direction SD of the transfer command in the case where the quadrangular region is designated as an example of pixel data transfer, and shows eight of (a) to (h). Source area and destination area can be specified independently.

Next, arithmetic control in which the calculation of the pixel position in the transfer is easy will be described.

FIG. 24 specifically shows a part related to arithmetic control of the pixel position based on the configuration shown in FIG. The flag register 210 includes a code decoder 2101 and a code register 2102. The flag register 210 has an area determination flag, a zero flag, a negative flag, and the like, which are reflected depending on the state of the calculation result. However, the flag register 210 is not shown here because it is not used for the description.

In the command register 3207, command codes in commands transmitted from the outside through the FIFO memory 400 are temporarily stored. A part of the information of the command code is transmitted to the microprogram address register 110, and the microprograms are sequentially read out to perform arithmetic control in accordance with a predetermined processing algorithm.

The arithmetic and control unit 300 executes coordinate calculation for calculating the drawing address of the figure and processing of the figure data. The code decoder 2101 generates predetermined code data according to the present invention in accordance with some information of the command code and information provided from other components in the computing device 30.

The code register 2102 temporarily stores the code data generated by the code decoder 2101. The mode decoder 2009 disposed in the micro instruction decoder 200 decodes the processing mode field of the command to control arithmetic processing.

25A to 25E show the format (CDT) of the nosebleed (transfer) command. It consists of a command code of 1 word (16 bits) and the following parameters 1 to 4 of 4 words. By setting the parameters, various scanning directions can be selected during transmission.

Fig. 26 shows a conceptual diagram of an operation example of the kopi command. The parameters X _s and Y _s are starting point coordinates of the source (transfer source) area 13S as the read area. The parameters DX, DY define the direction and size of the area. In other words, starting from X _s and Y _s , the area is moved in the right direction in FIG. 25 at DX> 0, the left direction at DX <0, the upward direction at DY> 0, and the downward direction at DY <0. And specify the size in absolute values of DX and DY. The bit S in FIG. 25 (a) first indicates a scanning priority, and is a horizontal priority first when S = 0 and a vertical direction first when S = 1.

In the embodiment of Fig. 24, the first word in the command transmitted from the outside is recognized as a command code and is dimensioned to the command register 3207. The microprogram is started in accordance with the upper four bits of the command code to start the control of the nose copy processing.

The S bit in the command code and the OSD field (Fig. 25) are sent to the code register 2102 via the code decoder 2101. The lower processing mode field of the command code is decoded by the mode decoder (2009).

The parameters 1 to 4 are sequentially sent to the general purpose register group 3102 inside the arithmetic and control unit 300. The current drawing point coordinates (X, Y) are stored in registers CPX and CPY.

27A is a layout view showing a configuration example of the code register 2102 according to the present invention. This code register holds the next 10 bits of information. In addition, in this figure, the information stored in each register part is shown by the arrow, respectively, taking the case of the kopi command as an example.

(1) Q1

It is a 1st bit which switches between coordinate registers X and Y. In the copi command, it is used to determine the priority in the X-direction and Y-direction of scanning in the writing area, that is, the source area 13S. Therefore, the S bit of the command code is set as Q1.

When Q1 = 0, the X and Y registers are selected as specified. When Q1 = 1, the Y register is selected when X is specified and the X register when Y is specified.

(2) Q2

It is a 2nd bit which switches between coordinate registers X and Y. In the Pico command, it is used to switch between the X and Y directions of scanning in the destination area 13D which is the writing area. Therefore, bit 2 of the DSD field (Fig. 25) of the command code is set as Q2.

In Q2 = 0, the X and Y registers are selected as specified. In Q2 = 1, the registers are selected by reversing the specification of X and Y.

(3) S1x

It is 2-bit information that holds the operation code in the first X direction. In general, the upper bit of the two bits is for selecting whether to add or subtract, and whether the lower bit adds or subtracts (when the bit is "1") or not (bit is "0"). Is to make a choice).

In the Kopi command, the sign of the parameter DX is set in the upper bit, and "1" is set in the lower bit. That is, the upper bits are used as information for specifying the operation code in the X direction of the source region 13S.

(4) S1y

It is two bits of information that holds the operation code in the first Y direction, and is used for operation selection as in S1x described above.

In the kopi command, the sign (mutual bit) and "1" (low bit) of the parameter DY are set respectively, and the operation code in the Y direction of the source area 13S is designated.

(5) S2x

It is 2-bit information that holds the operation code in the second X direction, and the operation code in the X direction of the destination region 13D is designated in the Copi command. Bit 1 of the DSD field of the command is set higher and "1" is lower.

(6) S2y

It is 2-bit information that holds the operation code in the second Y direction, and the operation code in the Y direction of the destination region 13D is designated in the Copi command. Bit 1 of the DSD field of the command is set higher and "1" is lower.

Summarizing the above, S1x, S1y, S2x, and S2y can take four states, respectively, and when "00" and "10", "0" is added or subtracted (ie, no processing). If "01", "1" is added. If "11", "1" is subtracted.

As described above, in the Pico command, all of the lower bits of the registers S1x, S1y, S2x, and S2y of the code register 2102 are set to "1", but the command for performing other processing controls and changes these bits. It may be.

28 shows a processing flow of the kopi command. The contents of the expression specifying each register are as follows.

(1) X _s (Q1)

Specify the Xs register when Q1 = 0 and the Ys register when Q1 = 1. That is, it is the coordinate value of the 1st or preferential scanning direction of the source area 13S.

(2) Ys (Q1)

Specify the Ys register when Q1 = 0 and the Xs register when Q1 = 1. In other words. It is the coordinate value of the 2nd scanning direction of the source area 13S.

(3) X (Q2)

Specify the X register at Q2 = 0 and the Y register at Q2 = 1. That is, it is the coordinate value of the 1st or preferential scanning direction of the destination area | region 13D.

(4) Y (Q2)

Specify the Y register at Q2 = 0 and the X register at Q2 = 1. That is, it is the coordinate value of the 2nd scanning direction of the destination area | region 13D.

(5) S1x (Q1)

Select S1x at Q1 = 0 and S1y at Q1 = 1. That is, it is the code | symbol of the 1st (priority) scanning direction of the source area 13S.

(6) S1y (Q1)

Select S1y at Q1 = 0 and S1x at Q1 = 1. That is, it is the code | symbol of the 2nd scanning direction of the source area | region 13S.

(7) S2x (Q2)

Select S2x at Q2 = 0 and S2y at Q2 = 1. It is the sign of the 1st (priority) scanning direction of the destination area | region 13D.

(8) S2y (Q2)

Select S2y at Q2 = 0 and S2x at Q2 = 1. It is the sign of the 2nd scanning direction of the destination area | region 13D.

In Fig. 28, the kopi command first inputs parameters 1 to 4 following the command code, that is, Xs, Ys, DX, and DY, and stores them in a register inside the arithmetic and control device 300 (step S1).

Subsequently, processing for one line in the first (priority) scanning direction is started. To this end, the starting coordinate values of the Xs (Q1) and X (Q2), that is, the first (first) scanning direction of the source region 13S and the destination region 13D are saved (temporarily memorized) in another register (step S2). ).

Next, the pixel information of the coordinate point designated by (Xs, Ys) is transferred to the coordinate point designated by (X, Y) (step S3). Such transfer processing of one pixel is as described above.

Next, the code values S1x (Q1) and S2x (Q2) are added to the coordinate values Xs (Q1) and X (Q2) in the first scanning direction of the source region 13S and the destination region 13D. That is, the designated coordinate points of the respective areas are moved by one pixel in the first scanning direction, respectively (step S4).

The processing of steps S3 and S4 is repeated until the designated coordinate point reaches the end point of one line (step S5).

End line 1 processing. When the determination at step S5 is established, Xs (Q1) and X (Q2) are returned (step S6), and the code value S1y (Q1) and S2y are respectively applied to the second scanning direction coordinate values Ys (Q1) and Y (Q2). (Q2) is added, and the starting point coordinate of the second line is set (step S7).

The above-described processing of steps S2 to S7 is repeated until the determination of step S8 is established until the entire line processing in the second scanning direction is completed, whereby the entire data of the source area 13S can be transferred.

As described above, in the present embodiment, various pointer scan modes at the time of area data transfer can be realized in a single processing flow shown in FIG. 28, so that the control information (e.g., microprogram) can be greatly reduced or simplified. Can be.

Further, other commands and pattern commands can be applied similarly.

27B and 27C show the format of the pattern command. As apparent from the figure, this command consists of a command code of 1 word 16 bits and a parameter of 1 word.

The pattern command is a command that expands the pattern information stored in the pattern memory inside the figure processing apparatus onto the display memory. By selecting the operation mode of the command, various scanning can be performed on the pointer.

Claims (60)

An output device 40, 50 for outputting graphic data, connected to the output device, one pixel data comprising a plurality of bits, and for holding the graphic data constituting one word with a plurality of pixel data; A figure in which the memory 13 and the graphic data of one word designated by the read address are read out, predetermined pixel data in the read one word graphic data are specified, and the specified pixel data is written in accordance with a write address. Graphic processing system having a processing device (20, 30). 2. The graphics processing apparatus according to claim 1, wherein the figure processing apparatus has a logic operator 3305 for calculating and processing the specified pixel data according to mask information for specifying predetermined pixel data in the read one word graphic data. Figure processing system An output device 40, 50 for outputting graphic data, connected to the output device, one pixel data comprising a plurality of bits, and for holding the graphic data constituting one word with a plurality of pixel data; A memory 13, a read data buffer 3310 for reading and holding one word of graphic data designated by the read address, and predetermined pixel data in the read one word of graphic data. A shift operator 3301 for shifting the specified pixel data according to a write address; A doping processing device (20, 30) comprising a write data buffer (3306) for holding the shifted pixel data for writing to the display memory, and an address decoder (2002) for updating the read address and the write address. Figure processing system characterized in that it has. 4. The graphics processing system according to claim 3, wherein the address decoder updates in a different scanning direction on the display screen from the read address and the write address. 5. The logic operator (3305) according to claim 3 or 4, wherein the figure processing apparatus calculates and processes the specified pixel data according to mask information for specifying predetermined pixel data in the read one word graphic data. Figure processing system characterized in that it has a. 6. The figure processing system according to claim 5, wherein the mask information is held in a mask register (3303). 6. The figure processing system according to claim 5, wherein the mask information is generated according to the pixel address. The figure processing system according to claim 3 or 4, wherein the number of pixel data in the one word is variably changed. The figure processing system according to claim 3 or 4, wherein the number of bits constituting said one pixel data is variably changed. 5. The figure processing according to claim 3 or 4, wherein the plurality of read pixel data forms a read area 13S on a display screen, and the read address is an address specifying pixel data in the read area. system. One pixel data is composed of a plurality of bits, and accesses the display memory 13 which holds the graphic data constituting one word with a plurality of the pixel data and performs processing, and outputs the graphic data to the output devices 40 and 50. For outputting to the reader, the graphic data of the word designated by the read address is read out, predetermined pixel data in the read one word graphic data is specified, and the specified pixel data is written in accordance with the write address. One shape processing system. 12. The graphics processing system according to claim 11, wherein the figure processing system has a logic operator 3305 for calculating and processing the specified pixel data according to mask information for specifying predetermined pixel data in the read one word of graphic data. Figure processing system. One pixel data is composed of a plurality of bits, and accesses the display memory 13 which holds the graphic data constituting one word with a plurality of the pixel data and performs processing, and outputs the graphic data to the output devices 40 and 50. A read data buffer 3310 for reading and holding the one-word graphic data designated by the read-out address, and predetermined pixel data in the read one-word graphic data for outputting to the specified word data. A shift operator 3301 for shifting the write address according to a write address, a write data buffer 3306 for holding the shifted pixel data for writing to the display memory, an address decoder for updating the read address and the write address. (2002), characterized in that the graphics processing system. The graphics processing system according to claim 13, wherein the address decoder updates in a different scanning direction on the display screen from the read address and the write address. 15. The logic operator (3305) according to claim 13 or 14, wherein the figure processing system calculates and processes the specified pixel data according to mask information for specifying predetermined pixel data of the read one word graphic data. Figure processing system characterized in that it has a. 3. The figure processing system according to claim 2, wherein the mask information is held in a mask register (3303). 3. The figure processing system according to claim 2, wherein the mask information is generated according to the pixel address. 3. The graphics processing system according to claim 1 or 2, wherein the graphics processing apparatus has a shift operator (3301) for shifting pixel data to be written according to the read address and the write address. 3. The figure processing system according to claim 1 or 2, wherein the number of pixel data in said one word is variably changed. The figure processing system according to claim 1 or 2, wherein the number of bits constituting said one pixel data is variably changed. 3. The figure according to claim 1 or 2, wherein the plurality of read pixel data forms a read area 13S on a display screen, and the read address is an address specifying pixel data in the read area. Processing system. 3. The figure according to claim 1 or 2, wherein the plurality of pixel data to be written form a writing area 13D on a display screen, wherein the writing address is an address specifying pixel data in the writing area. Processing system. 3. The figure processing system according to claim 1 or 2, wherein the logic operator performs a logical operation on the pixel data of the read source and the pixel data of the write line. 5. The figure according to claim 3 or 4, wherein the plurality of pixel data to be written form a writing area 13D on a display screen, wherein the writing address is an address specifying pixel data in the writing area. Processing system. 5. The figure processing system according to claim 3 or 4, wherein the logic operator performs a logical operation on the pixel data of the read source and the pixel data of the write line. 13. The figure processing system according to claim 12, wherein the mask information is held in a mask register (3303). 13. The figure processing system according to claim 12, wherein the mask information is generated according to the pixel address. 13. The graphics processing system according to claim 11 or 12, wherein the graphics processing system has a shift operator (3301) for shifting pixel data to be written according to the read address and the write address. 13. The figure processing system according to claim 11 or 12, wherein the number of pixel data in the one word is variably changed. 13. The figure processing system according to claim 11 or 12, wherein the number of bits constituting said one pixel data is variably changed. 13. The figure according to claim 11 or 12, wherein the plurality of read pixel data forms a read area 13S on a display screen, and the read address is an address for specifying pixel data in the read area. Processing system. 13. The figure according to claim 11 or 12, wherein the plurality of pixel data to be written is formed on the display screen, and the write address is an address for specifying the pixel data in the write area. Processing system. 13. The figure processing system according to claim 11 or 12, wherein the logic operator performs a logical operation on the pixel data of the read source and the pixel data of the write line. 16. The graphics processing system according to claim 15, wherein said mask information is held in a mask register (3303). The figure processing system according to claim 15, wherein the mask information is generated according to the pixel address. 15. The graphics processing system according to claim 13 or 14, wherein the number of pixel data in the one word is variably changed. The figure processing system according to claim 13 or 14, wherein the number of bits constituting said one pixel data is variably changed. 15. The figure according to claim 13 or 14, wherein the plurality of read pixel data forms a read area 13S on a display screen, wherein the read address is an address specifying pixel data in the read area. Processing system. 15. The figure according to claim 13 or 14, wherein the plurality of pixel data to be written form a writing area 13D on a display screen, wherein the writing address is an address specifying pixel data in the writing area. Processing system. 15. The graphics processing system according to claim 13 or 14, wherein the logic operator performs a logical operation on the pixel data of the read source and the pixel data of the write line. One pixel data is composed of a plurality of bits, and accesses the display memory 13 which holds the graphic data constituting one word with a plurality of the pixel data and performs processing, and outputs the graphic data to the output devices 40 and 50. Reading out one word of graphic data specified by the read address, specifying predetermined pixel data in the read one word of graphic data, and writing the specified pixel data for output to And a step of writing in accordance with the figure. The method of claim 41. And wherein the figure processing method has a step of calculating and processing the specified pixel data in accordance with mask information for specifying predetermined pixel data of the read one word of graphic data. 43. The figure processing system according to claim 42, wherein the mask information is held in a mask register (3303) and has a step of reading out and processing the mask register. 43. The figure processing method according to claim 42, further comprising the step of generating the mask information according to a pixel address. 43. The figure processing method according to claim 41 or 42, wherein the figure processing method has a step of shifting pixel data to be written according to the read address and the write address. 43. The figure processing method according to claim 41 or 42, further comprising the step of variably changing the number of pixel data in said one word. 43. The figure processing method according to claim 41 or 42, comprising the step of variably changing the number of bits constituting said one pixel data. 43. The method of claim 41 or 42, wherein the plurality of read pixel data forms a read area 13S on the display screen, and wherein the read address has a step of generating an address specifying the pixel data in the read area. Characterized by the processing method. 43. The method according to claim 41 or 42, wherein the plurality of pixel data to be written form a writing area 13D on a display screen, and wherein the writing address has a step of generating an address specifying pixel data in the writing area. Characterized by the processing method. 45. The figure processing method according to claim 43 or 44, wherein the operation processing step includes a step of performing a logical operation between the pixel data of the read source and the pixel data of the write line. One pixel data is composed of a plurality of bits, and accesses the display memory 13 which holds the graphic data constituting one word with a plurality of the pixel data and performs processing, and outputs the graphic data to the output devices 40 and 50. In order to output to the print address, a read step for reading and holding the graphic data of one word specified by the read address, and predetermined pixel data in the graphic data of the read one word are specified, and the specified pixel data is written to the write address. And a shift step for shifting, a write step for holding the shifted pixel data for writing to the display memory, and an address decode step for updating the read address and the write address. 52. The graphics processing method according to claim 51, wherein the address decode step is updated in a different scanning direction on a display screen from the read address and the write address. The method according to claim 51 or 52, wherein the figure processing method has a step of calculating and processing the specified pixel data in accordance with mask information for specifying predetermined pixel data in the read one word graphic data. Figure processing system. 54. The figure processing method according to claim 53, wherein said mask information has a step of retaining in a mask register (3303). 54. The figure processing method according to claim 53, wherein the mask information is generated in accordance with the pixel address. 53. The figure processing method according to claim 51 or 52, further comprising the step of variably changing the number of pixel data in said one word. 53. The figure processing method according to claim 51 or 52, comprising the step of variably changing the number of bits constituting said one pixel data. 53. The method of claim 51 or 52, wherein the plurality of read pixel data forms a read area 13S on a display screen, and wherein the read address has a step of generating an address specifying pixel data in the read area. Characterized by the processing method. 53. The method of claim 51 or 52, wherein the plurality of pixel data to be written form a writing area 13D on a display screen, and wherein the writing address has a step of generating an address specifying pixel data in the writing area. Characterized by the processing method. 54. The graphics processing method according to claim 53, wherein the step of performing the arithmetic processing is performed logical operation of the pixel data of the read source and the pixel data of the write line.