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KR950007356B1 - Making method of tft for lcd - Google Patents

Making method of tft for lcd Download PDF

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KR950007356B1
KR950007356B1 KR1019920007978A KR920007978A KR950007356B1 KR 950007356 B1 KR950007356 B1 KR 950007356B1 KR 1019920007978 A KR1019920007978 A KR 1019920007978A KR 920007978 A KR920007978 A KR 920007978A KR 950007356 B1 KR950007356 B1 KR 950007356B1
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semiconductor layer
layer
forming
gate electrode
insulating
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KR930024190A (en
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김동규
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삼성전자주식회사
김광호
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/67Thin-film transistors [TFT]
    • H10D30/6704Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/1368Active matrix addressed cells in which the switching element is a three-electrode device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/67Thin-film transistors [TFT]
    • H10D30/6704Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Nonlinear Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Optics & Photonics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)

Abstract

내용 없음.No content.

Description

액정표시장치의 박막트랜지스터 및 그 제조방법Thin film transistor of liquid crystal display and manufacturing method

제1도는 종래 액정표시장치의 박막트랜지스터의 단면도.1 is a cross-sectional view of a thin film transistor of a conventional liquid crystal display device.

제2도는 이 발명에 따른 액정표시장치의 박막트랜지스터의 단면도.2 is a cross-sectional view of a thin film transistor of a liquid crystal display according to the present invention.

제3(a)~(d)도는 이 발명에 따른 액정표시장치의 박막트랜지스터의 제조공정도이다.3 (a) to 3d are manufacturing process diagrams of the thin film transistor of the liquid crystal display device according to the present invention.

본 발명은 액정표시장치의 박막트랜지스터 및 그 제조방법에 관한 것으로서, 특히 절연막에 둘러싸인 박막트랜지스터를 형성하여 공정이 간단하며, 적층막들의 단차피복성을 향상시켜 액정표시장치의 신뢰성을 향상시킬 수 있는 액정표시장치의 박막트랜지스터 및 그 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor of a liquid crystal display device and a method of manufacturing the same. In particular, the process is simple by forming a thin film transistor surrounded by an insulating film, and the reliability of the liquid crystal display device can be improved by improving step coverage of the laminated films. A thin film transistor of a liquid crystal display device and a manufacturing method thereof.

현재 랩탑(Lap Top) 및 노트북(Note book)형 컴퓨터, 휴대용 TV등에 널리 쓰이는 액정표시장치(Liquid Crystal Display ; 이하 LCD하 칭함)는 종래 음극선관(Cathode Ray Tube)에 비해 소비전력이 적으며, 경박단소화할 수 있는 장점이 있어 그 사용범위가 점차 넓어지고 있다. LCD의 대형화, 고정세화의 추세에 따라 LCD의 스위칭소자로 쓰이는 박막트랜지스터(Thin Film Transistor ; 이하 TFT라 칭함)의 소형화, 저항이 적은 금속배선, 재료의 선택, TFT를 형성하는 적층막들의 단차피복성(Ste Coverage)의 개선등이 중요한 과제가 되고 있다. 또한, 금속배선에 있어서는 금속배선의 두께 또는 폭이 저항과 반비례하므로 적당한 정도이하로는 감소시킬 수 없다. 따라서 기판과 금속배선과의 단차로 인하여 후속적층막의 단차피복성이 악화되는 문제점이 있어 금속배선을 절연성기판에 묻거나 경사에칭하는 등의 방법이 연구 실행되고 있다.Currently, liquid crystal displays (hereinafter referred to as LCDs), which are widely used in laptop tops, notebook computers, and portable TVs, consume less power than conventional cathode ray tubes. There is an advantage that can be reduced to light and short, the range of use is gradually widening. In accordance with the trend of large-sized and high-definition LCDs, thin film transistors (hereinafter referred to as TFTs), which are used as switching elements of LCDs, miniaturization of metal wiring, low-resistance metals, selection of materials, and step coverage of laminated films forming TFTs Improvements in ste coverage have become important tasks. In addition, in the metal wiring, the thickness or width of the metal wiring is inversely proportional to the resistance and cannot be reduced to an appropriate level or less. Therefore, there is a problem that the step coverage of the subsequent laminated film is deteriorated due to the step between the substrate and the metal wiring. Therefore, a method of burying the metal wiring on the insulating substrate or inclining etching is performed.

제1도는 종래 액정표시장치의 박막트랜지스터의 단면도를 나타낸 것으로, 게이트전극(13)이 절연층(12)에 묻힌 역스태거드형(Inverted Starered Type) TFT이다. 유리기판(11)상에 Al 또는 Cr등의 금속으로 게이트전극(13)이 형성되어 있으며, 상기 게이트전극(13)의 양측벽에 상기 게이트전극(13)과 같은 높이로 절연층(12)이 형성되어 있다. 산화규소 또는 질화규소로 된 게이트 절연막(14)이 상기 절연층(12)과 게이트전극(13)의 표면에 형성되어 있으며, 비정질실리콘으로된 반도체층(15)이 상기 게이트전극(13)상의 게이트절연막(14) 표면에 형성되어 있다. 또한, 상기 반도체층(15) 및 상기 게이트전극(13)상의 게이트 절연막(14) 표면에 형성되어 있다. 또한, 상기 반도체층(15) 및 게이트 절연막(14)의 상부에 Cr, Al 또는 Ta등의 금속으로 소오스전극(17)이 형성되어 있으며, 상기 소오스전극(17)과 소정간격 떨어진 반도체층(15)상에 게이트 절연막(14)과 겹치도록 드레인전극(18)이 형성되어 있다. 상기 소오스전극(17) 및 드레인전극(18)과 반도체층(15)의 접촉부위에 오옴믹접촉을 위한 고농도 반도체층(16)이 게제되어 있다.1 is a cross-sectional view of a thin film transistor of a conventional liquid crystal display device, which is an Inverted Starered TFT having a gate electrode 13 buried in an insulating layer 12. The gate electrode 13 is formed of a metal such as Al or Cr on the glass substrate 11, and the insulating layer 12 is formed on both side walls of the gate electrode 13 at the same height as the gate electrode 13. Formed. A gate insulating film 14 made of silicon oxide or silicon nitride is formed on the surface of the insulating layer 12 and the gate electrode 13, and a semiconductor layer 15 made of amorphous silicon is formed on the gate electrode 13. (14) It is formed on the surface. In addition, the semiconductor layer 15 and the gate electrode 13 on the gate insulating film 14 are formed on the surface. In addition, a source electrode 17 is formed of a metal such as Cr, Al, or Ta on the semiconductor layer 15 and the gate insulating layer 14, and the semiconductor layer 15 is spaced apart from the source electrode 17 by a predetermined distance. ), The drain electrode 18 is formed so as to overlap the gate insulating film 14. A high concentration semiconductor layer 16 for ohmic contact is disposed on the contact portion of the source electrode 17, the drain electrode 18, and the semiconductor layer 15.

상술한 종래 액정표시장치의 TFT는 게이트전극을 절연막에 묻어 게이트전극에 의한 단자를 제거하여 게이트 절연막, 반도체층, 소오스전극 및 드레인전극등 후속적층막들의 단차피복성을 향상시켰으나, TFT 제작시 절연층에 게이트전극이 형성될 홈을 형성하는 제1식각공정과, 반도체응를 패턴잉하는 제2식각공정과, 소오스 및 드레인전극을 패턴잉하는 제3식각공정등 세차례의 식각공정을 행해야 하므로 제조공정이 복잡한 문제점이 있었다.The TFT of the above-described conventional liquid crystal display device has a gate electrode buried in an insulating film to remove the terminal by the gate electrode, thereby improving the step coverage of the subsequent stacked films such as the gate insulating film, the semiconductor layer, the source electrode, and the drain electrode. Three etching processes are required: a first etching process for forming a groove in which a gate electrode is to be formed in a layer, a second etching process for patterning a semiconductor electrode, and a third etching process for patterning a source and a drain electrode. There was this complicated issue.

또한, 반도체층 패턴잉 공정시 반도체층의 표면이 오염되어 TFT의 신뢰성을 떨어뜨리고 반도체응의 단차에 의해 소오스 및 드레인전극의 단차피복성이 저하되는 문제점이 있다.In addition, during the semiconductor layer patterning process, the surface of the semiconductor layer is contaminated to reduce the reliability of the TFT, and the step coverage of the source and drain electrodes is degraded due to the step of semiconductor application.

따라서 이 발명은 제조공정이 간단하며, 반도체층 표면의 오염을 방지하고, 소오스 및 드레인 전극의 단차 피복성을 향상시켜 TFT의 신뢰성을 향상시킬 수 있는 액정표시장치의 TFT 및 그 제조방법을 제공함에 있다.Accordingly, the present invention provides a liquid crystal display TFT and a method of manufacturing the same, which can simplify the manufacturing process, prevent contamination of the surface of the semiconductor layer, and improve the reliability of the TFT by improving the step coverage of the source and drain electrodes. have.

상기와 같은 목적을 달성하기 위하여 이 발명은, 절연기판상에 형성되는 액정표시장치의 박막트랜지스터에 있어서, 유리재질의 절연기판과, 상기 절연기판의 상부에 순차적으로 적층되어 있는 게이트전극, 게이트 절연막 및 반도체층과, 상기 반도체층의 양단에 형성된 고농도 반도체층과, 상기 게이트전극, 게이트 절연막 및 반도체층의 측면을 감싸도록 형성되는 절연층과, 상기 고농도 반도체층과 절연층의 표면에 형성된 소오스 및 드레인전극으로 이루어지는 액정표시장치의 박막트랜지스터를 특징으로 한다. 또한, 이 발명은 액정표시장치의 박막트랜지스터 제조방법에 있어서, 절연기판의 전표면에 제1절연층을 형성하는 공정과, 상기 제1절연층상에 상기 제1절연층의 일부가 노출되도록 제1감광막 패턴을 형성하는 공정과, 상기 제2감광막 패턴에 의해 노출된 제1절연층을 소정깊이 제거하여 홈을 형성하는 공정과, 상기 구조의 전표면에 제1도전층, 제2절연층 및 반도체층 및 고농도 반도체층을 순차적으로 형성하는 공정과, 상기 제1감광막 패턴 및 제1감광막 패턴상의 제1도전층, 제2절연층 및 반도체층을 형성하는 공정과, 상기 구조의 전표면에 제2도전층을 형성하는 공정과, 상기 제2도전층의 상부에 반도체층의 채널영역이 노출되도록 제2감광막 패턴을 형성하는 공정과, 상기 제2감광막 패턴에 의해 노출된 제2도전층 및 고농도 반도체층을 순차적으로 제거하여 소오스 및 드레인전극을 형성한 후 제2감광막 패턴을 제거하는 공정으로 이루어지는 액정표시장치의 박막트랜지스터 제조방법을 특징으로 한다.In order to achieve the above object, the present invention is a thin film transistor of a liquid crystal display device formed on an insulating substrate, a glass insulating substrate, a gate electrode and a gate insulating film sequentially stacked on the insulating substrate And a semiconductor layer, a high concentration semiconductor layer formed at both ends of the semiconductor layer, an insulating layer formed to surround side surfaces of the gate electrode, the gate insulating film, and the semiconductor layer, a source formed on the surface of the high concentration semiconductor layer and the insulating layer, The thin film transistor of the liquid crystal display device which consists of a drain electrode is characterized by the above-mentioned. In addition, the present invention provides a method of manufacturing a thin film transistor of a liquid crystal display device, comprising the steps of forming a first insulating layer on the entire surface of the insulating substrate, and a portion of the first insulating layer exposed on the first insulating layer. Forming a photoresist pattern, forming a groove by removing a predetermined depth of the first insulating layer exposed by the second photoresist pattern, and forming a groove on the entire surface of the structure; Forming a layer and a highly concentrated semiconductor layer sequentially; forming a first conductive layer, a second insulating layer, and a semiconductor layer on the first photoresist pattern and the first photoresist pattern; and a second surface on the entire surface of the structure. Forming a conductive layer, forming a second photoresist pattern so that the channel region of the semiconductor layer is exposed on the second conductive layer, and a second conductive layer and a high concentration semiconductor exposed by the second photoresist pattern First layer sequentially Thereby, a method of manufacturing a thin film transistor of a liquid crystal display device comprising a process of removing a second photoresist pattern after forming a source and a drain electrode.

이하, 첨부한 도면을 참조하여 이 발명에 따른 액정표시장치의 박막트랜지스터 및 그 제조방법을 상세히 설명한다.Hereinafter, a thin film transistor and a method of manufacturing the liquid crystal display according to the present invention will be described in detail with reference to the accompanying drawings.

제2도는 이 발명에 따른 액정표시장치의 박막트랜지스터의 단면도이다.2 is a cross-sectional view of a thin film transistor of the liquid crystal display according to the present invention.

유리재질의 절연기판(21)상의 소정부위에 Al, Cr, Ta등의 금속으로 2000~4000Å 정도 두께의 게이트전극(25)이 형성되어 있다. 상기 게이트전극(25)의 상부에 산화규소 또는 질화규소로 1000~2000Å 정도 두께의 게이트 절연막(26)이 형성되어 있다. 이때 상기 게이트전극(25)과 게이트 절연막(26)의 경계면에 결함생성을 방지하기 위해 게이트전극(25)을 소정두께 양극산화하여 양극산화막을 형성한 후 게이트 절연막(26)을 형성하기도 한다. 계속해서 상기 게이트 절연막(26)의 표면에 다결정실리콘(이하, Poly-Si라 칭함), 비정질실리콘(이하, a-SI라 칭함) 또는 수소화된 비정질(이하, a-Si : H라 칭함)등으로 2000~3000Å 정도두께의 반도체층(27)이 형성되어 있다. 계속해서, 상기 게이트전극(25), 게이트 절연막(26) 및 반도체층(27)의 측면에 산화규소, 질화규소 또는 비피에스지(BPSG ; Boro-Phospho Silicate Glass)등과 같은 유리재질 절연물질등으로 절연층(22)이 형성되어 있다. 상기 절연층(22)의 두께는 상기 게이트전극(25)과 게이트 절연막(26) 그리고 반도체층(27)의 두께를 합한것과 비슷한 정도이다.On a predetermined portion of the insulating substrate 21 made of glass material, a gate electrode 25 having a thickness of about 2000 to 4000 m is formed of a metal such as Al, Cr, Ta, or the like. A gate insulating film 26 having a thickness of about 1000 to 2000 micrometers is formed on the gate electrode 25 with silicon oxide or silicon nitride. In this case, in order to prevent defects on the interface between the gate electrode 25 and the gate insulating film 26, the gate electrode 25 may be anodized to a predetermined thickness to form an anodized film, and then the gate insulating film 26 may be formed. Subsequently, polycrystalline silicon (hereinafter referred to as Poly-Si), amorphous silicon (hereinafter referred to as a-SI), or hydrogenated amorphous form (hereinafter referred to as a-Si: H) on the surface of the gate insulating film 26, etc. The semiconductor layer 27 of about 2000-3000 micrometers in thickness is formed. Subsequently, an insulating layer is formed on the side surfaces of the gate electrode 25, the gate insulating layer 26, and the semiconductor layer 27 by a glass insulating material such as silicon oxide, silicon nitride or BPSG (Boro-Phospho Silicate Glass). (22) is formed. The thickness of the insulating layer 22 is about the same as the sum of the thicknesses of the gate electrode 25, the gate insulating film 26, and the semiconductor layer 27.

계속해서, 상기 반도체층(27)의 양단에 고농도로 불순물이 도핑된 poly-Si, a-Si 또는 a-Si : H등으로 300~500Å 정도 두께로 고농도 반도체층(28)이 형성되어 있다. 상기 고농도 반도체층(27)은 반도체층(27)과 전극들의 오옴믹접촉을 위한 것이다. 계속해서, 상기 고농도 반도체층(27) 및 절연층(22)의 상부에 Al, Cr, Ta, W등의 금속으로 소오스전극(31)과 드레인전극(32)이 형성되어 있다. 상기와 같이 절연층(22)에 묻힌 박막트랜지스터는 각 층들간의 단차가 없으므로 단차피복성이 악화되지 않아 박막트랜지스터의 신뢰성을 향상시킬 수 있다.Subsequently, high-concentration semiconductor layers 28 are formed at both ends of the semiconductor layer 27 at a thickness of about 300 to 500 kV, such as poly-Si, a-Si, a-Si: H, and the like, which are heavily doped with impurities. The high concentration semiconductor layer 27 is for ohmic contact between the semiconductor layer 27 and the electrodes. Subsequently, a source electrode 31 and a drain electrode 32 are formed on metals such as Al, Cr, Ta, and W on the high concentration semiconductor layer 27 and the insulating layer 22. As described above, since the thin film transistor buried in the insulating layer 22 does not have a step between each layer, the step coverage may not be deteriorated, thereby improving reliability of the thin film transistor.

제3(a)~(d)도는 이 발명에 따른 액정표시장치의 박막트랜지스터 공정도이다. 특히, 역스태거드 TFT의 제조공정도이다.3 (a) to 3d are process charts of the thin film transistor of the liquid crystal display according to the present invention. In particular, it is a manufacturing process diagram of a reverse staggered TFT.

제3(a)도를 참조하면, 유리재질 절연기판(21)의 표면에 물리증착 또는 화학기상증착등의 방법으로 산화규소 또는 질화규소 5000~8000Å 정도 두께의 절연층(22)을 형성한다. 그 다음 상기 절연층(22)의 상부 표면에 상기 절연층(22)의 일부가 노출되도록 제1감광막 패턴(23)을 형성한다. 그 다음, 상기 제1감광막 패턴(23)에 의해 노출된 절연층(22)을 건식 또는 습식식각 방법으로 제거하여 홈(24)을 형성한다.Referring to FIG. 3 (a), the insulating layer 22 having a thickness of about 5000 to 8000 Pa of silicon oxide or silicon nitride is formed on the surface of the glass insulating substrate 21 by physical vapor deposition or chemical vapor deposition. Next, a first photoresist pattern 23 is formed on the upper surface of the insulating layer 22 so that a part of the insulating layer 22 is exposed. Next, the insulating layer 22 exposed by the first photoresist pattern 23 is removed by a dry or wet etching method to form the grooves 24.

제3(b)도를 참조하면, 상기 구조의 전표면에 물리증착 또는 화학기상증착등의 방법으로 2000~4000Å 정도 두께의 게이트전극(25), 1000~2000Å 정도 두께의 게이트 절연막(26), 2000~3000Å 정도 두께의 반도체층(27) 및 300~500Å 정도 두께의 고농도 반도체층(28)을 순차적으로 형성한다. 이때 상기 게이트전극(25)은 Al, Cr 또는 Ta등의 금속으로 형성하며, 상기 반도체층(27)은 poly-Si, a-Si 또는 a-Si : H등으로 형성하고, 고농도 반도체층(28)은 P 도는 n형 불순물이 고농도로 도핑된 poly-Si, a-Si 또는 a-Si : H등으로 형성한다. 이때 상기 절연층(22)에 형성된 홈(23)의 두께와 상기 게이트전극(25)과의 게이트 절연막(26) 그리고 반도체층(27)의 두께를 합한 정도와 비슷하다. 또한, 상기 게이트전극(25)과 게이트 절연막(26)의 경계면에 전위등의 결함이 발생하는 것을 방지하기 위해 상기 게이트전극(25)이 양극산화 가능한 금속일 경우에 게이트전극(25)의 상부 표면을 소정두께 양극산화하여 양극산화막을 형성한 후 게이트 절연막(26)을 형성할 수도 있다.Referring to FIG. 3 (b), the gate electrode 25 having a thickness of about 2000 to 4000 microns, the gate insulating film 26 having a thickness of about 1000 to 2000 microns, by physical vapor deposition or chemical vapor deposition on the entire surface of the structure, The semiconductor layer 27 having a thickness of about 2000 to 3000 mW and the high concentration semiconductor layer 28 of about 300 to 500 mW are sequentially formed. In this case, the gate electrode 25 is formed of a metal such as Al, Cr or Ta, and the semiconductor layer 27 is formed of poly-Si, a-Si or a-Si: H, and the like, and has a high concentration of the semiconductor layer 28. ) Is formed of poly-Si, a-Si, or a-Si: H, which is doped with a high concentration of P or n-type impurities. In this case, the thickness of the groove 23 formed in the insulating layer 22 and the thickness of the gate insulating layer 26 and the semiconductor layer 27 with the gate electrode 25 are approximately the same. In addition, the upper surface of the gate electrode 25 when the gate electrode 25 is an anodized metal in order to prevent defects such as dislocations from occurring at the interface between the gate electrode 25 and the gate insulating film 26. Is formed by anodizing a predetermined thickness to form an anodic oxide film, and then the gate insulating film 26 may be formed.

제3(c)도를 참조하면, 상기 제1감광막 패턴(23) 상에 순차적으로 적층한 게이트전극(25), 게이트 절연막(26), 반도체층(27) 및 고농도 반도체층(28)을 통상의 리프트오프(Lift Off) 방법으로 제거하여 절연층(23)의 홈(24)을 메꾼 게이트전극(25), 게이트 절연막(26), 반도체층(27) 및 고농도 반도체층(28)만 남긴다. 그 다음, 상기 절연층(22) 및 고농도 반도체층(29)의 표면에 물리증착 또는 화학기상증착등의 방법으로 Al, Ta, Cr 또는 W등의 금속으로 2000~4000Å 정도 두께로 도전층(29)을 형성한다. 그 다음, 상기 도전층(29)의 상부표면에 상기 반도체층(27)의 채널영역을 노출시키기 위해 제2감광막 패턴(30)을 형성한다.Referring to FIG. 3 (c), the gate electrode 25, the gate insulating film 26, the semiconductor layer 27, and the high concentration semiconductor layer 28 that are sequentially stacked on the first photoresist film pattern 23 are typically used. The gate electrode 25, the gate insulating layer 26, the semiconductor layer 27, and the high concentration semiconductor layer 28 having the grooves 24 of the insulating layer 23 filled out are removed by the lift off method. Subsequently, the conductive layer 29 may be formed on the surface of the insulating layer 22 and the high concentration semiconductor layer 29 by a metal such as Al, Ta, Cr, or W by a method such as physical vapor deposition or chemical vapor deposition. ). Next, a second photoresist pattern 30 is formed on the upper surface of the conductive layer 29 to expose the channel region of the semiconductor layer 27.

제3(d)도를 참조하면, 상기 제2감광막 패턴(30)에 의해 노출된 도전층(29) 및 고농도 반도체층(28)을 건식 또는 습식식각 방법으로 순차적으로 제거하여 반도체층(27)을 노출시키고, 소오스전극(31)과 드레인전극(32)을 형성한다.Referring to FIG. 3 (d), the conductive layer 29 and the high concentration semiconductor layer 28 exposed by the second photoresist layer pattern 30 may be sequentially removed by a dry or wet etching method. The source electrode 31 and the drain electrode 32 are formed.

상술한 바와 같이 이 발명은 액정표시장치의 박막트랜지스터를 절연층에 묻히도록 형성하여 TFT의 단차피복성을 향상시키고, 한번의 리프트오프 공정과 한번의 사진식각공정만 행하므로 반도체층과 게이트 절연막의 경계면, 고농도 반도체층과 소오스 및 드레인전극의 결함생성을 방지한다.As described above, the present invention forms the thin film transistor of the liquid crystal display device so as to be buried in the insulating layer to improve the step coverage of the TFT, and performs only one lift-off process and one photo etching process. The defect generation of the interface, the highly concentrated semiconductor layer and the source and drain electrodes is prevented.

따라서, 이 발명은 액정표시장치의 TFT 제조공정이 간단하며 TFT의 신뢰성을 향상시킬 수 있는 이점이 있다.Therefore, this invention has the advantage of simplifying the TFT manufacturing process of the liquid crystal display device and improving the reliability of the TFT.

Claims (4)

액정표시장치의 박막트랜지스터 제조방법에 있어서, 절연기판의 전표면에 절연층을 형성하는 공정과, 상기 절연층상에 상기 절연층의 일부가 노출되도록 제1감광막 패턴을 형성하는 공정과, 상기 제1감광막 패턴에 의해 노출된 절연층을 소정깊이 제거하여 홈을 형성하는 공정과, 상기 구조의 전표면에 게이트전극, 게이트 절연막, 반도체층 및 고농도 반도체층을 순차적으로 형성하는 공정과, 상기 제 1 감광막 패턴 및 제 1 감광막 패턴상의 게이트전극, 게이트 절연막, 반도체층 및 고농도 반도체층을 제거하는 공정과, 상기 구조의 전표면에 도전층을 형성하는 공정과, 상기 도전층의 상부에 반도체층의 채널영역이 노출되도록 제2감광막 패턴을 형성하는 공정과, 상기 제2감광막 패턴에 의해 노출된 제2도전층 및 고농도 반도체층을 순차적으로 제거하여 소오스 및 드레인전극을 형성한 후 제2감광막 패턴을 제거하는 공정으로 이루어지는 액정표시장치의 박막트랜지스터 제조방법.A method of manufacturing a thin film transistor of a liquid crystal display device, the method comprising: forming an insulating layer on an entire surface of an insulating substrate; forming a first photosensitive film pattern on the insulating layer to expose a portion of the insulating layer; Forming a groove by removing a predetermined depth of the insulating layer exposed by the photosensitive film pattern, sequentially forming a gate electrode, a gate insulating film, a semiconductor layer, and a high concentration semiconductor layer on the entire surface of the structure; and the first photosensitive film Removing a gate electrode, a gate insulating film, a semiconductor layer and a high concentration semiconductor layer on the pattern and the first photoresist pattern, forming a conductive layer on the entire surface of the structure, and a channel region of the semiconductor layer on the conductive layer. Forming a second photoresist pattern so as to expose the photoresist, and sequentially removing the second conductive layer and the high concentration semiconductor layer exposed by the second photoresist pattern. Method for manufacturing a thin film transistor over the source and drain electrodes after forming the liquid crystal comprising a step of removing the second photosensitive film pattern display device. 제1항에 있어서, 상기 절연층 식각공정을 건식 또는 습식식각방법으로 되는 군으로부터 선택되는 하나의 식각방법으로 행하는 액정표시장치의 박막트랜지스터 제조방법.2. The method of claim 1, wherein the insulating layer etching process is performed by one etching method selected from the group consisting of a dry or a wet etching method. 제1항에 있어서, 상기 제1도전층 형성공정후 제1도전층의 일부를 양극산화하여 양극산화막을 형성하는 공정을 추가로 구비하는 액정표시장치의 박막트랜지스터 제조방법.The method of claim 1, further comprising: anodizing a part of the first conductive layer after the first conductive layer forming step to form an anodized film. 제1항에 있어서, 상기 제1감광막 패턴 및 제1감광막 패턴상의 게이트전극, 게이트 절연막, 반도체층 및 고농도 반도체층을 제거하는 공정을 통상의 리프트오프 공정으로 행하는 액정표시장치의 박막트랜지스터 제조방법.The method of manufacturing a thin film transistor of a liquid crystal display device according to claim 1, wherein the step of removing the gate electrode, the gate insulating film, the semiconductor layer, and the highly concentrated semiconductor layer on the first photoresist pattern and the first photoresist pattern is performed by a normal lift-off process.
KR1019920007978A 1992-05-12 1992-05-12 Making method of tft for lcd Expired - Fee Related KR950007356B1 (en)

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