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KR950007028B1 - Shutter speed controlling circuit for camera system - Google Patents

Shutter speed controlling circuit for camera system Download PDF

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Publication number
KR950007028B1
KR950007028B1 KR1019920013087A KR920013087A KR950007028B1 KR 950007028 B1 KR950007028 B1 KR 950007028B1 KR 1019920013087 A KR1019920013087 A KR 1019920013087A KR 920013087 A KR920013087 A KR 920013087A KR 950007028 B1 KR950007028 B1 KR 950007028B1
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shutter speed
data
camera system
nxr
control signal
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KR940002655A (en
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김직
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금성일렉트론주식회사
문정환
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    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03BAPPARATUS OR ARRANGEMENTS FOR TAKING PHOTOGRAPHS OR FOR PROJECTING OR VIEWING THEM; APPARATUS OR ARRANGEMENTS EMPLOYING ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ACCESSORIES THEREFOR
    • G03B9/00Exposure-making shutters; Diaphragms
    • G03B9/08Shutters

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)

Abstract

내용 없음.No content.

Description

카메라 시스템의 셔터 속도 제어회로Shutter speed control circuit of camera system

제1도는 종래 카메라 시스템의 셔터 속도 제어회로의 블럭도.1 is a block diagram of a shutter speed control circuit of a conventional camera system.

제2도는 제1도에 있어서, 데이타에 따른 셔터 속도의 상태도.2 is a state diagram of shutter speed according to data in FIG. 1;

제3도는 제1도에 있어서, 직렬데이타의 파형도.3 is a waveform diagram of serial data in FIG.

제4도는 본 발명 카메라 시스템의 셔터 속도 제어회로도.4 is a shutter speed control circuit diagram of the camera system of the present invention.

제5도는 제4도에 있어서, 데이타 출력시 타이밍도.5 is a timing diagram at the time of outputting data.

제6a, b도는 제4도에 있어서, 데이타에 따른 셔터 속도의 상태도.6A and 6B show the state of the shutter speed in accordance with the data in FIG.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 데이타셀렉터 2 : 디코더1: data selector 2: decoder

3 : 카운터 11 : 메모리3: counter 11: memory

12 : 래치 13 : 제어신호출력부12: latch 13: control signal output unit

NXR1-NXR9: 배타적노아게이트 NA1: 낸드게이트NXR 1 -NXR 9 : Exclusive Noagate NA 1 : Nandgate

본 발명은 메모리를 이용한 셔터 속도 제어에 관한 것으로, 특히 씨씨디 카메라 시스템에서 셔터 스피드의 데이타를 메모리에 저장하여 로직을 간략히 하고 칩의 면적을 최소화하는 카메라 시스템의 셔터 속도 제어회로에 관한 것이다.The present invention relates to a shutter speed control using a memory, and more particularly, to a shutter speed control circuit of a camera system that simplifies logic and minimizes chip area by storing shutter speed data in a memory in a CD camera system.

제1도는 종래 카메라 시스템의 셔터 속도 제어회로도로서 이에 도시된 바와같이, 모드신호(Mode4)에 따라 직렬데이타(Si)를 입력받아 병렬데이타(Pi)로 출력하는 데이타셀렉터(1)와, 이 데이타셀렉터(1)의 출력(Pi)을 입력받아 디코딩한 신호(SS1,-SS9)를 출력하는 6×9디코더(2)와, 이 디코더(2)의 출력(SS1,-SS9)을 초기값으로 하여 512진까지 카운팅한 신호(Xsub)를 출력하는 카운타(3)로 구성된 것으로, 상기 데이타 셀렉터(1)의 병렬데이타(Pi)는 (D0-D2,FL1,FL2,ENB)의 6개 데이타이고, 상기 카운터(3)는 9비트 카운터이다.FIG. 1 is a shutter speed control circuit diagram of a conventional camera system. As shown therein, a data selector 1 that receives serial data Si according to a mode signal Mode 4 and outputs the parallel data Pi, and 6x9 decoder 2 for receiving the output Pi of the data selector 1 and outputting the decoded signals SS 1 , -SS 9 , and the outputs of the decoder 2 (SS 1 , -SS 9). ) And a counter (3) which outputs a signal (Xsub) counted up to 512 digits as an initial value. The parallel data Pi of the data selector 1 is (D 0 -D 2 , FL 1 , FL). 2 , ENB), and the counter 3 is a 9-bit counter.

이와같이 구성된 본 발명 카메라 시스템의 셔터 속도 제어회로의 동작과정을 제2도 데이타에 따른 셔터 속도의 상태도, 제3도 직렬데이타의 파형도를 참조하여 설명하면 다음과 같다.The operation of the shutter speed control circuit of the camera system constructed as described above will be described with reference to the state diagram of the shutter speed according to FIG. 2 data and the waveform diagram of FIG. 3 serial data.

먼저, 모드신호(Mode4)가 저전이일때 제3a도에 도시된 바와같이 클럭(CLK)이 입력됨에 따라 제3b도에 도시된 바와같이 직렬데이타(Si)가 데이타셀렉터(1)에 입력되고 제3c도에 도시된 바와같이 상기 모드신호(Mode4)가 고전위가 되면 상기 데이타셀렉터(1)에서 병렬데이타(Pi)가 6×9디코더(2)에 출력된다.First, as the clock CLK is inputted as shown in FIG. 3a when the mode signal Mode 4 is low transition, serial data Si is inputted to the data selector 1 as shown in FIG. 3b. As shown in FIG. 3C, when the mode signal Mode 4 becomes high potential, the parallel data Pi is output from the data selector 1 to the 6x9 decoder 2.

이때, 모드신호(Mode3)가 입력됨에 따라 카메라 시스템의 동작 모드를 결정하는데 상기 모드신호(Mode3)가 저전위이면 PAL로, 고전위이면 NTSC로 동작된다.At this time, when the mode signal Mode 3 is inputted, the operation mode of the camera system is determined. When the mode signal Mode 3 is low potential, PAL is operated, and if it is high potential, NTSC is operated.

이에따라, 디코더(2)는 데이타셀렉터(1)의 병렬데이타(Pi)를 입력받아 각 데이타(ENB), (FL1), (FL3), (D0-D2)의 조합에 의해 디코딩된 값(SS1-SS9)이 결정되는데, 제2도에 도시된 바와같이 상기 각 데이타(ENB), (FL1), (FL2), (D0-D2)의 전위에 따라 디코딩값이 결정되어 셔터 속도가 결정된다.Accordingly, the decoder 2 receives the parallel data Pi of the data selector 1 and decoded by a combination of each data ENB, (FL 1 ), (FL 3 ), and (D 0 -D 2 ). Values SS 1 -SS 9 are determined, as shown in FIG. 2 , according to the potential of each of the data ENB, FL 1 , FL 2 , and D 0 -D 2 . This is determined so that the shutter speed is determined.

즉, 카운터(3)는 디코더(2)의 출력(SS1-SS9)을 입력받아 그 디코딩값(SS1-SS9)을 초기값으로 세팅하여 512진(=29)까지 카운팅함으로써 세팅된 초기값과 512(=29)까지의 차이가 셔터 속도의 간격이 되며 출력신호(Xsub) 값이 된다.That is, the counter 3 is set by receiving the outputs SS 1 -SS 9 of the decoder 2 and setting the decoding values SS 1 -SS 9 as initial values and counting up to 512 digits (= 2 9 ). The difference between the initial value and 512 (= 2 9 ) becomes the interval of the shutter speed and becomes the output signal (Xsub) value.

그러나, 이와같은 종래 회로는 셔터 속도값을 출력하기 위해 200여개의 게이트가 필요하고 레이아웃(Layout) 면적도 전체 칩사이즈의정도를 차지할 만큼 큰 면적이 소요되는 문제점이 있었다.However, such a conventional circuit requires about 200 gates to output the shutter speed value, and the layout area also has a total chip size. There was a problem that it takes a large area to occupy the degree.

본 발명은 이러한 문제점을 감안하여 셔터 속도에 따른 데이타를 메모리에 저장하고 병렬데이타에 따라 셔터 속도값을 출력하는 카메라 시스템의 셔터 속도 제어회로를 창안한 것으로, 이를 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.In consideration of such a problem, the present invention has been made a shutter speed control circuit of a camera system for storing data according to shutter speed in a memory and outputting a shutter speed value according to parallel data, which will be described in detail with reference to the accompanying drawings. As follows.

제4도는 본 발명 카메라 시스템의 셔터 속도 제어회로도로서 이에 도시한 바와같이, 병렬데이타(D0-D2), (FL1), (FL2), (ENB) 및 모드신호(Mode3)를 입력받아 해당 저장값(SS1,-SS9)을 출력하는 메모리(11) 와, 제어신호(XSG1)에 상기 메모리(11)의 출력(SS1,-SS9)을 입력받아 제어신호(XSG2)에 출력하는 래치(12)와, 이 래치(12)의 출력(SS1,-SS9)과 외부카운터값(Ctn1-Ctn9)을 배타적으로 비교하여 그 논리값을 낸딩하는 제어신호출력부(13)로 구성한 것으로, 상기 제어 신호출력부(13)는 일측에 래치출력(SS1-SS9)이 각기 접속한 배타적 노아게이트(NXR1-NXR9)의 타측에 외부카운터값(Ctn1-Ctn9)을 각기 접속하고 상기 배타적노아게이트(NXR1-NXR9)의 출력(V1-V9)을 낸드게이트(NA1)에 입력시켜 제어신호(Xsub)가 출력하도록 구성한다.4 is a shutter speed control circuit diagram of a camera system according to the present invention. As shown therein, parallel data (D 0 -D 2 ), (FL 1 ), (FL 2 ), (ENB) and a mode signal (Mode 3 ) receiving by receiving the stored value (SS 1, -SS 9) output (SS 1, -SS 9) of the memory 11 in the memory 11, and a control signal (XSG 1) for outputting a control signal ( A control for exclusively comparing the latch 12 output to the XSG 2 ), the outputs SS 1 and -SS 9 of the latch 12 with the external counter values Ctn 1 to Ctn 9 , and outputting the logic value. be configured as a signal output section 13, the control signal output section 13 outputs a latch (SS 1 -SS 9) outside the counter value on the other side of the exclusive-NOR gate (NXR 1 -NXR 9), each one connected to one side (Ctn 1 -Ctn 9 ) are connected to each other, and the output of the exclusive NOR gates (NXR 1 -NXR 9 ) (V 1 -V 9 ) to the NAND gate (NA 1 ) is configured to output the control signal (Xsub) do.

이와같이 구성한 본 발명 카메라 시스템의 셔터 속도 제어회로의 작용 및 효과를 제5도 데이타 출력시 타이밍도, 제6도 데이타에 다른 셔터 속도의 상태도를 참조하여 상세히 설명하면 다음과 같다.The operation and effect of the shutter speed control circuit of the camera system constructed as described above will be described in detail with reference to the timing chart at the time of outputting the data of FIG. 5 and the state of the shutter speed different from the data of FIG.

먼저, 모드신호(Mode3)의 레벨에 따라 카메라 시스템의 동작모드가 결정될때 메모리(11)에 병렬데이타(D0-D2), (FL1), (FL2), (ENB)가 입력하면 병렬데이타값에 해당하는 데이타(SS1-SS9)가 래치(12)에 출력한다.First, parallel data (D 0 -D 2 ), (FL 1 ), (FL 2 ), and (ENB) are input to the memory 11 when the operation mode of the camera system is determined according to the level of the mode signal (Mode 3 ). The data (SS 1 -SS 9 ) corresponding to the parallel data values are output to the latch 12.

이때, 래치(12)에 제5a도에 도시한 바와같이 제어신호(XSG1)가 저전위로 입력하면 메모리(11)의 출력(SS1-SS9)을 일시저장하고 제5b도에 도시한 바와같이 제어신호(XSG2)가 저전위로 입력할때 상기 래치(12)는 래치시킨 데이타(SS1-SS9)를 제어신호출력부(13)에 출력한다.At this time, when the control signal XSG 1 is input to the latch 12 at a low potential as shown in FIG. 5A, the outputs SS 1 -SS 9 of the memory 11 are temporarily stored and as shown in FIG. 5B. Likewise, when the control signal XSG 2 is input at the low potential, the latch 12 outputs the latched data SS 1 to SS 9 to the control signal output unit 13.

따라서, 제어신호출력부(13)는 래치(12)의 출력(SS1-SS9)을 배타적노아게이트(NXR1-NXR9)의 일측에 각기 입력시킴과 아울러 외부카운터값(Cnt1-Cnt9)을 타측에 입력시켜 비교한 출력(V1-V9)을 낸드게이트(NA1)에서 낸딩함으로써 제어신호(Xsub)가 출력한다.Thus, the control signal output section 13 is a latch 12, the output (SS 1 -SS 9) an exclusive NOR gate (NXR 1 -NXR 9), each input Sikkim as well as outside the counter value to one side of (Cnt 1 -Cnt of 9 ) is input to the other side, and the control signals Xsub are output by outputting the compared outputs V 1 -V 9 from the NAND gate NA 1 .

즉. 메모리(11)에 병렬데이타(Pi)가 입력함에 따라 제6a,b도에 도시한 바와같은 셔터 속도 데이타(SS1-SS9)가 래치(12)에 출력하고 제어신호출력부(13)는 제어신호(XSG1), (XSG2)에 따른 래치(12)의 출력(SS1-SS9)가 외부카운터값(Cnt1-Cnt9)을 배타적노아게이트(NXR1-NXR9)에서 비교하여 낸드게이트(NA1)에서 낸딩한다. 이에따라, 메모리(11)의 출력값(SS1-SS9)이 외부카운터값(Cnt1-Cnt9)과 일치되었을때 카메라 시스템의 셔터 속도 제어신호(Xsub)가 고전위에서 저전위로 인에이블되어 출력한다.In other words. As the parallel data Pi is input to the memory 11, shutter speed data SS 1 to SS 9 as shown in Figs. 6A and 6B are output to the latch 12, and the control signal output unit 13 comparing the control signal (XSG 1), (XSG 2 ) the output of the latch (12) (SS 1 -SS 9 ) the external counter value (Cnt 1 -Cnt 9) an exclusive NOR gate (NXR 1 -NXR 9) according to the To NAND gate NA 1 . Yiettara, the shutter speed control signal (Xsub) of the camera system is enabled and outputs low potential when the output value up on Classical (SS 1 -SS 9) of the memory 11 is consistent with the external count value (Cnt 1 -Cnt 9) .

상기에서 상세히 설명한 바와같이 본 발명 카메라 시스템의 셔터 속도 제어회로는 셔터 속도에 따른 데이타를 메모리에 저장하여 입력데이타에 따라 출력함으로써 회로구성이 간단하고 레이아읏(Layout) 면적이 감소하는 효과가 있다.As described in detail above, the shutter speed control circuit of the camera system of the present invention stores the data according to the shutter speed in the memory and outputs the data according to the input data, thereby simplifying the circuit configuration and reducing the layout area.

Claims (2)

병렬데이타(D6-D2), (FL1), (FL2), (ENB)와 모드신호(Mode|3)에 따른 데이타(SS1-SS9)를 출력하는 메모리(11)와, 제어신호(XSG1), (XSG2)에 따라 상기 메모리(11)의 출력(SS1-SS9)을 래치시키는 래치(12) 와, 이 래치(12)의 출력(SS|1-SS9)과 외부카운터값(Cnt1-Cnt9)을 비교하고 낸딩하여 제어신호(Xsub)를 출력하는 제어신호출력부(13)로 구성한 것을 특징으로 하는 카메라 시스템의 셔터 속도 제어회로.A memory 11 for outputting data (SS 1 -SS 9 ) according to the parallel data (D 6 -D 2 ), (FL 1 ), (FL 2 ), (ENB) and the mode signal (Mode | 3 ), A latch 12 for latching the outputs SS 1 -SS 9 of the memory 11 according to the control signals XSG 1 and XSG2, and the outputs SS | 1- SS 9 of the latch 12. And a control signal output unit (13) for outputting a control signal (Xsub) by comparing and NAND with external counter values (Cnt 1 -Cnt 9 ). 제1항에 있어서, 제어신호출력부(13)는 래치(12)의 출력(SS1-SS9)이 일측에 각기 접속된 배타적노아게이트(NXR1-NXR9)의 타측에 외부카운터값(Cnt1-Cnt|9)을 각기 접속하고 상기 배타적노아게이트(NXR1-NXR9)의 출력(V1-V9)을 낸드게이트(NA1)에 입력시켜 제어신호(Xsub)가 출력하도록 구성한 것을 특징으로 하는 카메라 시스템의 셔터 속도 제어회로.The method of claim 1, wherein the control signal output section 13 has external counter value in the other of the output (SS 1 -SS 9) an exclusive NOR gate (1 -NXR NXR 9) each connected to one side of the latch 12 ( Cnt 1 -Cnt | 9 ) are connected to each other, and the outputs of the exclusive nodal gates (NXR 1 -NXR 9 ) (V 1 -V 9 ) are input to the NAND gate (NA 1 ) so that the control signal (Xsub) is output. Shutter speed control circuit of the camera system, characterized in that.
KR1019920013087A 1992-07-22 1992-07-22 Shutter speed controlling circuit for camera system Expired - Fee Related KR950007028B1 (en)

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KR1019920013087A KR950007028B1 (en) 1992-07-22 1992-07-22 Shutter speed controlling circuit for camera system

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Application Number Priority Date Filing Date Title
KR1019920013087A KR950007028B1 (en) 1992-07-22 1992-07-22 Shutter speed controlling circuit for camera system

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KR950007028B1 true KR950007028B1 (en) 1995-06-26

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