KR950006983B1 - Input protection circuit in semiconductor device - Google Patents
Input protection circuit in semiconductor device Download PDFInfo
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- KR950006983B1 KR950006983B1 KR1019920020711A KR920020711A KR950006983B1 KR 950006983 B1 KR950006983 B1 KR 950006983B1 KR 1019920020711 A KR1019920020711 A KR 1019920020711A KR 920020711 A KR920020711 A KR 920020711A KR 950006983 B1 KR950006983 B1 KR 950006983B1
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- semiconductor device
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
- H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
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Abstract
내용 없음.No content.
Description
제1도는 종래의 ESD보호용 전원패드 및 전원선의 배치도.1 is a layout view of a conventional ESD protection power pad and power line.
제2도는 ESD보호소자의 평면구성도.2 is a plan view of the ESD protection device.
제3도는 본 발명에 따른 ESD보호용 전원패드 및 전원선의 배치도.3 is a layout view of the ESD protection power pad and power line according to the present invention.
본 발명은 반도체장치의 정전방전(ESD)에 대한 보호장치에 관한 것으로, 특히 다수개의 전원핀들을 사용하는 반도체장치에서 ESD에 대한 보호를 위한 장치에 관한 것이다.The present invention relates to a device for protection against electrostatic discharge (ESD) of a semiconductor device, and more particularly to a device for protection against ESD in a semiconductor device using a plurality of power pins.
집적회로의 집적화가 증가하면서 하나의 칩내에서 동작되는 회로의 수는 많아지고, 그 결과 전력소모가 중개됨에 따라 전원핀의 수를 증가시키게 되었다. 또한 메모리장치에서는 입출력의 갯수가 멀티비트(MULTIBIT)화 되는 추세에 있고 이런 바이트 또는 워드확장형의 메모리장치에서는 출력시 짧은 시간 동안에 급격히 많은 전류가 흐르므로, 출력핀 8개당 하나의 전원전압 Vcc, 하나의 접지접압 Vss를 위한 전원핀이 하나씩 증가되고 있다.As the integration of integrated circuits increases, the number of circuits operating in one chip increases, and as a result, the number of power pins increases as power consumption is mediated. In addition, in the memory device, the number of input / output is multi-bit (MULTIBIT), and in the byte- or word-expanded memory device, a large amount of current flows for a short time during output, so one power voltage Vcc, one per eight output pins is used. The power pin for the ground contact voltage Vss at is increasing by one.
제1도의 종래기술은 국내특허 91-16125에서 개시된 것으로서, 두 개 이상의 Vcc 또는 두 개 이상의 Vss를 갖는 반도체장치에 있어서, Vcc핀들까지 칩내에서 모두 금속선으로 연결하고, Vss핀들까지 칩내에서 모두 금속선으로 연결한 다음, 이를 각 입출력패드에 인접하여 존재하는 ESD보호소자(200)의 전원으로 사용하는 구성으로 되어 있다. 또한, 제1도의 종래구성에서는, 기본적으로 각 전원핀이 갖고 있던 종래의 본딩패드, 즉 주변회로입력용헤드, 센스앰프구동용 패드 및 입출력버퍼입력용 패드등의 다수개의 패드들을 그대로 가지면서 이들중 한 개 이상이 다른 전원핀의 패드와 칩내에서 금속선으로 연결되어 있다.The prior art of FIG. 1 is disclosed in Korean Patent No. 91-16125. In a semiconductor device having two or more Vccs or two or more Vss, the Vcc pins are all connected to the metal wire in the chip, and the Vss pins are all the metal wire in the chip. After the connection, it is configured to be used as a power source for the ESD protection element 200 existing adjacent to each input / output pad. Also, in the conventional configuration of FIG. 1, the conventional bonding pads that each power pin has, that is, have a plurality of pads such as peripheral circuit input heads, sense amplifier driving pads, and input / output buffer input pads as they are. At least one of them is connected to the pad of the other power pin by a metal wire in the chip.
제1도의 ESD보호소자(200)의 구성은 제2도에 나타나 있다. 제1도의 패드 P1과 Vss1Vss3사이의 ESD방전경로는 제2도의 제1확산영역(10)과 제2확산영역(20)사이에서 이루어지는 펀치스로우현상에 의해 만들어지고, 패드 P1과 VccVcc3사이의 ESD방전경로는 제2도의 제1확산영역(10)제2확산영역(20)제3확산영역(30)사이에서 일어나는 펀치스루우현상에 의해 만들어진다. 이런 칩내에서의 모든 입출력해드와 모든 전원패드사이의 정전기에 의한 스트레스전하들은 각 패드의 옆에 존재하는 제3도와 같은 ESD보호소자에서의 펀치스루우과정에 의해 방전된다. 이때, 전원패드는 칩의 전원잡음에 의한 간섭을 받지 않기 위하여 주변회로공급용, 셀어레이의 센스 앰프공급용 및 워드라인전위유지용등으로 한개의 전원핀에 여러개의 전원 패드들을 갖추고 있다. 그러나, 이러한 종래의 구조에서는, ESD보호소자에 전원을 공급하기 위하여 여러개의 전원핀들을 칩내에서 금속선으로 직접 연결하였기 때문에, 전원핀들 각각의 분리된 기능이 서로간의 전언잡음에 의해 영향을 받게 되어 TTL입력버퍼의 입력레벨마진 및 속도등의 전기적 특성이 악화되는 문제가 있다.The configuration of the ESD protection device 200 of FIG. 1 is shown in FIG. The ESD discharge path between the pads P1 and Vss1Vss3 in FIG. 1 is made by a punch throw phenomenon between the first diffusion region 10 and the second diffusion region 20 in FIG. 2, and the ESD discharge between the pads P1 and VccVcc3. The path is created by the punch-through phenomenon occurring between the first diffusion region 10, the second diffusion region 20, and the third diffusion region 30 in FIG. The electrostatic stress charges between all the input / output heads and all the power pads in the chip are discharged by the punch-through process in the ESD protection device as shown in FIG. 3 next to each pad. At this time, the power pad has a plurality of power pads on one power pin for supplying a peripheral circuit, supplying a sense amplifier of a cell array, and maintaining a word line potential so as not to be affected by the noise of the chip. However, in this conventional structure, since several power pins are directly connected by metal wires in a chip for supplying power to an ESD protection device, the separate functions of the power pins are affected by the noise of each other. There is a problem that the electrical characteristics such as input level margin and speed of the input buffer deteriorate.
따라서 본 발명의 목적은 다수개의 전원핀들을 사용하는 반도체장치에 있어서 전원핀들간의 전원잡음영향을 억제하는 입력보호장치를 제공함에 있다.Accordingly, an object of the present invention is to provide an input protection device for suppressing the influence of power noise between power pins in a semiconductor device using a plurality of power pins.
상기 본 발명의 목적을 달성하기 위하여 본 발명은, 두 개 이상의 전원핀들을 가지며 상기 전원핀들에 해당하는 정전방전보호소자들을 가지는 반도체장치에 있어서, 상기 전원핀들의 각각과 와이어본딩된 각각의 상기 정전방전보호소자전원공급용의 패드들과, 상기 정전방전보호소자전원공급용의 패드들과 각각 분리되고 상기 전원핀들의 각각과 와이어본딩되며 상기 반도체장치내의 소정회로에 전원을 공급하기 위한 패드들과, 상기 정전방전보호소자전원공급용의 패드들을 연결하는 금속선을 구비함을 특징으로 한다. 여기서, 상기 반도체장치내의 소정회로는 주변회로, 센스앰프 및 입출력 버퍼등이 해당된다.In order to achieve the object of the present invention, the present invention is a semiconductor device having two or more power pins and having an electrostatic discharge protection element corresponding to the power pins, each of the power pins and each of the electrostatic Pads for supplying discharge protection device power, pads for supplying power to a predetermined circuit in the semiconductor device, each of which is separated from the pads for supplying the electrostatic discharge protection device power supply and wire-bonded with each of the power pins; And a metal wire connecting the pads for power supply of the electrostatic discharge protection device. Here, the predetermined circuit in the semiconductor device corresponds to a peripheral circuit, a sense amplifier, an input / output buffer, and the like.
이하 본 발명은 제3도를 참조하여 상세히 설명한다. 제3도를 참조하면, Vss1은 출력버퍼공급용 접지전압핀이고, Vss2는 셀어레이의 센스앰프공급용 접지전압핀, Vss3는 주변회로공급용 접지전압핀이다. 이들 세개의 접지전압핀들은 하나의 패드를 사용하고 종래의 경우처럼 금속선으로 연결하면, 출력버퍼가 동작할때 Vss1에서 유기된 전원잡음이 금속선을 통하여 직접 주변회로에 영향을 주게 될 것이고 셀어레이의 센스앰프가 동작할 때에도 마찬가지로 주변회로에 전원잡음을 인가하게 될 것이다. 그래서 제3도의 본 발명의 실시예에서는, Vss1, Vss2, Vss3에 ESD보호소자 공급용의 독립적인 패드 P11, P22, P33을 각각 설치하여 와이어본딩(L11, L22, L33)하였다. 따라서, 출력버퍼가 동작하는 경우에 Vss1에서 유기된 전원잡음은 L11L12Vss버스L32P31의 경로를 거쳐 주변회로공급용 패드 P31에 전달되므로 Vss1의 전원잡음은 감쇄된다. 같은 방법으로, 셀어레이의 센스앰프동작시에도 Vss2에서 유기된 전원잡음은 L21L22Vss버스L32L31P31의 경로를 통하여 주변회로공급용 패드 P31에 전달되므로, 주변회로에 미치는 Vss2의 전원잡음의 양을 현저하게 줄일 수 있다.Hereinafter, the present invention will be described in detail with reference to FIG. Referring to FIG. 3, Vss1 is a ground voltage pin for output buffer supply, Vss2 is a ground voltage pin for supplying sense amplifier of the cell array, and Vss3 is a ground voltage pin for supplying peripheral circuits. If these three ground voltage pins use a single pad and are connected with a metal wire as in the conventional case, the power noise induced in Vss1 will directly affect the peripheral circuit through the metal wire when the output buffer is operated. When the sense amplifier operates, it will apply power noise to the peripheral circuits as well. Thus, in the embodiment of the present invention of FIG. 3, independent pads P11, P22, and P33 for supplying an ESD protection element are provided at Vss1, Vss2, and Vss3, respectively, for wire bonding (L11, L22, L33). Therefore, when the output buffer is operated, the power supply noise induced at Vss1 is transmitted to the peripheral circuit supply pad P31 through the paths of L11_L12_Vss bus_L32_P31, so that the power noise of Vss1 is attenuated. In the same way, the power noise induced in Vss2 is transmitted to the peripheral circuit supply pad P31 through the path of the L21L22Vss bus L32L31P31 even during the sense amplifier operation of the cell array, thereby significantly reducing the amount of power noise of Vss2 on the peripheral circuit. Can be.
상기 제3도에 따른 본 발명의 실시예에서는 접지전압 Vss에 과하여만 설명하였으나, 전원전압 Vcc에 대하여도 제3도와 같은 방법으로 ESD보호소자용의 패드를 각각의 전원전압핀에 대하여 설치하고 이들을 해당하는 전원전압핀들에 와이어본딩시켜줌으로써, 동일한 전원잡음억제효과를 가질 수 있을 것이다.In the embodiment of the present invention according to FIG. 3, only the ground voltage Vss has been described. However, in the same way as in FIG. 3, the pad for the ESD protection device is installed on each of the power voltage pins. By wire-bonding to the power supply voltage pins, the same power supply noise suppression effect may be obtained.
상술한 바와 같이, 본 발명은 다수개의 전원핀들을 사용하는 반도체장치에서 각 전원핀에 대하여 독립된 ESD보호소자용 패드를 설치하고 해당하는 전원핀들과 상기 패드들을 각각 와이어본딩시켜줌에 의해, ESD에 대한 보호기능은 물론 전원핀간에 간섭되는 전원잡음의 영향을 감쇄시키는 효과가 있다.As described above, in the semiconductor device using a plurality of power pins, an ESD protection device pad is provided for each power pin, and the corresponding power pins and the pads are wire-bonded to protect the ESD. Function, of course, has the effect of attenuating the influence of power noise interfered between power pins.
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019920020711A KR950006983B1 (en) | 1992-11-05 | 1992-11-05 | Input protection circuit in semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019920020711A KR950006983B1 (en) | 1992-11-05 | 1992-11-05 | Input protection circuit in semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR940012596A KR940012596A (en) | 1994-06-23 |
| KR950006983B1 true KR950006983B1 (en) | 1995-06-26 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019920020711A Expired - Fee Related KR950006983B1 (en) | 1992-11-05 | 1992-11-05 | Input protection circuit in semiconductor device |
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| KR (1) | KR950006983B1 (en) |
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- 1992-11-05 KR KR1019920020711A patent/KR950006983B1/en not_active Expired - Fee Related
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| KR940012596A (en) | 1994-06-23 |
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St.27 status event code: A-5-5-R10-R13-asn-PN2301 St.27 status event code: A-5-5-R10-R11-asn-PN2301 |
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| R18-X000 | Changes to party contact information recorded |
St.27 status event code: A-5-5-R10-R18-oth-X000 |
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| P22-X000 | Classification modified |
St.27 status event code: A-4-4-P10-P22-nap-X000 |
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| P22-X000 | Classification modified |
St.27 status event code: A-4-4-P10-P22-nap-X000 |