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KR950006837Y1 - Out lead surface exposed semiconductor package - Google Patents

Out lead surface exposed semiconductor package Download PDF

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Publication number
KR950006837Y1
KR950006837Y1 KR92022707U KR920022707U KR950006837Y1 KR 950006837 Y1 KR950006837 Y1 KR 950006837Y1 KR 92022707 U KR92022707 U KR 92022707U KR 920022707 U KR920022707 U KR 920022707U KR 950006837 Y1 KR950006837 Y1 KR 950006837Y1
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South Korea
Prior art keywords
package
semiconductor package
lead
exposed semiconductor
outlead
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Expired - Fee Related
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KR92022707U
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KR940013677U (en
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안희영
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문정환
금성일렉트론 주식회사
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Priority to KR92022707U priority Critical patent/KR950006837Y1/en
Priority to DE19934339174 priority patent/DE4339174A1/en
Priority to JP28677393A priority patent/JPH06209056A/en
Priority to TW085208401U priority patent/TW303984U/en
Publication of KR940013677U publication Critical patent/KR940013677U/en
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Publication of KR950006837Y1 publication Critical patent/KR950006837Y1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01068—Erbium [Er]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

내용 없음.No content.

Description

아웃리드 표면 노출형 반도체 패키지Out lead surface exposed semiconductor package

제1a,b도는 종래 표면 실장형 반도체 패키지의 실장 상태를 도시한 도면으로서, a도는 측단면도이고, b도는 정면도이다.1A and 1B show a mounting state of a conventional surface mount semiconductor package, in which a is a side cross-sectional view and b is a front view.

제2a,b도는 본 고안에 의한 아웃리드 표면 노출형 반도체 패키지의 구조를 보인 도면으로서, a도는 측단면도이고, b도는 a도의 저면도이다.2A and 2B are views showing the structure of an out-lead surface exposed semiconductor package according to the present invention, in which a is a side cross-sectional view and b is a bottom view of a.

제3도는 본 고안 아웃리드 표면 노출형 반도체 패키지의 표면 실장 상태를 보인 측면도.3 is a side view showing a surface mounted state of the inventive out-lead surface exposed semiconductor package.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

11 : 패키지몸체 11a : 상부몸체11: Package Body 11a: Upper Body

11b : 하부몸체 12 : 아웃리드11b: lower body 12: out lead

13 : 기판 14 : 솔더범프13 substrate 14 solder bump

본 고안은 표면 실장형 반도체 패키지의 외관구조에 관한 것으로, 특히 아웃리드를 패키지몸체의 양외측으로 돌출시키지 않고 패키지몸체의 표면(하면 양측)에 노출시킴으로써 기판 실장후의 두께를 낮추고 아웃리드의 변형에 의한 페일(Fail)을 방지하도록 한 아웃리드 표면 노출형 반도체 패키지에 관한 것이다.The present invention relates to a surface structure of a surface-mount semiconductor package, and in particular, the outlead is exposed to the surface of the package body (both lower side) without protruding to both sides of the package body, thereby lowering the thickness after mounting the substrate and deforming the outlead. The present invention relates to an out-lead surface exposed semiconductor package designed to prevent a failure caused by a defect.

일반적으로 표면 실장형 반도체 패키지는 제1a, b도에 도시한 바와같이, 패키지몸체(1)의 양외측으로 돌출된 복수개의 아웃리드(2)들을 기판(3)에 형성된 메탈라인에 일치시켜 솔더(4)를 이용 리플로워 솔더링 하는 것에 의하여 실장하도록 구성되어 있다.In general, a surface-mount semiconductor package is soldered by matching a plurality of outleads 2 protruding outwardly of the package body 1 to the metal lines formed on the substrate 3, as shown in FIGS. It is comprised so that it may be mounted by reflow soldering using (4).

도면에서 미설명 부호 5는 반도체칩을 보인 것이고, 6은 리드 프레임의 패들을 보인 것이며, 7은 상기 패들(6)에 탑재된 반도체칩(5)과 리드프레임의 인너리드(8)를 전기적으로 접속연결하기 위한 골드와이어를 보인 것이다.In the drawing, reference numeral 5 denotes a semiconductor chip, 6 denotes a paddle of a lead frame, and 7 denotes an electrical connection between the semiconductor chip 5 mounted on the paddle 6 and the inner lead 8 of the lead frame. It shows the gold wire for connecting.

그러나, 상기한 바와같은 구조를 갖는 종래의 표면 실장형 패키지는 제1a도에서와 같이, 실장 후 패키지몸체(1)와 기판(3)간에 소정높이의 갭(Gap)(t)이 형성되어 실장 후 패키지의 높이가 커지게 되고, 씬패키지(Thin package) 다핀의 경우에는 리드의 변형 및 리드편평도의 문제로 실장페일(Fail)이 발생되는 단점이 있었다.However, in the conventional surface mount package having the structure as described above, as shown in FIG. 1A, a gap Gt t having a predetermined height is formed between the package body 1 and the substrate 3 after mounting. After the height of the package becomes large, the thin package (Thin package) has a disadvantage in that the failure (Fail) occurs due to the deformation of the lead and the problem of the flatness of the lead.

이를 감안하여 안출한 본 고안의 목적은 기판에 솔더링되는 아웃리드들을 패키지몸체의 양외측으로 돌출시키지 않고 패키지몸체의 표면(하면 양측)에 노출시킴으로써 실장후의 패키지 높이를 낮추고, 취급을 용이하게 함과 아울러 아웃리드의 변형 리드 편평도 문제를 일소하여 아웃리드들의 변형에 의한 실장페일을 방지하도록 한 아웃리드 표면 노출형 반도체 패키지를 제공함에 있다.In view of this, the object of the present invention is to reduce the package height after mounting and facilitate handling by exposing the outleads soldered to the substrate to the surface (bottom side) of the package body without protruding to both sides of the package body. In addition, the present invention provides an outlead surface exposed semiconductor package which eliminates the problem of flattened lead flatness of the outlead and prevents the mounting failure due to the deformation of the outlead.

상기와 같은 본 고안의 목적을 달성하기 위하여, 표면 실장형 반도체 패키지를 구성함에 있어서, 패키지몸체의 상부크기를 하부 크기보다 크게하여 상부몸체의 양측 하면으로 다수개의 아웃리드를 노출시켜 구성함을 특징으로 하는 아웃리드 표면 노출형 반도체 패키지가 제공된다.In order to achieve the object of the present invention as described above, in constructing a surface-mount semiconductor package, the upper size of the package body is larger than the lower size to expose a plurality of outleads on both sides of the lower surface of the upper body. An outlead surface exposed semiconductor package is provided.

상기와 같이된 본 고안 아웃리드 표면 노출형 반도체 패키지를 실장함에 있어서는 실장기판에 소정높이로 다수개의 솔더범프를 형성하여 배열하고, 이 솔더범프에 패키지의 아웃리드들을 일치시켜 리플로워 솔더링하는 것에 의하여 실장된다.In mounting the inventive out-lead surface-exposed semiconductor package as described above, a plurality of solder bumps are formed and arranged at a predetermined height on a mounting substrate, and by reflow soldering by matching the outleads of the package to the solder bumps. It is mounted.

따라서 실장후의 패키지 높이가 종래에 비해 낮아지고, 아웃리드가 돌출되지 않으므로 리드변형 및 피드편평도 문제를 해소함으로써 리드변형에 의한 실장페일을 방지할 수 있으며, 제조시 포밍공정을 배제할 수 있는 등 제조공정이 간소화되고, 패키지의 취급(Handling)이 간편하다는 등의 효과가 기대된다.Therefore, the package height after mounting is lower than in the past, and the outlead does not protrude, thereby eliminating the problem of lead deformation and feed flatness, thereby preventing mounting failure due to lead deformation, and eliminating the forming process during manufacturing. The effect is that the process is simplified and the handling of the package is simple.

이하, 상기한 바와같은 본 고안에 의한 아웃리드 표면 노출형 반도체 패키지를 첨부도면에 도시한 실시예를 따라서 상세히 설명한다.Hereinafter, the outlead surface exposed semiconductor package according to the present invention as described above will be described in detail with reference to the embodiment shown in the accompanying drawings.

제2a, b도는 본 고안 아웃리드 표면 노출형 반도체 패키지의 구조를 보인 측단면도 및 제2a도의 저면도이고, 제3도는 본 고안 반도체 패키지의 실장 형태를 보인 측단면도로서 이에 도시한 바와같이, 본 고안에 의한 아웃리드 표면 노출형 반도체 패키지는 패키지몸체(11)의 상, 하부(11a)(11b)크기를 달리하여 그 상, 하부 몸체(11a)(11b)의 크기 차이로 인하여 형성되는 상부몸체(11)의 양측 하면으로 다수개의 아웃리드(12)를 노출시켜 구성함을 특징으로 하고 있다. 즉 패키지몸체(11)의 상부(11a)크기를 하부(11b)크기보다 소정폭(W)만큼 크게하여 그 폭(W)에 의해 형성된 상부몸체(11a)의 양측 하면으로 기판(13)에 접속되는 다수개의 아웃리드(12)를 노출시켜 구성한 것이다.2A and 2B are a side cross-sectional view showing the structure of the inventive out-lead surface-exposed semiconductor package and a bottom view of FIG. 2A, and FIG. 3 is a side cross-sectional view showing the mounting form of the semiconductor package of the present invention. The outlead surface exposed semiconductor package according to the present invention has an upper body formed by the size difference between the upper and lower bodies 11a and 11b of the package body 11 and the upper and lower bodies 11a and 11b. A plurality of out leads 12 are exposed on both lower surfaces of (11). That is, the size of the upper portion 11a of the package body 11 is larger than the lower portion 11b by a predetermined width W, and connected to the substrate 13 on both lower surfaces of the upper body 11a formed by the width W. A plurality of outleads 12 are exposed.

도면에서 미설명 부호 15는 반도체칩, 16은 패들, 17은 금속와이어를 보인 것이다.In the drawings, reference numeral 15 denotes a semiconductor chip, 16 paddles, and 17 a metal wire.

이와같이된 본 고안 아웃리드 표면 노출형 반도체 패키지를 기판에 실장함에 있어서는 제3도에 도시한 바와같이, 기판(13)에 다수개의 솔더범프(14)를 형성하여 배열하고, 이 솔더범프(14)에 패키지의 아웃리드(12)들을 각각 대응하도록 일치시켜 리플로워 솔더링하는 것에 의하여 실장하게 된다.In mounting the present invention designed out-lead surface-exposed semiconductor package on a substrate, as shown in FIG. 3, a plurality of solder bumps 14 are formed on the substrate 13, and the solder bumps 14 are arranged. In this case, the outleads 12 of the package are respectively matched to correspond to each other, thereby reflow soldering.

따라서, 실장후의 패키지 높이가 종래에 비해 낮아지는 것이다.Therefore, the package height after mounting becomes low compared with the past.

이상에서 상세히 설명한 바와같이, 본 고안에 의한 아웃리드 표면 실장형 반도체 패키지는 기판에 실장되는 아웃리드가 패키지 몸체의 표면으로 노출되므로 실장후 패키지의 높이가 종래에 비해 낮아지고, 아웃리드가 패키지몸체의 외측으로 돌출되지 않으므로 패키지의 취급이 간편할 뿐만아니라 리드변형 및 리드편평도 문제를 일소함으로써 리드변형에 의한 실장페일(Fail)를 방지할 수 있으며, 제조시에도 포밍공정을 배제할 수 있으므로 제조공정이 간소화되는 효과가 있고 아울러 리드프레임의 재료 절감을 도모하는 효과도 있다.As described in detail above, the outlead surface mounted semiconductor package according to the present invention is exposed to the surface of the package body of the outlead mounted on the substrate, so that the height of the package after mounting is lower than in the prior art, the outlead package body Since it does not protrude to the outside of the package, handling of the package is simple, and the lead deformation and lead flatness problems can be eliminated to prevent mounting failure due to the lead deformation, and the forming process can be eliminated during manufacturing. This has the effect of being simplified, and also has the effect of reducing the material of the leadframe.

Claims (1)

표면 실장형 반도체 패키지를 구성함에 있어서, 패키지몸체(11)의 상부(11a) 크기를 하부(11b) 크기보다 소정폭(W)만큼 크게하여 그 폭(W)에 의해 형성된 상부몸체(11a)의 양측 하면으로 기판(13)에 접속되는 다수개의 아웃리드(12)를 노출시켜 구성함을 특징으로 하는 아웃리드 표면 노출형 반도체 패키지.In constructing the surface mount semiconductor package, the upper body 11a of the package body 11 is made larger by the predetermined width W than the lower body 11b so that the upper body 11a formed by the width W of the package body 11 is formed. An outlead surface-exposed semiconductor package characterized by exposing a plurality of outleads 12 connected to the substrate 13 on both lower surfaces thereof.
KR92022707U 1992-11-18 1992-11-18 Out lead surface exposed semiconductor package Expired - Fee Related KR950006837Y1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR92022707U KR950006837Y1 (en) 1992-11-18 1992-11-18 Out lead surface exposed semiconductor package
DE19934339174 DE4339174A1 (en) 1992-11-18 1993-11-16 Semiconductor housing with exposed connection elements - has upper section of housing body wider than lower section to expose inner connections on both side sections of lower surface of upper section
JP28677393A JPH06209056A (en) 1992-11-18 1993-11-16 Semiconductor package with surface exposed leads
TW085208401U TW303984U (en) 1992-11-18 1993-11-18 Semiconductor package having surface-exposing leads

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR92022707U KR950006837Y1 (en) 1992-11-18 1992-11-18 Out lead surface exposed semiconductor package

Publications (2)

Publication Number Publication Date
KR940013677U KR940013677U (en) 1994-06-25
KR950006837Y1 true KR950006837Y1 (en) 1995-08-21

Family

ID=19344201

Family Applications (1)

Application Number Title Priority Date Filing Date
KR92022707U Expired - Fee Related KR950006837Y1 (en) 1992-11-18 1992-11-18 Out lead surface exposed semiconductor package

Country Status (4)

Country Link
JP (1) JPH06209056A (en)
KR (1) KR950006837Y1 (en)
DE (1) DE4339174A1 (en)
TW (1) TW303984U (en)

Also Published As

Publication number Publication date
DE4339174A1 (en) 1994-06-09
KR940013677U (en) 1994-06-25
JPH06209056A (en) 1994-07-26
TW303984U (en) 1997-04-21

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