KR950005643B1 - Packet switch - Google Patents

Abstract

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Description

Packet switch

1 is a schematic diagram showing the basic form of the packet-switching apparatus of the present invention.

2 is an equivalent circuit diagram of FIG.

3 is a schematic diagram showing the basic configuration of Octopus 2 in FIG.

4 is a circuit diagram showing the internal connection of Octopus.

5 is a functional block diagram showing the operation principle of the receiver and transmitter in FIG.

6 is a detailed block diagram of the transmitter of FIG. 3;

7 is a detailed block diagram of the receiver of FIG. 3;

* Explanation of symbols for main parts of the drawings

1-8, C: Octopus 10: Receiver

20: transmitting unit 101: serial / parallel converter

102: scheduler and micro command decoder 103: decoder

104: error correction table 105: encoder

106: call information table 107: direction decoder

108: frame module 109: leg selector

201-208: Thermal buffer 211: Dynamic buffer manager

212: useful block space address unit 213: output buffer

214: data preparation block address unit 215: packet pulse generator

216: data ejector N: nozzle

L ₁ -L ₈ : Leg

The present invention relates to a packet switching apparatus for dividing transmission information into packet types and transmitting in an Anynchronous Transfer Mode (ATM), and is particularly suitable for any type of application service provided by the switching apparatus. It is a generic switch architecture that can perform its functions even under adverse conditions such as military tactical environment.It is based on the eight-line capacity. A packet switching device.

Since the study of the feasibility and feasibility began in the 1970s, the packet exchange method has been continuously developed along with the data communication market with the strong demand of users who want variable transmission band, distributed processing and distributed control. In particular, since the mid-1980s, a single integrated operation of the communication system has made numerous adjustments and has made the BISDN (Broadband Intergrated Services Digital Network) visible. The situation is accelerating the development of the packet switch of the ATM (ATM).

In general, unlike a circuit switch, a packet switch is designed in a common memory method, a common media type, and a space partitioning method.

The common memory packet switch is composed of a common memory shared by all input lines and output lines. Packets inputted from all input lines are multiplexed into one stream and delivered to the common memory for storage, and the packets are stored one by one in the output buffer inside the common memory, and at the same time, one packet is selected in each output buffer and then outputted. It is composed of a stream and transmitted to an output side, and the transmitted output stream is divided and transmitted to an output line.

However, two important design constraints must be met for this packet switch. First, the time for determining where to store the packet and the processing time for determining the appropriate control signal must be small enough to maintain the flow of the input packet. In other words, there should be a centralized controller that can process N packets and select N output packets in each slot. The second most important constraint is the allocation of a limited amount of memory.

There are three main methods of allocating this memory. First, all I / O stages share a single memory. Since the operation speed of the switch must be about N times faster than the I / O link speed, the buffer read and write Performing control at high speed is the most important problem. The second is to divide the memory into N and share several small buffers. By sharing cell buffer that can read and write in packet unit, hardware saving and relative operation speed of memory can be achieved, but the complexity of selecting cell buffer to store and relatively large buffer are needed. The disadvantage is that buffers cannot be used efficiently. Third, it operates a unique buffer as a queue, and the internal speed of the switch and the input / output operation speed are the same.When packet input, the packet information and header are separated, and the exchanged packet header and information are combined by hardware. It consists of relatively simple hardware, such as a rotary shifter and a rotary selector.

As a result, the common memory packet exchanger uses the memory in common, so the memory utilization efficiency is high and the amount of memory required is small, but the time-sharing exchange is used. It should operate at high speed N times faster.

Therefore, in order to perform such a high-speed exchange function, device technology and signal synchronization technology must be preceded, and broadcasts cause delays of other services than broadcasts. A counter that limits the quantity at a certain level and a method of increasing the internal operating speed are needed.

In addition, a common medium type packet exchanger is a device for exchanging packets using a common medium. All packets arriving at an input line are synchronously multiplexed onto a single common high speed medium, which is more than the speed of a single input line. It should have bandwidth N times faster. Each output line is connected to the bus through an interface consisting of an address filter and an output first-in, first-out (FIFO) buffer, and each interface receives all packets sent from the bus and examines the packet's output address to preempt the packet. Determines whether to send to the buffer.

Accordingly, the packet exchanger of the common medium type multiplexes all packets inputted from the input terminal into one stream and transmits them one by one to each output line.

Here, the single path through which all packets are transmitted is a divided bus in broadcasting, and the exchange is performed by an address filter in the output connection device.

However, in this device, it has to have limited bandwidth and transmission efficiency compared to the multipath switching structure, and thus, multiple rings or buses must be used in one or several hierarchical structures to increase the limited capacity.

In addition, the space-switched packet exchanger establishes several paths simultaneously between several inputs and outputs, each has the same transmission speed as the transmission line, and centralizes switching for connecting one input terminal and output terminal. It has a structure distributed to each element of the exchanger without needing to be. However, this means that if you want to set up multiple paths, but each input wants to be connected to a different output, you can't set up other calls except one if you want to use certain internal equipment in the exchange equipment at the same time. This phenomenon is called internal blocking, which limits the performance of the switch. Therefore, buffering must be done to prevent blocking of the call, and the buffer must be located at the internal device or input stage due to the possibility of internal blocking. Where to put such a buffer will have a significant impact on the performance and hardware implementation of the space split exchange.

In addition, the packet switch of each method as described above has been developed for the purpose of error-free communication in a communication environment that guarantees a cell loss rate of 10 ^-9 or less recommended by the CCITT. Therefore, a new concept of switch structure should be developed for the communication environment that does not meet the BISDN conditions.

In particular, even in the field of military communication where tacticality is required, various demands for high quality communication services provided under a commercial communication environment have been actively developed, and individual single equipment development has been continued to satisfy such demands. As a result, the development of each equipment that was not uniform did not have many different Data Characterist (CS) and requirements, and the interface and interoperability of these equipments were always a big obstacle. Also, the recent emergence of digitalized communication equipment has made clear the limitations of interoperability and operation of analog circuit-based communication environment based on the current communication environment. The situation has been studied.

Accordingly, an object of the present invention is to provide a function suitable for any type of application service that a switch must provide, and unlike a switch of another packet switching device that requires an optimal environmental condition, it can perform its functions under adverse conditions such as military tactics environment. The present invention provides a packet switching device of a generic switch architecture.

Another object of the present invention is basically a general-purpose ATM switch fabric that is not limited to service rectification (use and speed) of the application to which the exchange is applied, and active errors to enable high-speed ATM cell processing even in a poor transmission environment. The present invention provides a packet switching device with a built-in correction function.

It is still another object of the present invention to provide a packet switching device which is composed of a basic eight-line switch fabric and can increase line capacity by three-dimensional assembling thereof.

The object of the present invention is to connect eight basic octopus having an external connection nozzle and an internal connection leg and a central octopus for redundant control through its internal connection legs, The packet data inputted by the Octopus nozzle is processed by the reception unit of the Octopus, and then its legs are selected and output.The packet data inputted by the Octopus leg is processed by the Octopus transmitter and processed and transmitted to his nozzle. This is achieved by the following description in detail with reference to the accompanying drawings.

1 is a schematic diagram showing the basic form of an 8-line packet switching apparatus of the present invention. As shown therein, eight basic octopus 1-8, which is a buffering element, and a central octopus C for redundant control are internally shown. Is connected so that packet data can be transmitted and received between the octopus 1-8 and C. Therefore, it is possible to process port data in units of at least 1 byte, which brings a huge advantage in handling data. Also, it is possible to control a switching system using a high-speed compact microcontroller, making it easier and more economical to implement a system. You lose.

FIG. 2 is an equivalent circuit diagram of FIG. 1, and as shown therein, each octopus 1-8, C has one nozzle N connected to an external user terminal or other exchanger and its octopus 1-. It has eight legs (L _1- L ₈ ) which are connected internally between 8 and C, and the packet inputted to the nozzle N of each octopus (1-8, C) is the octopus ( 1-8, C) after processing in the output can be also his one leg (L ₁ -L _8), the Octopus (1-8, C) packet inputted to as the leg (L ₁ -L ₈₎ is that the It is comprised so that it may output to the nozzle N after processing by the octopus 1-8 and C.

FIG. 3 is a schematic view showing the basic configuration of the second-order octopus 1-8 and C. As shown in FIG. 3, a receiver for processing a packet input to the nozzle N and outputting it to the legs L ₁ -L _{8 is} shown. And a transmitter 20 for processing the packets input to the legs L ₁ -L ₈ and outputting them to the nozzle N, wherein the packets processed by the receiver 10 are the receiver 10. Selects one or more of its legs L ₁ -L ₈ and outputs the selected legs.

Such Octopus 1-8 and C have the same structure in terms of hardware and software, are independent of each other in operation and function, and the nine Octopus 1-8 and C are combined to form a unit exchange element. Technical system transplantation of characteristic and function change can be done in Octopus unit, and performance improvement is simplified after establishing and establishing the whole communication network.

4 is a circuit diagram showing the internal connection state of the octopus (1-8, C) in FIG. 2, and as shown in FIG. 4, the number of the octopus (C, 1-8) is m, and the values from 0 to 8 are respectively shown. Assign the leg (L ₁ -L ₈ ) number of each octopus (C, 1-8) to n, and assign each value up to 1-8, and then apply the leg (m, n) to the nth leg of the mth octopus. In this case, 1 <m, n <7, and if the leg (m, n) is connected to the leg (n, m) under the condition n = n, internal connection between the octopus (1-8) is made, and m = When legs (0, n) are connected to legs (n, n) under the condition of 0, 1 <n <7, internal connection between the octopus 1-8 and the central octopus C is made.

That is, the legs (L ₂ ), (L ₃ ), (L ₄ ), (L ₅ ), (L ₆ ), (L ₇ ), and (L ₈ ) of the octopus ( ₁ ) octopus corresponding to the leg number. Legs (L ₁ ), (L ₁ ), (L ₁ ), (L ₁ ), (2), (3), (4), (5), (6), (7), (8) L ₁ ), (L ₁ ), and (L ₁ ), respectively, and the legs of the octopus (2) (L ₁ ), (L ₃ ), (L ₄ ), (L ₅ ), (L ₆ ), ( L _7), (Octopus 1, 3, 4, 5, 6, and 7, the legs of the (8) (L ₂₎ corresponding to L ₈₎ in the leg number, (L ₂ ), (L ₂ ), (L ₂ ), (L ₂ ), (L ₂ ), and (L ₂ ), respectively, and in this way, the octopus (1-8) is connected to each other, Internal wiring between 1-8) is made.

Also, (L ₁ ), (L ₂ ), (L ₃ ), (L ₄ ), (L ₅ ), (L ₆ ), (L ₇ ), and (L ₈ ) of the central octopus (C). Legs (L ₁ ), (L) corresponding to leg numbers in octopus (1), (2), (3), (4), (5), (6), (7), and (8) ₂ ), between (L ₃ ), (L ₄ ), (L ₅ ), (L ₆ ), (L ₇ ) and (L ₈ ), respectively, between the octopus (1-8) and the central octopus (C). Internal wiring is done.

Octopus 1-8, C, which is connected in this way, only needs to transmit the packet data in its own leg, such as the number of another Octopus, in order to exchange the packet data received from the other Octopus. For example, in order to transmit the packet data received by the octopus 1 to the octopus 2, the packet data may be transmitted to its own leg L ₂ corresponding to the number of the octopus 2.

In addition, since the octopus 1-8, C is a kind of multiplexer, the multiplexer terminals are connected to each other to have an exchange function.

(A) of FIG. 5 is a functional block diagram showing the operation principle of the receiver 10 of FIG. 3. As shown in FIG. 5, the packet data input to the nozzle N is input from the receiving processor 11. The basic format of the processed packet consists of one octet-size error correction field data, four octets of header data, and 48 octets of payload data. The header of the data is converted into the address of the call information table 13 using the error correction table 12, and the header of the packet data is subsequently received using the call information table 13 based on the value. It is made of a header that represents Octopus, and is then transmitted to the corresponding leg among his legs (L ₁ -L ₈ ). In this case, since the processing is different for each packet type, the receiving processor 11 codes the software using the microprogram concept, stores the coded data in the microprogram memory 13, and then codes the codes according to the order. Will process the packet.

FIG. 5B is a functional block diagram showing the operation principle of the transmitter 3 of FIG. 3. As shown in FIG. ₅ , the transmitter processor 21 transmits the packet data input through the legs L _{1 to} L ₈ . After receiving the data, the buffer 22 is stored in the buffer memory 22 and output to the nozzle N in order.

By the way, the transmitter 2 and the receiver 10 are regarded as completely independent even if they are in the same number of octopus, and the transmitter 20 and the receiver 10 should be independently operated to be designed in one chip. There is no need.

FIG. 6 is a detailed block diagram of the receiver of FIG. 3, and the serial / parallel converter 100 converts serial packet data, which is input in bytes through the nozzle N, into parallel packet data as shown in FIG. ), A scheduler and a micro command decoder 102 that receives the output data of the serial / parallel converter 101 and performs a schedule and a micro instruction, and the serial / parallel converter 101 A decoder 103 for decoding the packet header data among the output packet data, an error correction table 104 whose address is designated by the output data of the decoder 103, and error decoding data is output, and the error correction table ( An encoder 105 for encoding the error decoding data of 104), and a call information table for addressing bytes in units of bytes by the output data of the encoder 105 to output header data and output leg data. Control unit 106 and the header data output from the call information table 106 under the control of the scheduler and the micro-command decoder 102 and the fade output from the serial / parallel converter 101. Directional decoder to decode the output leg data output from the call information table 106 under the control of the framing module 108 and the scheduler and the micro-command decoder 102 to add the payload data in the form of a packet ( 107 and one of the legs L ₁ -L ₈ is selected according to the output signal of the direction decoder 107, and the leg selector 109 for outputting the packet data of the framing module 108 to the selected leg. It consists of.

The packet data inputted to the nozzle N is composed of one byte of error correction determination field data, four bytes of header data, and 48 bytes of payload data, and constitutes a total of 53 bytes.

FIG. 7 is a detailed block diagram of the transmitter of FIG. 3, and as shown therein, packet data input through the legs L _{1 to} L ₈ are sequentially stored and stored by the data ready intercept signal DRI. A queue buffer 201-208 to be sequentially outputted, and the output packet data of the column buffer 201-208 are inputted through a designated useful block address of the available block space address unit 212. An output buffer 213 sequentially storing each block (BLK ₁ -BLK ₈ ) in a FCFS (First Come First Derved) method, and the useful block space address unit 212 by checking the state of the output buffer 213. The dynamic buffer manager 211 which detects the absence of an output packet and outputs the detection signal by allocating a block address to the block block, assigns an output block address to the output block address, and outputs the output block address of the dynamic buffer manager 211. Data preparation block to output block selection address A packet pulse generator 215 for generating and outputting a dummy packet by an address packet 214, an output packet-free detection signal of the dynamic buffer manager 211, and the data preparation block address unit 214. According to the output block selection address, the blocks BLK _{1 to} BLK ₈ of the output buffer 213 are selected, the packet data of the selected block is output to the nozzle N, and the dummy pulse packet is generated by the packet pulse generator 215. The dummy packet is outputted to the data ejector 216 which outputs the dummy packet to the nozzle N when it is output.

The operation of the receiver 10 and the transmitter 20 configured as described above will be described in detail as follows.

Serial packet data input in units of bytes through the nozzle N is converted into parallel data by one byte in the serial / parallel converter 101, and applied to the scheduler and the microcommand decoder 102, and thus, serial / parallel at this time. From the error correction determination field data of the first byte of the packet data output from the converter 101, it is determined whether an error correction request is required. In this case, if the packet data has an error correction request, the packet data output from the serial / parallel converter 101 is determined. The packet header data from the second byte to the fifth byte is decoded by the decoder 103 in byte units to designate an address of the error correction table 104.

In this case, according to the 2: 1 error correction principle, 4-bit error decoded data is read in nibble units for each byte addressed, and 2 bytes of error decoded data are obtained after the entire 4-byte header is addressed. Is generated. In this process, header 1-bit error correction and 2-bit error detection are possible. As described above, the two-byte error decoding data output from the error correction table 104 is encoded in the byte unit by the encoder 105 and then specifies the address of the call information table 106. Here, the call information table 106 records the header data of 4 bytes to be newly updated and the output leg number to which they are output.

Therefore, as the address of the call information table 106 is designated by the output data of the encoder 105, newly-encoded 4-byte header data and output leg data are output.

Therefore, the error correction determination field data, which is the first byte, the header data of 4 bytes output from the call information data 106, and the payload data of 48 bytes output from the serial / parallel converter 101 thereafter are the scheduler and the micro command decoder. Under the control of 102, the framing module 108 sums and outputs the packet in the form of a 53-byte packet frame.

At this time, the output leg data output from the call information table 106 is decoded by the direction decoder 107 under the control of the scheduler and the micro command decoder 102 and output as a leg selection signal. As the legs L ₁ -L ₈ of the selector 10 are selected, the packet data of the framing module 108 is output through the selected legs.

On the other hand, packet data that is output to the leg (L ₁ -L ₈₎ of the receiving unit 10 as the input to the leg (L ₁ -L ₈₎ of the sending unit 20 are each successively to the column buffer (201-208) After being stored as, it is sequentially output by the data ready interrupt signal (DRI). At this time, according to the allocation of the useful blocks of the useful block space address unit 212 in the dynamic buffer message 211 for checking the state of the output buffer 213, the packet data outputted sequentially from the thermal buffers 201 to 208 respectively. The useful block addresses are stored in the FCFS scheme in the blocks BLK _{1 to} BLK ₈ of the output buffer 213, respectively. At this time, the output block selection address is output from the data preparation block address unit 214 according to the output block address output from the dynamic buffer manager 211, and the output buffer (2) is output from the data ejector 216 according to the output block selection address. A block BLK ₁ -BLK ₈ of 213 is selected, and the packet data of the selected block is outputted to the nozzle N.

When no packet data is stored in the blocks BLK _{1 to} BLK ₈ of the output buffer 213, the dynamic buffer manager 211 detects it and outputs an output packet-free detection signal. Accordingly, the packet pulse generator After the dummy packet is generated at 215, the dummy packet is output to the nozzle N through the data ejector 216. Here, the pulse generation period of the dummy packet is determined in proportion to the stability of the system clock, and if the output packet is not maintained until a predetermined time has elapsed, a regular packet pulse occurs. And it is sent to the nozzle N. FIG.

As described in detail above, the present invention internally connects the eight basic octopus and the control central octopus to transmit packet data input through the nozzle of each octopus through another octopus, and each octopus is hardware and software. In general, it has the same structure and is independent of each other in operation and function, so it is suitable for any type of application service that a packet exchange switch must provide, and it is a general-purpose exchange structure capable of functioning in a poor transmission environment such as a military tactic environment. It is effective to become. In addition, the present invention is capable of processing the data in 1 byte unit, which is a big advantage in data handling, and the octopus is combined to form an 8-wire unit switching device, so the technical system transplantation of the network characteristics and the functional change is octopus unit. It is possible to improve the performance after construction and construction of the entire communication network, and the circuit capacity can be easily increased by three-dimensionally assembling the unit switching elements of the eight-line capacity.

Claims (7)

8 Octopus base (1-8) and the central Octopus (C) of the replacement control with the external connection nozzle (N) and the legs for the inner connection (L ₁ -L ₈₎ for each leg for its internal link (L ₁ - L ₈ ), and is configured to transmit and receive packet data between the octopus (1-8, C). The method of claim 1, wherein the base Octopus (1-8), each leg (L ₁ -L ₈₎ of their own legs for the number of the Octopus and each connected to the same number of legs of the Octopus center (C), the leg rest Is a packet switching device, characterized in that each connected to the same number leg as the own octopus number of the other octopus corresponding to the leg number. The method according to claim 1 or 2, wherein each of the octopuses 1-8 and C processes the packet data input to the nozzle N, and then selects legs L _{1 to} L ₈ to output them to the selected legs. receiver 10 and the packet switching device of each leg consisting of characterized in that to a transmission unit 20 for output to the nozzle (N) to process the packet data that is input to the (L ₁ -L _8). The receiver 10 receives the packet data input to the nozzle N, and converts the header of the packet data into the address of the call information table 13 using the error correction table 12. On the basis of the value, the header of the packet data is made into a header indicating the next receiving octopus based on the call information table 13 and then transmitted to the corresponding leg among the legs L ₁ -L ₈ . Packet switching device. The method of claim 3, wherein the transmitting unit 20 is configured to receive the packet data through the legs (L _1- L ₈ ) and to store in the buffer memory 22, and then output the nozzle (N) in order Packet Switching Device. The serial / parallel converter 101 according to claim 3, wherein the receiver 10 converts serial packet data input in units of bytes through the nozzle N into parallel packet data, and the serial / parallel converter 101. A scheduler and a micro-command decoder 102 for receiving DML output data and performing a schedule and a micro-command, and a decoder 103 for decoding header data of the packet data output from the serial / parallel converter 101, An error correction table 104 addressed by the output data of the decoder 103 and outputting error decoding data, an encoder 105 for encoding the error decoding data of the error correction table 104, and the encoder ( The call information table 106 is designated in byte units by the output data of 105 to output the header data and the output leg data, and the control of the scheduler and the micro command decoder 102 is performed. The framing module 108 for adding the header data output from the call information table 106, the error correction judgment field data, and the payload data output from the serial / parallel converter 101 in packet form, and the scheduler. And a direction decoder 107 which decodes the output leg data output from the call information table 106 under the control of the microcommand decoder 102 and a leg L ₁ -according to the output signal of the direction decoder 107. L ₈ ) and a leg selector (109) for outputting packet data of the framing module (108) to the selected leg. 4. The thermal buffer 201 of claim 3, wherein the transmitter 20 sequentially stores packet data input through the legs L _{1 to} L ₈ and sequentially outputs the data by the data ready interrupt signal DRI. And an output buffer which receives the output packet data of the thermal buffers 201-208 through the designated useful block address of the useful block ox address unit 212 and stores them sequentially in each block L _1- L ₈ . 213 and a dynamic buffer manager which checks the state of the output buffer 213, allocates a block address to the useful block space address unit 212, allocates an output block address, and outputs an output packet-free detection signal. 211, a data preparation block address unit 214 for outputting an output block selection address in accordance with the output block address of the dynamic buffer manager 211, and an output packet non-detection signal of the dynamic buffer manager 211. Dummy packet generated and printed By selecting the kit pulse generator 215 and a block (L ₁ -L ₈₎ of the output buffer 213 according to the output selection block address of the block address data preparing section 214, the packet data of the selected block And a data ejector (216) for outputting to the nozzle (N) and outputting the dummy packet to the nozzle (N) when the dummy packet is output from the packet pulse generator (215).