KR950004561B1 - Flash write circuit of semiconductor memory device - Google Patents

Abstract

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Description

Flash write circuit of semiconductor memory device

1 is a functional block diagram of a general video RAM.

2 is a flashlight circuit diagram according to the prior art.

3 is an operation timing diagram of FIG. 2.

4 is a flashlight circuit diagram according to the present invention.

5 is an operation timing diagram of FIG.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices, and more particularly to a flash write circuit for resetting data stored in the memory device.

Today, semiconductor memory devices are rapidly expanding in their use. In addition, new memory devices have been developed to meet the needs of users. Among them, the most rapidly developing field is the field of Dynamic Random Access Memory (DRA M). As a memory device using the DRAM, there is a video RAM, which is an image-only memory device. The video RAM is a single chip by adding a serial access memory (SAM) having a function of a shift register to a general DRAM. When the video RAM is operated, image data is stored in the DRAM and serially output using the SAM.

Among the functions of the video RAM, the flash write mode has been very usefully used as a function for resetting data stored in a DRAM memory cell used as a memory device. The flashlight mode is one time This function resets the data stored in all memory cells connected to one word line in a cycle. This feature has a powerful effect on the resetting of multiple column bitlines in the case of video RAMs that must process large amounts of data at the same time. Since the flash write mode is a function corresponding to a write operation of a memory cell, the flash write mode is performed using a circuit necessary for the write mode.

1 is a functional block of a general video RAM. 1 is composed of a DRAM, which is a data storage means, and means for serially inputting and outputting the data. DSF, which is one of the control signals in FIG. 1, is a special function control signal, and generates the flashlight operation signal using the DSF signal.

2 is a flashlight circuit according to the prior art. 2 (a) is a flashlight circuit diagram of the prior art. The circuit of FIG. 2 (a) includes an address input buffer stage 20 for inputting a column address, a FLW signal for performing a flashlight operation, a column decoder 21 for decoding the address and the FLW signal, and the decoded signal. The input / output gate 22 connects the data bit line with the input / output terminal 23 by an address. FIG. 2 (b) shows an example of the configuration of the column address buffer stage. The column addresses Ai (i = 1 to n) are combined with the flashlight signal FLW to give CAi and Generates. At this time, when the FLW signal is "high", the CAi and Are all “high”. Figure 2 (c) is an embodiment of the column decoder. The circuit of FIG. 2 (c) is an embodiment for decoding only two column addresses A ₀ , A ₁ . In an actual column decoder, the decoding method as shown in FIG. 2 (c) is continuously performed, resulting in a more complicated circuit. 3 is an operation timing diagram of FIG. 2. The operation of FIG. 2 will be described with reference to FIG. 3. As shown in FIG. 3 (a), when the control signal DSF is not enabled as "high", the flashlight signal FLW remains "low". At this time, as shown in FIG. 3 (b), the column decoder 21 performs normal column address decoding. But low strobe signal When the control signal DSF is triggered “high” after is enabled, the flash write signal FLW is enabled “high”. At this time, as shown in FIG. 3 (c), the output CAi of the buffer stage 20 which receives the flashlight signal and The outputs of are all "high". Accordingly, all of the input / output gates 22 of FIG. 2 (a) are turned on, and predetermined data is loaded on bit lines connected to the input / output gate through the input / output gate 22. Therefore, all of the memory cells connected to the selected word line are subjected to a flash write operation in which genital predetermined data is stored.

However, in the conventional flashlight circuit shown in FIG. 2, since the flashlight signal is input to the front end of the decoder, t shown in FIG. 3 (c) by the delay stage of the column decoder 21 is shown. A time delay of _d will occur. This time delay may cause a malfunction in the write operation of the memory chip. In other words, in order to perform a flash write operation on the memory cells at a time, a write margin must be large. If the write margin is small, a large overload occurs in the bit line driver, thereby increasing the possibility of malfunction. Therefore, in order to solve the problem, during the flash write operation, the path of the flash write signal should be shortened so that the write operation can be performed quickly by focusing on the time delay. Also, in FIG. 2 of the prior art, since the flashlight signal is connected to the front end of the column decoder 21, a configuration for combining the column address with the flashlight signal is required. Therefore, the configuration of the column address input buffer stage is complicated.

Accordingly, an object of the present invention is to provide a flashlight flashlight circuit with increased light margin.

Another object of the present invention is to provide a flashlight circuit which is easy to control.

The present invention for achieving the above object is to provide a flashlight circuit by increasing the light margin by shortening the path of the flashlight signal by applying the flashlight signal to the input / output gate.

4 is a flashlight circuit according to the present invention. 4 (a) shows an address input buffer 30 for inputting a column address, a column decoder 21 for decoding the column address, and a logic gate circuit for combining the decoded column address and the flashlight signal FLW ( 31), a data input / output terminal 23 for inputting / outputting data to the bit line, and an input for controlling the output of the logic gate circuit 31 to block the bit line and the data input / output terminal 23. / Output gate 22. 4 (b) shows an embodiment of the address buffer stage 30 shown in FIG. 4 (a). 4 (c) is a circuit for decoding only two column addresses A ₀ and A ₁ as in FIG. 3 (c) as an example of the column decoder 21 of FIG. 4 (a). In an actual column decoder, the decoding method as shown in FIG. 2 (c) is performed continuously, resulting in a more complicated circuit. 4 (d) is an embodiment of the logic gate circuit 31 shown in FIG. 4 (a). 4 (d) shows the output DCAi / of the column decoder 21. The control signal of the input / output gate 22 is generated by the logical sum of the flashlight signal FLW. 5 is an operation timing diagram of FIG. An operation of FIG. 4 will be described with reference to FIG. 5. The column address decoded by the column decoder 21 and the flash write signal FLW are connected to a gate terminal of the input / output gate 22 through a logic gate circuit 31. When the flashlight signal FLW is " low ", as shown in Fig. 5A, the column decoder 21 performs normal column address decoding. However, when the flash write signal FLW is enabled as "high", as shown in FIG. 5 (b), the outputs of the logic gate circuit 31 are all high. Therefore, the input / output gates 22 are all turned on. In this case, a bit line in which predetermined data (eg, “high” or “low” data) of the input / output terminal 23 is connected to the input / output gate 22 through the input / output gate 22. Supplied to. At the same time, the flash write operation is performed on the memory cells connected to the selected word line.

In the flashlight circuit of FIG. 4 according to the present invention, the flashlight signal is applied to the rear end of the column decoder 21 to control the input / output gate. Therefore, in the prior art of FIG. 2, the delay time problem at the column decoder 21 generated because the flashlight signal is connected to the column address buffer stage 20 is greatly reduced. In the flashlight circuit of FIG. 4 according to the present invention, since the output of the column decoder 21 and the flashlight signal are controlled using the logic gate circuit 31, the flashlight circuit of FIG. It's much simpler to control.

As described above, in the flashlight circuit according to the present invention, the flashlight signal is combined by using the decoding address of the column decoder and the logic sum gate circuit, and the input / output gate is controlled by the output of the logic sum gate circuit, thereby performing flashlight operation. The present invention provides a flashlight circuit that greatly reduces the time time delay and increases the light margin, and facilitates control of the flashlight operation.

Claims (5)

A memory cell array having a plurality of row addresses and column addresses, arranged in a matrix of a plurality of word lines and data bit lines, and first selection means for receiving the column addresses and selecting the data bit lines And second selection means for selectively activating the word line by receiving the row address, an input / output terminal for inputting or outputting data to the plurality of data bit lines, the input / output terminal and the plurality of data bits. A semiconductor memory device having a plurality of switch means connected between lines and controlled to an output of said first selection means, said semiconductor memory device comprising: a connection between said first selection means and a control terminal of said switch means and stored in said memory cell; Further comprising control means for selectively resetting the data. The semiconductor memory device according to. 2. The apparatus of claim 1, wherein the control means receives a flashlight signal, inputs a plurality of outputs of the first selection means to each first terminal, and inputs the flashlight signal to each second terminal, And a logic gate circuit for activating the switch means when any one of an input of the first terminal and the second terminal is activated. The semiconductor memory device according to claim 1, wherein said switch means is an N-MOS transistor whose output is connected to a gate thereof. The semiconductor memory device of claim 2, wherein the flashlight signal is a signal generated inside the memory device in synchronization with a flashlight mode signal applied from the outside of the memory device. 3. The logic gate circuit of claim 2, wherein the logic gate circuit comprises: a NOR logic gate for inputting the output of the first selection means to a first terminal and the control signal to a second terminal; and an inverter for inverting the output of the NOR logic gate. A semiconductor memory device, characterized in that consisting of.