KR950002204B1 - Making method of diode for protecting circuit - Google Patents
Making method of diode for protecting circuit Download PDFInfo
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- KR950002204B1 KR950002204B1 KR1019920012903A KR920012903A KR950002204B1 KR 950002204 B1 KR950002204 B1 KR 950002204B1 KR 1019920012903 A KR1019920012903 A KR 1019920012903A KR 920012903 A KR920012903 A KR 920012903A KR 950002204 B1 KR950002204 B1 KR 950002204B1
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- diode
- impurity region
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
- H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
- H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
- H10D89/611—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using diodes as protective elements
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/201—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits
- H10D84/204—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits of combinations of diodes or capacitors or resistors
- H10D84/221—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits of combinations of diodes or capacitors or resistors of only diodes
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- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
내용 없음.No content.
Description
제 1 도는 일반적인 입력보호 회로도.1 is a general input protection circuit diagram.
제 2 도는 일반적인 출력보호 회로도.2 is a general output protection circuit diagram.
제 3 도는 종래 보호회로의 제 1 다이오드 단면 및 평면도.3 is a cross-sectional view and a plan view of a first diode of a conventional protection circuit.
제 4 도는 종래 보호회로의 제 2 다이오드 단면 및 평면도.4 is a cross-sectional view and a plan view of a second diode of a conventional protection circuit.
제 5 도는 본 발명 실시예의 보호회로의 다이오드 공정단면도.5 is a cross-sectional view of a diode process of a protection circuit of an embodiment of the present invention.
제 6 도는 본 발명 실시예의 보호회로의 다이오드 단면 및 평면도.6 is a cross-sectional view and a plan view of a diode of the protection circuit of the embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1,1a : 웰 2 : 필드산화막1,1a: well 2: field oxide film
3 : 산화막 3a : 절연막3: oxide film 3a: insulating film
4 : 폴리실리콘 5 : 마스크4: polysilicon 5: mask
6 : n형 폴리실리콘 7 : P 형 폴리실리콘6: n-type polysilicon 7: P-type polysilicon
8 : 전극8: electrode
본 발명은 반도체 소자 제조방법에 관한 것으로, 특히, ESD(Electro Static Discharge)개선 및 고집적화에 적당한 보호회로의 다이오드 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a diode of a protection circuit suitable for improving electrostatic discharge (ESD) and high integration.
일반적인 보호회로는 반도체 소자를 외부의 정전기 등으로부터 보호하기 위한 것으로, 제1도 및 제2도와 같이 다이오드(D1-D2), 저항(R1), MOS(Q1-Q2)로 이루어진 입력보호회로(제1도)와 출력보호회로(제2도)로 구분할 수 있다.A general protection circuit is to protect a semiconductor device from external static electricity and the like, and is composed of a diode D 1 -D 2 , a resistor R 1 , and a MOS Q 1 -Q 2 , as shown in FIGS. 1 and 2. It can be divided into an input protection circuit (FIG. 1) and an output protection circuit (FIG. 2).
이와 같은 보호회로에 필요한 종래의 다이오드를 첨부된 도면을 참조하여 설명하면 다음과 같다.Referring to the accompanying drawings, a conventional diode required for such a protection circuit is as follows.
제 3 도는 제 1 도 및 제 2 도에서 다이오드(D1)의 구조를 나타낸 단면 및 평면도로써 제 3 도a와 같이 n형 웰(Well)(1)에 필드산화막(2)을 성장시켜 각 영역을 격리시키고, 고농도 P형 이온주입한 제 1 불순물 영역(P+)과 고농도 n형 이온주입한 제 2 불순물 영역(n+)을 형성하고 전면에 산화막(3)을 형성하고 제 1 불순물영역(P+)과 제2 불순물 영역(n+)에 콘택(Contact)을 형성하여 전극(8)을 형성한 구조로써 그 평면도는 제 3 도b와 같다.FIG. 3 is a cross-sectional view and a plan view showing the structure of the diode D 1 in FIGS. 1 and 2. The field oxide film 2 is grown in an n-type well 1 as shown in FIG. To form a first impurity region (P + ) implanted with high concentration P-type ion and a second impurity region (n + ) implanted with high concentration n-type ion implantation, an oxide film (3) is formed on the entire surface, and the first impurity region ( A contact is formed in P + ) and the second impurity region n + to form an electrode 8, and the plan view thereof is the same as in FIG. 3B.
또한, 제 4 도는 제 1 도 및 제 2 도에서 다이오드(D2)의 구조를 나타낸 단면 및 평면도로써, 제 4 도a와 같이 P형 웰(1a) 표면에 필드산화막(2)을 성장하여 각 영역을 격리시키고 이온주입으로 제 1 불순물영역(P+)과 제 2 불순물 영역(n+)을 형성하고 전면에 산화막(3)을 증착한 후 제 1 불순물영역(P+)과 제 2 불순물 영역(n+)에 콘택을 형성하여 전극(8)을 형성한 것이다. 그리고, 그 평면도는 제 4 도 b와 같다.FIG. 4 is a cross-sectional view and a plan view showing the structure of the diode D 2 in FIGS. 1 and 2. The field oxide film 2 is grown on the surface of the P-type well 1a as shown in FIG. Isolation of the region, the first impurity region P + and the second impurity region n + are formed by ion implantation, and an oxide film 3 is deposited on the entire surface, and then the first impurity region P + and the second impurity region are formed. The electrode 8 was formed by forming a contact at (n + ). The plan view is shown in FIG. 4B.
그러나, 이와 같은 종래의 보호회로의 다이오드에 있어서는 한정된 면적내에서 ESD에 충분히 견딜만한 다이오드 용량을 구현하기 어렵고, 또한 충분히 용량의 다이오드를 만들려면 많은 면적을 차지하기 때문에 고집적화에 문제가 있다.However, in the diode of such a conventional protection circuit, it is difficult to implement a diode capacity that can withstand ESD sufficiently within a limited area, and there is a problem of high integration because it takes a large area to make a diode of sufficient capacity.
본 발명은 상기와 같은 문제점을 해결하기 위해 안출한 것으로써, ESD개선 및 고집적화 하는데 그 목적이 있다.The present invention has been made to solve the above problems, the object of which is to improve the ESD and high integration.
이와 같은 목적을 달성하기 위한 본 발명을 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다.When the present invention for achieving the above object will be described in detail with reference to the accompanying drawings.
제 5 도는 본 발명의 보호회로 다이오드의 공정단면도 및 평면도로써 제 5 도a와 같이 n형 웰(1) 표면에 필드산화막을 성장하여 각 영역간을 격리시키고, 임의의 액티브 영역에 고농도 P형 이온주입으로 제 1 불순물영역(P+)을 형성하고 제 1 불순물 영역(P+)과 이웃한 액티브 영역에 고농도 n형 이온주입으로 제 2 불순물영역(n+)을 형성한다.FIG. 5 is a process cross-sectional view and a plan view of a protective circuit diode of the present invention, as shown in FIG. As a result, the first impurity region P + is formed, and the second impurity region n + is formed in the active region adjacent to the first impurity region P + by high concentration n-type ion implantation.
계속해서 전면에 산화막(3)을 증착하고 상기 제 1 불순물영역(P+) 제 2 불순물 영역(n+)상측에 콘택을 형성한다.Subsequently, an oxide film 3 is deposited on the entire surface, and a contact is formed on the first impurity region P + and the second impurity region n + .
제 5 도b와 같이 전면에 폴리실리콘(4)을 증착하고 재 결정화한 다음 제 5 도c와 같이 폴리실리콘(4)에 P형 이온(BF2) 주입하여 P형 폴리실리콘(7)을 형성한다. 제5도d와 같이 제 1 불순물영역(P+) 상측의 폴리실리콘(4) 위에 포토레지스트(P/R)로 마스크(5)를 형성하고, 선택적으로 n형 (As) 이온주입을 실시하여 n형 폴리실리콘(6)을 형성한다.As shown in FIG. 5B, polysilicon 4 is deposited on the entire surface and recrystallized, and P-type ions (BF 2 ) are implanted into the polysilicon 4 as shown in FIG. do. As shown in FIG. 5D, a mask 5 is formed of photoresist P / R on the polysilicon 4 above the first impurity region P + , and then n-type (As) ion implantation is selectively performed. An n-type polysilicon 6 is formed.
그리고, 제 5 도e와 같이 포토에치 공정으로 폴리실리콘(4)의 불필요한 부분을 제거하여 다이오드 패턴을 형성한다.Then, as shown in FIG. 5E, an unnecessary portion of the polysilicon 4 is removed by a photoetch process to form a diode pattern.
제5도f와 전면에 산화막 또는 질화막으로 절연막(3a)을 형성하고 상기 n형 폴리실리콘(6)과 P형 폴리실리콘(7) 부위에 콘택을 만들어 그 부위에 전극(8)을 형성한다.An insulating film 3a is formed of an oxide film or a nitride film on the entire surface of FIG. 5F and an oxide film or a nitride film, and contacts are formed at portions of the n-type polysilicon 6 and the P-type polysilicon 7 to form electrodes 8 thereon.
이와 같이 콘택된 평면도는 제 5 도g와 같다.The plan view thus contacted is the same as in FIG.
또한, 제 6 도는 P형 웰(1a) 표면에 제 1 불순물영역(P+)과 제 2 불순물 영역(n+)을 형성한 것으로 공정은 상기와 같다.In FIG. 6, the first impurity region P + and the second impurity region n + are formed on the surface of the P-type well 1a. The process is as described above.
이상에서 설명한 바와 같이 본 발명에 따른 보호회로의 다이오드 제조방법에 있어서는, 고농도 P형 제1불순물영역과 고농도 n형 제2불순물영역에 폴리실리콘을 증착 및 재결정화하여 선택적으로 P형 및 N형 폴리로 만듦으로 해서 면적을 늘리지 않고 몇 배 이상의 다이오드를 형성하여 고집적화를 이룰 수 있고, 기존방식에 비해 ESD 능력이 훨씬 향상되는 효과가 있다.As described above, in the diode manufacturing method of the protection circuit according to the present invention, polysilicon is deposited and recrystallized in the high concentration P-type first impurity region and the high concentration n-type second impurity region to selectively form P-type and N-type poly By making it, it is possible to achieve high integration by forming a diode several times more without increasing the area, and the ESD capability is much improved compared to the conventional method.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019920012903A KR950002204B1 (en) | 1992-07-20 | 1992-07-20 | Making method of diode for protecting circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019920012903A KR950002204B1 (en) | 1992-07-20 | 1992-07-20 | Making method of diode for protecting circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR940003101A KR940003101A (en) | 1994-02-19 |
| KR950002204B1 true KR950002204B1 (en) | 1995-03-14 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019920012903A Expired - Fee Related KR950002204B1 (en) | 1992-07-20 | 1992-07-20 | Making method of diode for protecting circuit |
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| Country | Link |
|---|---|
| KR (1) | KR950002204B1 (en) |
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1992
- 1992-07-20 KR KR1019920012903A patent/KR950002204B1/en not_active Expired - Fee Related
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| Publication number | Publication date |
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| KR940003101A (en) | 1994-02-19 |
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